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1 PAGE NO: EXP NO: 1A SIMULATION OF HALF ADDER AND FULL ADDER. DATE: AIM: To design, simulate and synthesize the Half adder and Full adder. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i ALGORITHM: 1. Start the program. 2. Declare the input and output variables. 3. Declare the output as register data type. 4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code. 5. Terminate the program. THEORY: HALF ADDER: The half adder consists of two input variables designated as Augends and Addend bits. Output variables produce the Sum and Carry. The carry output is 1 only when both inputs are 1 and,sum is 1 if any one input is 1. The Boolean expression is given by, sum = x ^ y FULL ADDER: carry = x & y A Full adder is a combinational circuit that focuses the arithmetic sum of three bits. It consists of 3 inputs and 2 outputs. The third input is the carry from the previous Lower Significant Position. The two outputs are designated as Sum (S) and Carry (C). The binary variable S gives the value of the LSB of the Sum. The output S=1 only if odd number of 1 s are present in the input and the output C=1 if two or three inputs are 1. sum = x ^ y ^ z carry= (x & y) (y & z) (x & z) PROCEDURE 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code by choosing HDL as top level source module. 3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window. 4.Perform the functional simulation using Xilinx ISE simulator

2 PAGE NO: PROGRAM: Verilog code for half adder Data Flow Modelling: module HA(a,b,sum,carry); input a,b; output sum,carry; assign sum=a^b; assign carry=a&b; endmodule BehaviouralModelling: module HA(a,b,sum,carry); input a,b; output sum,carry; (a or b) begin sum=a^b; carry=a&b; end endmodule Structural Modelling: module HA(a,b,sum,carry); input a,b; output sum,carry; xor x1(sum,a,b); and a1(carry,a,b); endmodule SYNTHESIS REPORT: Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices % Number of 4 input LUTs % Number of bonded IOBs % RTL Schematic Representation Top Level

3 PAGE NO: RTL Schematic Representation Gate Level SIMULATION REPORT

4 PROGRAM: Verilog code for full adder Data Flow Modelling: module FA(sum,carry,a,b,c); input a,b,c; output sum,carry; assign sum=a^b^c; assign carry=(a&b) (b&c) (c&a); endmodule BehaviouralModelling: module FA(sum,carry,a,b,c); input a,b,c; output sum,carry; regsum,carry; (a or b or c) begin sum=a^b^c; carry=(a&b) (b&c) (c&a); end endmodule Structural Modelling: module FA(sum,carry,a,b,c); input a,b,c; output sum,carry; wire c1,c2,c3; xor x1(sum,a,b,c); and a1(c1,a,b); and a2(c2,b,c); and a3(c3,c,a); or o1(carry,c1,c2,c3); endmodule SYNTHESIS REPORT: Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices % Number of 4 input LUTs % Number of bonded IOBs %

5 RTL Schematic Representation Top Level RTL Schematic Representation Gate Level SIMULATION REPORT RESULT: Thus the half adder and full adder were designed using Verilog HDL and it was simulate and synthesize.

6 PAGE NO: EXP NO: 1.B DATE: SIMULATION OF HALF SUBTRACTOR AND FULL SUBTRACTOR AIM: To design, simulate and synthesize the half subtractor and full subtractor. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i ALGORITHM: 1. Start the program. 2. Declare the input and output variables. 3. Declare the output as register data type. 4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code. 5. Terminate the program. HALF SUBTRACTOR: PROGRAM: Data Flow Modelling: module HS(diff,borrow,a,b); input a,b; output diff,borrow; assign diff=a^b; assign borrow=!a&b; endmodule BehaviouralModelling: module HS(diff,borrow,a,b); input a,b; output diff,borrow; regdiff,borrow; or b) begin diff=a^b; borrow=!a&b; end endmodule Structural Modelling: module HS(diff,borrow,a,b); input a,b; output diff,borrow; xor x1(diff,a,b);

7 and a1(borrow,!a,b); endmodule SIMULATION REPORT: HALF SUBTRACTOR: PROGRAM: Data Flow Modelling: module HS(diff,borrow,a,b); input a,b; output diff,borrow; assign diff=a^b; assign borrow=!a&b; endmodule BehaviouralModelling: module HS(diff,borrow,a,b); input a,b; output diff,borrow; regdiff,borrow; or b) begin diff=a^b; borrow=!a&b; end endmodule Structural Modelling: module HS(diff,borrow,a,b); input a,b; output diff,borrow; xor x1(diff,a,b); and a1(borrow,!a,b); endmodule

8 SIMULATION REPORT: SYNTHESIS REPORT: Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices % Number of 4 input LUTs % Number of bonded IOBs % FULL SUBTRACTOR: PROGRAM: Data Flow Modelling: module FS(diff,borrow,a,b,c); input a,b,c; output diff,borrow; assign diff=a^b^c; assign borrow=(!a&b) (!a&c) (b&c); endmodule BehaviouralModelling: module FS(diff,borrow,a,b,c); input a,b,c; output diff,borrow; always@(a or b or c) begin diff=a^b^c; borrow=(!a&b) (!a&c) (b&c); end endmodule Structural Modelling: module FS(diff,borrow,a,b,c); input a,b,c; output diff,borrow; wire b1,b2,b3; xor x1(diff,a,b,c); and a1(b1,!a,b); and a2(b2,!a,c); and a3(b3,b,c); or o1(borrow,b1,b2,b3);

9 endmodule SIMULATION REPORT: SYNTHESIS REPORT: Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices % Number of 4 input LUTs % Number of bonded IOBs % RESULT: Thus the half subtractor and full subtractor were designed using Verilog HDL and it was simulate and synthesize.

10 EXP NO: 1.C SIMULATION OF 4:1MUX AND 1:4 DEMUX DATE: AIM: To design, simulate and synthesize 4:1 multiplexer and 1:4 demultiplexer. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i ALGORITHM: 1. Start the program. 2. Declare the input and output variables. 3. Declare the output as register data type. 4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code. 5. Terminate the program. THEORY: MULTIPLEXER: A Multiplexer is a Combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The set of selection of a particular line is controlled by selection lines. Normally there are 2 n input lines and n selection lines whose bit combinations determine which input is selected. The 4:1 MUX has four inputs I0, I1, I2 and I3 and select lines S0 and S1. The select lines s0 and s1 are decoded to select a particular AND gate. The outputs of the AND gates are applied to a single OR gate that provides the one line output Y. DEMULTIPLEXER: A Demultiplexer is a Combinational circuit that selects binary information from one of input line and directs it to many output line. The set of selection of a particular output is controlled by selection lines. Normally there are 1 input line and 2 n selection lines whose bit combinations determine the output. The 1:4 DEMUX has one input and select lines S 0 and S1. The select lines s0 and s1 are decoded to select a particular AND gate. The outputs of the AND gates provides the various line output Y1, Y2, Y3 and Y4. PROCEDURE: 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code by choosing HDL as top level source module. Check syntax, view RTL schematic and note the device utilization summary by double. 3. Clicking on the synthesis in the process window. 4. Perform the functional simulation using Xilinx ISE simulator

11 PROGRAM: Verilog code for 4 to 1 Multiplexer module mux(en, a, y,sel); input en; input [3:0] a; input[1:0] sel; output y; reg y; always@(en or a) begin if(!en) y=1'b0; else case(sel) 2'b00 : y = a[3]; 2'b01 : y = a[2]; 2'b10 : y = a[1]; 2'b11 : y = a[0]; endcase end end module Verilog code for 1 to 4 Demultiplexer module demux(a, en, y, sel); input a; input en; output [3:0] y; input [1:0] sel; reg [3:0]y; always@(a or en) begin if(!en) y = 4'b0000; else case(sel) 2'b00 : begin y[3]=a; y[2:0]=3'b0; end 2'b01 : begin

12 end end module y[2]=a; y[3]=1'b0; y[1:0]=2'b0; end 2'b10 : begin y[1]=a; y[3:2]=2'b0; y[0]=1'b0; end 2'b11 : begin y[0]=a; y[3:1]=3'b0; end endcase SYNTHESIS REPORT: (FOR MUX) Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices % Number of 4 input LUTs % Number of bonded IOBs % RTL Schematic Representation Top Level

13 RTL Schematic Representation Gate Level SYNTHESIS REPORT: (FOR DEMUX) Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices % Number of 4 input LUTs % Number of bonded IOBs % RTL Schematic Representation Top Level

14 RTL Schematic Representation Gate Level SIMULATION REPORT: (FOR MUX) SIMULATION REPORT: (FOR DEMUX) RESULT: Thus the 4:1 mux and 1:4 demux were designed using Verilog HDL and it was simulate and synthesize.

15 EXP NO: 1.D SIMULATION OF ENCODER AND DECODER DATE: AIM: To design, simulate and synthesize the encoder and decoder. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i ALGORITHM: 1. Start the program. 2. Declare the input and output variables. 3. Declare the output as register data type. 4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code. 5. Terminate the program. THEORY: ENCODER An Encoder is a digital circuit that has 2 n (or fewer) input lines and n output lines. The output lines generate the binary the binary code corresponding to the input value. In encoder it is assumed that only one input has a value of 1 at any given time. DECODER Discrete quantities of information are represented in digital systems by binary codes. A binary code of n bits is capable of representing up to 2 n distinct elements of coded information. A decoder is a combinational circuit that converts binary information from n input lines to a maximum of 2 n unique output lines. If the n bit coded information unused combinations. The decoder may have fewer than 2 n outputs. The decoder are also called n to m line decoders, where is less than or equal to 2 n. Their purpose is to generate the 2 n (or fewer) minterms of input variables. The name decoder is also used in conjunction with other code converters such as BCD to SEVEN SEGMENT decoder. PROCEDURE: (FOR ENCODER & DECODER) 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code by choosing HDL as top level source module. 3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window. 4. Perform the functional simulation using Xilinx ISE simulator.

16 PROGRAM: Verilog code for Encoder module encoder(a, en, y); input [3:0] a; input en; output [1:0] y; reg[1:0] y; or a) begin if (!en) y = 2'b0; else case (a) end endmodule 4'b0001 : y = 2'b00; 4'b0010 : y = 2'b01; 4'b0100 : y = 2'b10; 4'b1000 : y = 2'b11; endcase Verilog code for Decoder module decoder(a, en, y); input[1:0] a; input en; output[3:0] y; reg[3:0] y; always@(en or a) begin end endmodule if(!en) y= 4'b0000; else case(a) 2'b00 : y = 4'b0001; 2'b01 : y = 4'b0010; 2'b10 : y = 4'b0100; 2'b11 : y = 4'b1000; default :y = 4'b0000; endcase

17 SYNTHESIS REPORT :( FOR ENCODER) Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices % Number of Slice Flip Flops % Number of 4 input LUTs % Number of bonded IOBs % RTL Schematic Representation Top Level RTL Schematic Representation Gate Level SYNTHESIS REPORT :( FOR DECODER) Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices % Number of 4 input LUTs % Number of bonded IOBs %

18 RTL Schematic Representation Top Level RTL Schematic Representation Gate Level SIMULATION REPORT: (FOR ENCODER)

19 SIMULATION REPORT: (FOR DECODER) RESULT: Thus the encoder and decoder were designed using Verilog HDL and it was simulated and synthesized.

20 EXP NO: 1.E DATE: SIMULATION OF 8 BIT ADDER AIM: To design, simulate and synthesize the 8 BIT adder TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i - ALGORITHM: 1. Start the program. 2. Declare the input and output variables. 3. Declare the output as register data type. 4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code. 5. Terminate the program. PROGRAM: module eightbittadd(sum,cout,a,b,cin); output [7:0]sum; output cout; input [7:0]a,b; input cin; wire c1,c2,c3,c4,c5,c6,c7; fulladd f0(sum[0],c1,a[0],b[0],cin); fulladd f1(sum[1],c2,a[1],b[1],c1); fulladd f2(sum[2],c3,a[2],b[2],c2); fulladd f3(sum[3],c4,a[3],b[3],c3); fulladd f4(sum[4],c5,a[4],b[4],c4); fulladd f5(sum[5],c6,a[5],b[5],c5); fulladd f6(sum[6],c7,a[6],b[6],c6); fulladd f7(sum[7],cout,a[7],b[7],c7); endmodule module fulladd(sum,cout,a,b,c); input a,b,c; output sum,cout; assign sum=a^b^c; assign cout=((a&b) (b&c) (c&a)); endmodule PROCEDURE: 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code by choosing HDL as top level source module. 3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window. 4. Perform the functional simulation using Xilinx ISE simulator.

21 OUTPUT: RESULT: Thus the 8-bit adder was designed using Verilog HDL and it was simulated and synthesized.

22 EXP.NO: 2 IMPLEMENTATION OF UP-DOWN COUNTER DATE: AIM: To design, simulate, synthesize and implement the up - down counter using FPGA. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i ALGORITHM: 1. Start the program. 2. Declare the input and output variables. 3. Declare the output as register data type. 4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code. 5. Terminate the program. PROCEDURE: 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code by choosing HDL as top level source module. 3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window. 4. Perform the functional simulation using Xilinx ISE simulator. THEORY: 4 - BIT COUNTER: This is a device for counter operation. It consists of a single user Flip Flop and a 3 bit Asynchronous Counter. This arrangement is for flexibility. Synchronous ones can also be used. It can be used as Module 8 Counter using only the 3 bit counter operation portion. It also provides gate reset inputs. This done can be configured as a decode counter by asynchronous recycling by using the gate reset inputs for the partial decoding. PROGRAM: module counter(q,clk,clr,up_down); input clk,clr,up_down; output[3:0]q; reg[3:0]temp; always@(posedgeclk or posedgeclr) begin if(clr) temp=4 b0000; else if(up_down) temp=temp+1 b1; else temp=temp- 1 b1;

23 end assign q=temp; endmodule Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices % Number of Slice Flip Flops % Number of 4 input LUTs % Number of bonded IOBs % Number of GCLKs % RTL Schematic Representation Top Level RTL Schematic Representation Gate Level

24 OUTPUT: RESULT: Thus the 4 bit up-down counter were designed using Verilog HDL and it was simulated, synthesized and implemented in FPGA.

25 EXP NO: 3 DATE: DESIGN AND SIMULATION OF MULTIPLIER AIM: To design, simulate and synthesize 4 bit multiplier. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i ALGORITHM: 1. Start the program. 2. Declare the input and output variables. 3. Declare the output as register data type. 4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code. 5. Terminate the program. THEORY: MULTIPLIER: In many digital signal processing applications such as correlations, convolutions, filtering and frequency analysis, one needs to perform multiplication. Multiplication algorithms will be used to illustrate methods of designing different cells so they fit into a larger structure. In order to introduce these designs, simple serial and parallel multipliers will be introduced. The appropriate tests should be consulted for more definite system architecture. The most basic form of multiplication consists of forming the products of two positive binary numbers. This may be accomplished through the traditional technique of Successive Addition and shifts in which each additive is conditional on one of the multiplier bits. The multiplication process may be viewed to consist of the following steps: 1. Evaluation of Partial Products, 2. Accumulation of the shifted partial products It should be noted that binary multiplication is equal to partial AND operations. Thus evaluation of partial products consists of the logical AND of the Multiplicand and the relevant Multiplier bit. Each column of partial products must then be added and if necessary any carry values is passed to the next column. There are a number of techniques that may be used to perform multiplication. In general the choice is based on the factors such as speed, throughput, numerical accuracy and area. As a rule, multiplication may be classified by the format, in which the words are accessed namely, 1. Serial Form 2. Serial / Parallel Form

26 3. Parallel Form PROCEDURE 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code by choosing HDL as top level source module. 3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window. 4. Perform the functional simulation using ModelSim XE simulator. 4- BIT MULTIPLIER Program: module mul(prod,a,b); input [3:0]a; input [3:0]b; wire [17:1]x; output [7:0]prod; assign prod[0]=a[0]&b[0]; HA H1(prod[1],x[1],(b[0]&a[1]),(b[1]&a[0])); FA F1(x[2],x[3],x[1],(b[1]&a[1]),(b[2]&a[0])); FA F2(x[4],x[5],x[3],(b[2]&a[1]),(b[3]&a[0])); HA H2(x[6],x[7],(b[3]&a[1]),x[5]); FA F3(x[9],x[8],x[7],(b[3]&a[2]),x[10]); FA F4(x[11],x[10],x[6],(b[2]&a[2]),x[12]); FA F5(x[13],x[12],x[4],(b[1]&a[2]),x[14]); HA H3(prod[2],x[14],x[2],(b[0]&a[2])); FA F6(prod[6],prod[7],x[8],(b[3]&a[3]),x[17]); FA F7(prod[5],x[17],x[9],(b[2]&a[3]),x[16]); FA F8(prod[4],x[16],x[11],(b[1]&a[3]),x[15]); HA H4(prod[3],x[15],x[13],(b[0]&a[3])); endmodule module HA(sum,carry,a,b); input a,b; output sum,carry; assign sum=a^b; assign carry=a&b; endmodule module FA(sum,carry,a,b,c); input a,b,c; output sum,carry; wire c1,c2,c3; assign sum=a^b^c;

27 assign c1=a&b; assign c2=b&c; assign c3=c&a; assign carry=c1+c2+c3; endmodule OUTPUT: SYNTHESIS REPORT: Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices % Number of Slice Flip Flops % Number of 4 input LUTs % Number of bonded IOBs % Number of 18X18s % Number of GCLKs % RTL Schematic Representation Top Level Location 8-bit Input Data 16-bit Result RESULT: synthesized. Thus the 8 bit multiplier was designed using Verilog HDL and it was simulated and

28 EXP NO: 4 DESIGNS AND SIMULATION OF FLIPFLOP DATE: AIM: To design, simulate and synthesize SR, D, T, and JK Flip flop TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i THEORY: SR FLIP FLOP: An SR Flip Flop is an arrangement of logic gates that maintains a stable output even after the inputs are turned off. This simple flip flop circuit has a set input (S) and a reset input (R). The set input causes the output of 0 (top output) and 1 (bottom output). JK FLIP FLOP: This simple JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a universal flip-flop circuit. The sequential operation of the JK flip flop is exactly the same as for the previous SR flip-flop with the same Set and Reset inputs. The difference this time is that the JK flip flop has no invalid or forbidden input states of the SR Latch even when S and R are both at logic 1. D FLIP FLOP: The D flip-flop tracks the input, making transitions with match those of the input D. The D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell. A D flip-flop can be made from a set/reset flip-flop by tying the set to the reset through an inverter. T FLIP FLOP: The T or "toggle" flip -flop changes its output on each clock edge, giving an output which is half the frequency of the signal to the T input. It is useful for constructing binary counters, frequency dividers, and general binary addition devices. It can be made from a J-K flip-flop by tying both of its inputs high. SR FLIP FLOP: Program: module CHARU(r, s, clk, q, q1); input r; input s; input clk; output q; output q1; reg q,q1; initial begin q=1'b0; q1=1'b1; end always@(posedge clk)

29 PAGE NO: begin case({s,r}) 2'd0:q=q; 2'd1:q=1'b0; 2'd2:q=1'b1; 2'd3:q=1'bx; endcase q1=~q; end endmodule Device utilization summary: Selected Device : 3s400tq144-4 Number of Slices: 1 out of % Number of Slice Flip Flops: 2 out of % Number of 4 input LUTs: 1 out of % Number of IOs: 5 Number of bonded IOBs: 5 out of 97 5% Number of GCLKs: 1 out of 8 12% OUTPUT: JK FLIP FLOP: Program: module CHARU(r, s, clk, q, q1); input r; input s; input clk; output q; output q1; reg q,q1; initial begin q=1'b0;

30 PAGE NO: q1=1'b1; end clk) begin case({s,r}) 2'd0:q=q; 2'd1:q=1'b0; 2'd2:q=1'b1; 2'd3:q=1'bx; endcase q1=~q; end endmodule Device utilization summary: Selected Device : 3s400tq144-4 Number of Slices: 1 out of % Number of Slice Flip Flops: 2 out of % Number of 4 input LUTs: 1 out of % Number of IOs: 5 Number of bonded IOBs: 5 out of 97 5% Number of GCLKs: 1 out of 8 12% OUTPUT: D FLIP FLOP: Program: module dff(d, clk, reset, q); input d; input clk; input reset; output reg q; clk) if(~reset)

31 begin q<=1'b0; end else begin q<=d; end endmodule Device utilization summary: Selected Device : 3s400tq144-4 Number of Slices: 1 out of % Number of Slice Flip Flops: 1 out of % Number of 4 input LUTs: 1 out of % Number of IOs: 4 Number of bonded IOBs: 4 out of 97 4% IOB Flip Flops: 1 Number of GCLKs: 1 out of 8 12% OUTPUT: T FLIP FLOP: Program: module cd(clk, t, rst_n, q); input clk; input t; input rst_n; output reg q; always@(posedge clk,negedge rst_n) begin if(~rst_n) q<=1'b0; else if(t)

32 PAGE NO: q<=~q; else q<=q; end endmodule Device utilization summary: Selected Device : 3s200tq144-4 Number of Slices: 1 out of % Number of Slice Flip Flops: 1 out of % Number of 4 input LUTs: 2 out of % Number of IOs: 4 Number of bonded IOBs: 4 out of 97 4% Number of GCLKs: 1 out of 8 12% OUTPUT: PROCEDURE: 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code by choosing HDL as top level source module. 3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window. 4. Perform the functional simulation using simulator. RESULT: Thus the flip-flops were designed using Verilog HDL and it was simulated and synthesized.

33 EX.NO:5 DESIGN AND SIMULATION OF MOORE S STATE TRANSITION DATE: CIRCUIT USING FSM TECHNIQUE AIM: To design, simulate and synthesize Moore s state transition circuit using FSM technique. TOOLS REQUIRED: SOFTWARE: XILINX ISE 9.1i ALGORITHM: 1. Start the program. 2. Declare the input and output variables. 3. Declare the output as register data type. 4. Use PROCEDURAL construct statements (behavioral modeling) for Verilog code. 5. Terminate the program. THEORY: A finite- state machine (FSM) or simply a state machine, is a mathematical model of computation. It is an abstract machine that can be in exactly one of a finite number of states any given time. The FSM can change from one state to another in response to some external inputs; the change from one state to another is called a transition. A FSM is defined by a list of its states, its initial state, and the conditions for each transition. PROCEDURE: 1. Click on the Xilinx ISE9.1i or Xilinx Project navigator icon on the desktop of PC. 2. Write the Verilog code by choosing HDL as top level source module. 3. Check syntax, view RTL schematic and note the device utilization summary by double clicking on the synthesis in the process window. 4. Perform the functional simulation using ModelSim XE simulator. PROGRAM: module fsm(clk,rst,in, out,state); input clk,rst,in; output out,state; reg[1:0]state; reg out; always@(posedge clk,posedge rst) begin if(rst) state<=2'b 00; else begin case(state)

34 2'b 00: begin if(in)state<=2'b 01; else state<=2'b 01; end 2'b 01: begin if(in)state<=2'b 11; else state<=2'b 10; end 2'b 10: begin if(in)state<=2'b 01; else state<=2'b 11; end 2'b 11: begin if(in)state<=2'b 01; else state<=2'b 10; end endcase end end clk,posedge rst) begin if(rst) out<=0; else if(state==2'b 11) out<=1; else out<=0; end endmodule

35 Device utilization summary: Selected Device : 3s50tq144-4 Number of Slices: 2 out of 768 0% Number of Slice Flip Flops: 3 out of % Number of 4 input LUTs: 3 out of % Number of IOs: 6 Number of bonded IOBs: 6 out of 97 6% Number of GCLKs: 1 out of 8 12% RESULT: synthesized. Thus the state machines were designed using Verilog HDL and it was simulated and

36 EXP NO: 6 DESIGN AND SIMULATION OF CMOS CIRCUITS DATE: AIM: To design and simulate CMOS circuits and adder circuits using the Schematic entry tool and obtain the characteristics. TOOLS REQUIRED: Micro wind THEORY: CMOS Inverter: It consists of NMOS and PMOS transistor in series connected between VDD and GND. The gate of the two transistors are shorted and connected to the input. When the input to the inverter A = 0, NMOS transistor is OFF and PMOS transistor is ON. The output is pull- up to VDD. When the input A = 1, NMOS transistor is ON and PMOS transistor is OFF. The Output is Pull-down to GND. CMOS Nor: A CMOS NOR gate circuit uses four MOSFETs just like the NAND gate, except that its transistors are differently arranged. Only in the event of both inputs being low (0) will both lower transistors be in cutoff mode and both upper transistors be saturated, the conditions necessary for the output to go high (1). CMOS Nand : The two-input NAND2 gate shown on the left is built from four transistors. The series-connection of the two n-channel transistors between GND and the gate- output ensures that the gate-output is only driven low (logical 0) when both gate inputs A or B are high (logical 1). The complementary parallel connection of the two transistors between VCC and gate-output means that the gate-output is driven high (logical 1) when one or both gate inputs are low (logical 0). PROCEDURE: 1. Draw the schematic of CMOS Inverter. 2. Perform Transient Analysis of the CMOS Inverter. 3. Obtain the output waveform CMOS INVERTER:

37 OUTPUT: CMOS NAND: OUTPUT:

38 CMOS NOR: OUTPUT:

39 FULL ADDER: OUTPUT:

40 HALF ADDER: OUTPUT: RESULT: Thus the design and simulate of CMOS circuits and adder circuits using the Schematic entry tool are completed and characteristics are obtained

41 EXP NO:7 DATE: DESIGN AND SIMULATION OF DYNAMIC CIRCUITS AIM: To design and simulate combinational circuit using the Schematic entry tool and obtainits characteristics TOOLS REQUIRED: Microwind THEORY: DYNAMIC NAND: The dynamic behaviour of the gate is simulated with SPICE. It is assumed that all inputs are set high as the clock transitions high. On the rising edge of the clock, the output node is discharged. The duration of the precharge cycle can be adjusted by changing the size of the PMOS precharge transistor. Making the PMOS too large should be avoided, however, as it both slows down the gate, and increases the capacitive load on the clock line. For large designs, the latter factor might become a major design concern as theclock load can become excessive and hard to drive. DYNAMIC INVERTER: There are two modes in which the dynamic circuits work. Precharge:When CLK= 0, the output node Out is precharged tov DD by the PMOS transistor Mp.During that time, the evaluate NMOS transistor M e is off, so that the pulldown path is disabled. Evaluation: For CLK= 1, the precharge transistor Mpis off, and the evaluation transistor Me is turned on. The output is conditionally discharged based onthe input values and the pull- down topology. If the inputs are such that the PDN conducts, then a low resistance path exists between Out and GNDand the output is discharged to GND. DYNAMIC NOR: For dynamic logic, the output transition probability does not depend on the state (history) of the inputs, but rather onthe signal probabilities only. For an n-tree dynamic gate, the output makesa 0 1transition during the precharge phase only if the output was discharged during the preceding evaluate phase. PROCEDURE: 1. Draw the schematic of CMOS Inverter. 2. Perform Transient Analysis of the CMOS Inverter. 3. Obtain the output waveform

42 DYNAMIC INVERTER: OUTPUT:

43 DYNAMIC NAND: OUTPUT:

44 DYNAMIC NOR: OUTPUT: RESULT: Thus the design and simulationof dynamic CMOS circuits using schematric entry tool are completed and characteristics are obtained

45 EXP NO:8 DESIGN AND SIMULATION OF DOMINO LOGIC CIRCUITS DATE: AIM: To design and simulate combinational circuit using the Schematic entry tool and to obtain its characteristics. TOOLS REQUIRED: THEORY: Microwind The dynamic static pair together is called domino logic. During pre charge the output of the dynamic gate is 1 and the output of the inverter is 0. During evaluation, the output of the dynamic gate id charged or discharged depending on inputs. This affects the second gate output and this will ripple through the whole chain one after the other, similar to a line of falling dominoes. Hence the name domino logic. PROCEDURE: 1. Draw the schematic of CMOS Inverter. 2. Perform Transient Analysis of the CMOS Inverter. 3. Obtain the output waveform

46 DOMINO INVERTER: OUTPUT:

47 DOMINO NAND: OUTPUT:

48 DOMINO NOR: OUTPUT: RESULT: Thus the design and simulation DOMINO logic circuits using schematric entry tool are completed and characteristics are obtained

49 EXP NO:9 DESIGN AND SIMULATION OF PSEUDO LOGIC CIRCUITS DATE: AIM: To design and simulate combinational circuit using the Schematic entry tool and to obtain its characteristics. TOOLS REQUIRED: Microwind THEORY: When input a=0, transistor N1 is off and the nominal high output voltage is Vdd. But when a is high both NMOS and PMOS is on. So there will be a direct path between Vdd and GND. The pull up network should have large resistance such that NMOS transistors can pull the ouput to zero. PROCEDURE: 1. Draw the schematic of CMOS Inverter. 2. Perform Transient Analysis of the CMOS Inverter. 3. Obtain the output waveform PSEUDO INVERTER:

50 OUTPUT: PSEUDO NAND: OUTPUT:

51 PSEUDO NOR: OUTPUT: RESULT: Thus the design and simulationof PSEUDO logic circuits using schematric entry tool are completed and characteristics are obtained

52 EXP NO: 10 DATE: LAYOUT OF CMOS CIRCUITS AIM: To draw the layout of CMOS Inverter, CMOS nand and CMOS nor using microwind. TOOLS REQUIRED: THEORY: Microwind CMOS INVERTER: CMOS Inverter consists of NMOS and PMOS transistor in series connected between VDD and GND. The gate of the two transistors are shorted and connected to the input. When the input to the inverter A = 0, NMOS transistor is OFF and PMOS transistor is ON. The output is pull-up to VDD. When the input A = 1, NMOS transistor is ON and PMOS transistor is OFF. The Output is Pull-down to GND. CMOS NAND: NAND and NOR gates are known as universal gates as any function can be implemented with them. NAND functionality can be implemented by parallel combination of PMOS and series combination of NMOS transistor. When any one of the inputs is zero, then the output will be one and when both the inputs are one the output will be low. CMOS NOR: NAND and NOR gates are known as universal gates as any function can be implemented with them. NOR functionality can be implemented by parallel combination of NMOS and series combination of PMOS transistor. When any one of the inputs is one, then the output will be one and when both the inputs are zero the output will be low. PROCEDURE: 1. Draw the CMOS Inverter layout by obeying the Lamda Rules 2. i. Poly - 2λ ii. Active contact - 2 λ iii. Active Contact Metal - 1 λ iv. Active Contact Active region - 2 λ v. Active Region Pselect - 3 λ vi. Pselect nwell - 3λ 3. Check DRC to verify whether any region violate the lamda rule. 4. Setup the extraction and extract the spice code.

53 LAYOUT DIAGRAM: CMOS INVERTER OUTPUT:

54 CMOS NAND: OUTPUT:

55 CMOS NOR: OUTPUT: RESULT: Thus the layout of CMOS Inverter using micro wind was designed and the output is verified successfully.

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