CPU Design for Computer Integrated Experiment

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1 CPU Design for Computer Integrated Experiment Shan Lu, Guangyao Li, Yijianan Wang CEIE, Tongji University, Shanghai, China Abstract - Considering the necessity and difficulty of designing a CPU for students, we simplify the MIPS instruction set for a MIPS architecture processor. Besides this, data path is given and all internal modules are compiled such as ALU module, controller module, bus module and so on. After testing and validation, the difficulty and time consumption of designing such a CPU are proved possible for students. As a result, a suit of experiment platforms based on CPU is born. It not only provides students a chance to have their own processor, but also provides us with a platform for further experiment, such as OS and fundamentals of compilation. Key words: MIPS, processor, integrated experiment 1 Introduction Nowadays, most students whose major are CS have little understanding of the principle of CPU works, and have little practice. So these students can hardly grasp the main point of principle computer organization. To solve this problem, a simple student-oriented CPU is born. This design is used to help students to learn more about the computer configuration in practice. What s more, this CPU also provides a platform for the following course of OS and fundamentals of compilation. Thanks to the open instruction model, MIPS instruction set [1] is chosen. In this model, subscribers are encouraged to design your own CPU in accordance with their own demands. Besides this, MIPS belongs to the RISC architecture, and the instructions are simple and few. So it is a good idea to choose MIPS instruction to structure our CPU. It is easy for students to see the achievement in a short term. Verilog [2] is chosen to design this CPU because it is similar to C, and majority of students have C programming foundation. What s more, there are enough choices for you to design, such as ALU module, controller module, I/O module [3], storage module and so on. In this article, the designs and verification of all modules are involved. As a result, this CPU design has achieved the expected effect. 2 The Design of MIPS Processor 2.1 MIPS Instruction Set According to Harvard structure, data are stored separately from instruction. Figure 1 shows the five steps of execute a MIPS instruction in a single cycle. The five steps are IF, ID, EX, MEM, W B. (1) IF step, instruction address is taken from PC Register(PC_Reg) to identify the current execution instruction and sent to Instruction Memory(Instr_Mem) to get the binary code of the instruction through Address Bus. (2) ID step, instruction code is decoded by Controller to get the control signal. According to the different instruction type, the corresponding register value is obtained from the Register File(Reg File). (3) EX step, the operand and the control signal are sent to the ALU for arithmetical or logical operation or the BS module for shifting. (4) MEM step, according to different MIPS instruction, the ALU result will be sent to the bus controller for arbitration. The bus controller will decide the destination of data such as Data Memory(Data_Mem) or GPIO. GPIO module realizes the responsibility of cache to solve the speed relation between internal unit and peripheral unit. (5) WB, according to the control signal, write-back mux module will decide whether the data writes back to the Register File(Reg_File).

2 IF ID EX MEM WB Controller ALU Bus Controller PC Reg Instr Mem WriteBack Mux Reg File BS Data Mem GPIO Figure 1 process and modules of MIPS Figure 2 MIPS processor data path The 30 most common used instructions as shown in Table 1 include the arithmetical operation, logical operation, branch, store instruction and so on. This set meets all the demands we need in the following design. MIPS instruction sets include three types: R-type, I-type and J-type. (1) R-type means register instructions. Two operands are taken from Register File, and the result is also sent to the Register File. (2) I-type means immediate instructions. These instructions fetch 16-bit immediate as an operand. (3) J-type means jump instructions. These instructions fetch 26-bit immediate as the destination address which will be stored into PC Register. of MIPS processor is designed as Figure 2. Pin information and wiring information is designed as well according to the statement in section ALU design ALU module typically handles logical and arithmetical operation. The operation between operand A and B is controlled by ALU control signal(alucontrol). Afterwards ALU result and zero flag can be fetched from the output pins. Figure 3 shows the pin signal and Table 2 shows the detailed information of pins. 2.2 MIPS CPU Design Data Path Design After analyzing the MIPS instruction format and its [4, 5] classification, referring to the relevant CPU design and the MIPS modules defined in Figure 1, the data path Figure 3 ALU pin signal

3 Table 1 MIPS instruction set and its format Mnemonic Symbol Format Sample Bit # R-type op rs rt rd shamt func add rs rt rd add $1,$2,$3 addu rs rt rd addu $1,$2,$3 sub rs rt rd sub $1,$2,$3 subu rs rt rd subu $1,$2,$3 and rs rt rd and $1,$2,$3 or rs rt rd or $1,$2,$3 xor rs rt rd xor $1,$2,$3 nor rs rt rd nor $1,$2,$3 slt rs rt rd slt $1,$2,$3 sltu rs rt rd sltu $1,$2,$3 sll rt rd shamt sll $1,$2,10 srl rt rd shamt srl $1,$2,10 sra rt rd shamt sra $1,$2,10 sllv rs rt rd sllv $1,$2,$3 srlv rs rt rd srlv $1,$2,$3 srav rs rt rd srav $1,$2,$3 jr rs jr $31 Bit # I-type op rs rt immediate addi rs rt immediate addi $1,$2,100 addiu rs rt immediate addiu $1,$2,100 andi rs rt immediate andi $1,$2,10 ori rs rt immediate andi $1,$2,10 xori rs rt immediate andi $1,$2,10 lw rs rt immediate lw $1,10($2) sw rs rt immediate sw $1,10($2) beq rs rt immediate beq $1,$2,10 bne rs rt immediate bne $1,$2,10 slti rs rt immediate slti $1,$2,10 sltiu rs rt immediate sltiu $1,$2,10 Bit # J-type op address j address j jal address jal 10000

4 Table 2 ALU pin signal and function a(31:0) operand a of arithmetical or logical operation b(31:0) operand b of arithmetical or logical operation alucontrol(3:0) control signal, operation type result(31:0) ALU result zero zero flag, if it is effective, ALU result is zero Controller Design During the five steps of implementing MIPS instructions, signals from controller control the data flow in EX step, Mem step and WB step. Controller receives the machine code from instruction register, and then decodes it into control signal to control others modules, such as ALU module, BS module and so on. Figure 4 shows the pin signal and Table 3 shows the detailed information of pins. Figure 4 controller pin signal Table 3 controller pin signal and function funct(5:0) funct filed of instruction ImmHigh(7:0) data bus, controller get the high 8-bit of immediate to identify the data direction, to I/O or memory zero zero flag alucontrol(3:0) ALU control signal bscontrol(2:0) BS control signal aluormem data strobe signal, if it is effective, ALU result is sent to register, else data from memory is sent to register dstreg address strobe signal, if it is effective, Instr are set as destination register address, else bits of instructions are set as destination register address jal data or address strobe signal, when signal is effective, the value of PC+4 is sent to the NO.31 register jmp PC strobe signal, when signal is effective, the jump location is sent to PC register jorjr PC strobe signal, when signal is effective, the jump location is sent to PC register muxtobs bit strobe signal, if it is effective, the bit is the value which is stored in the register, which address is bits of instructions, else the immediate in the 10-6 bits of instruction is sent to BS as the bit to be shifted pcsrc branch signal readio I/O read signal readmem memory read signal rtorimm data strobe signal, if it is effective, ALU operand is the value from register, else 15-0 bits of instruction writebackorbs data strobe signal, if it is effective, BS result is written back writeio I/O write signal writemem memory write signal writereg register write signal zeroorsign extend control signal, if it is effective, the 15-0 bits will extend by zero, else the 15-0 bits will extend by symbol

5 2.2.4 BS Module Design This CPU is a single cycle processor. In this type of process, shift instruction is demanded to complete in a single cycle. Nowadays, there are three popular encoding. After analyzing these decoding, full-encoding [6] is chosen to realize the BS module. For 32-bit barrel shifter, it demands 5-bit control signal to co mplete logical shift, arithmetical shift and cyclic shift. Figure 5 shows the pin signal and Table 4 shows the detailed information of pins. Figure 5 barrel shifter pin signal Table 4 barrel shifter pin signal and function Bit(4:0) bit to shift Sin(31:0) operand type(2:0) type Sout(31:0) BS result Bus Module Bus module provides the unified writing and reading management of I/O and memory. The data can be distributed and I/O selected signal and port address can be given by the I/O or memory read-write signal. Figure 6 shows the pin signal and Table 5 shows the detailed information of pins. Table 5 bus module pin signal and function address(15:0) address bus, the low 16-bit of ALU result is set as the address of memory or I/O iodate(15:0) data bus, the data from I/O is sent to bus controller mdata(31:0) data bus, data from memory is sent to bus controller wdata(31:0) data bus, data from register is sent to bus controller readio I/O read signal readmem memory read signal writeio I/O write signal writemem memory write signal portaddr(3:0) port address, the low 4-bit of I/O address is set as port address rdata(31:0) data bus, I/O or memory read signal decide to read I/O data or memory data write_data(31:0) data bus, I/O or memory write signal decide to write data to I/O or memory LEDCtrl LED strobe signal Register Module Register module(figure 7) consists of 32 registers. Among those registers, No.31 register is used to store return address, the other registers are general-purpose register. During the five steps of implementing MIPS instructions, register module typically handles EX step and WB step. During EX step, operand is fetched from register and sent to ALU module. During WB step, the data is written to the register by the write register signal. Figure 6 bus module pin signal Figure 7 register module pin signal

6 S T E P. A S T E P. B C o n t r o l l o r T e s t i n g P C I n s t r u c t i o n B u s C o n t r o l M e m o r y & R e g A L U B S G P I O Figure 8 module testing process Figure 9 TestBench code Table 6 register module pin signal and function ra1(4:0) address bus, the bits of instruction is send to register as register address ra2(4:0) address bus, the bits of instruction is send to register as register address wa3(4:0) address bus, the data written back is sent to register as register address wd3(31:0) data bus, the data written back is sent to register as register data clk clock signal we3 register write signal rd1(31:0) data bus, the data is read from registers according to the ra1 address rd2(31:0) data bus, the data is read from registers according to the ra2 address 3 Testing and Verification RTL simulation consists of two parts, module testing and system testing. This simulation needs complete testbench, and output response for observation. You can determine whether the design reach the expected function in accordance with these information 3.1 Module Testing This testing is divided into two parts as shown in Figure 8. Step A verifies the correctness of PC to fetch the current instruction and next instruction. That is, to verify whether the MIPS processor fetches the machine code which PC points to, correctly parses the func filed, op filed and ImmHigh field of instruction and sends the binary code into right pin. Step B use QtSpim to generate the machine code of test program. The test programs are required to cover the routine testing and marginal testing.

7 All test programs are run in Modelsim. You can determine whether the design reach the desired function with the help of output pin signal. 3.2 System Testing Write testbench to test the MIPS processor by black box testing. The test which involves all instructions includes logical operation test, arithmetical operation test, GPIO test and so on. Figure 9 shows the testbench code of jump instruction which contains all J-type instruction, jr instruction and parts of I-type instruction such as beq instruction. With the help of instruction execute order and the registers data generated by Modelsim, we can determine whether the design reach the desired function or not. 4 Conclusion A student-oriented MIPS processor is designed to recognize and execute MIPS instruction set correctly. Besides this, as supplements, interface information and function explanation are given. Tests show that the difficulty and time factor are considered to be possible for students to design such a CPU. What s more, the implement of this MIPS processor provide the computer integrated experiment a visual testbed. In the process of this design, students can learn more about the computer configuration in practice. Up till now, we have completed the design and implementation of MIPS processor. The future work is to improve and enlarge the processor, and to program some software such as BIOS, Mini OS or Compiler beyond it. 5 Reference [1] MipsMIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set,, MIPS Technologies, Inc. [2] Yuwen Xia, Verilog Digital System Design Tutorial. 2008, Beijing University of Aeronautics and Astronautics Press. [3] XILINX, XPS General Purpose Input/Output(GPIO) (v2.00a). [4] David Money Harris, Sarah L. Harris, Digital Design and Computer Architecture. [5] Quansheng Yang, The Computer System Comprehensive Design Course. 2008, Tsinghua University Press. [6] Field Programmable Gate Array. 1999, Atmel Corporation.

Computer Architecture Experiment

Computer Architecture Experiment Jiang Xiaohong College of Computer Science & Engineering Zhejiang University Architecture Lab_jxh 1 Topics 0 Basic Knowledge 1 Warm up 2 simple 5-stage of pipeline CPU