Topics. Midterm Finish Chapter 7

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1 Lecture 9

2 Topics Midterm Finish Chapter 7

3 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory address. The 32 outputs are connected to the eight OR gates for 32 x 8 = 256 internal connections.

4 Read-Only Memory

5 7.6 Programmable Logic Array (PLA) Similar in concept to PROM, except PLA does not provide full variable decoding and doesn t generate all minterms Decoder replaced by an array of programmable AND gates that generate input product terms Mask or field programmable F 1 = AB + AC + A BC F 2 = (AC + BC) minterms Output inverted when XOR connected to a 1 (x 1 = x ) Output unchanged when XOR connected to a 0 (x 0 = x)

6 7.7 Programmable Array Logic (PAL) Fixed OR array and programmable AND array Easier to program than a PLA Not as flexible as a PLA

7 7.7 Programmable Array Logic (PAL) Consider: w(a, B, C, D) = (2, 12, 13) = ABC + A B CD x(a, B, C, D) = (7, 8, 9, 10, 11, 12, 13, 14, 15) = A + BCD y(a, B, C, D) = (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) = A B + CD + B D z(a, B, C, D) = (1, 2, 8, 12, 13) = ABC + A B CD + AC D + A B C D = w + AC D + A B C D

8 7.7 Programmable Array Logic (PAL)

9 7.8 Sequential Programmable Devices Several types Sequential (or simple) Programmable Logic Device (SPLD) Complex Programmable Logic Device (CPLD) Field Programmable Gate Array (FPGA)

10 Sequential (or simple) Programmable Logic Device (SPLD) Modified PAL or PLA The SPLD includes FFs in addition to the AND-OR array Outputs taken from OR gates or from FFs. Basic macro-cell logic Same AND-OR PLA array FF output fed back to programmable AND gate to provide present-state conditions

11 Complex Programmable Logic Device (CPLD)

12 Xilinx FPGAs Basic Spartan and earlier devices CLB = Configurable Logic Block IOB = I/O Block

14 Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice contains two Look Up Tables (LUTs) Implements logic functions Can be configured as 16x1 memory (RAM16) Can be configured as a 16-bit shift register (SRL16) Each slice contains two storage elements Implements flip flops or latches Each slice contains two Multiplexers

15 Spartan 3E Architecture

16 Spartan 3E Architecture Two left slices of CLB supports both logic and memory functions Two right slices of CLB supports logic only SLICEL smaller and faster

17 Simplified SLICEL diagram

18 Spartan 3E Architecture LUTs in SLICEM can be programmed as distributed 16x1 RAM Can be configured to store larger amounts 16x4, 32x2, 64x1 in one CLB Can also be configured as dual port using two LUTs Same data written to both 16x1 memories Independent read addresses and outputs

19 Spartan 3E Architecture LUTs The F and G LUTs in a slice have four logic inputs (A1-A4) and a single output (D). Any four variable Boolean logic operation can be implemented using one LUT.

20 Spartan 3E Architecture Wide Multiplexer Each slice has two mutliplexers FiMUX multiplexes the two CLB inputs F5MUX multiplexes the two LUTs in a slice. See figure 20 of Spartan 3E datasheet for feedback routing

21 Spartan 3E Architecture Carry and Arithmetic Logic Full Adder Cin A B Sum Cout

22 Spartan 3E Architecture Multiplication Useful for small multipliers Use dedicated 18x18 multiplier blocks for larger

23 Block RAM Spartan-3E devices incorporate 4 to 36 dedicated block RAMs Block RAM synchronously stores large amounts of data while distributed RAM is better suited for buffering small amounts of data anywhere along data paths Block RAM initial values are configurable

24 Interconnect Resources Three types of general purpose interconnect: Single length lines (SLL) Double length lines (DLL) Long lines A grid of horizontal and vertical SLLs connects an array of switch boxes that provide a reduced number of connections between signal paths within each box Each CLB has a pair of tri-state buffes that can drive signals onto the nearest horizontal line

25 Programmable Interconnect Points (PIPs)

26 IOB

27 Spartan 3E Architecture Storage Elements Programmable as either a D-type FF or latch

28 Sequential Logic (i.e. Registers, FF s) Reset CLK or posedge RST) if (RST) Q <= 1'b0; else Q <= (F G H) & (A (B & C & D & E)); More difficult timing analysis Less than optimal optimization by the synthesis tool

29 Sequential Logic (i.e. Registers, FF s) Reset (cont.) CLK) if (RST) Q <= 1'b0; else Q <= (F G H) & (A (B & C & D & E));

30 Spartan 3E Architecture Shift Registers Each SLICEM LUT can be programmed as a 16-bit shift register Delay data from 1 to 16 clock cycles w/o using FFs. Can cascade to form larger shift registers The four SLICEM LUTs of a CLB can be combined to produce a 64 bit shift register The CLB FF can be used for one more shift delay

31 Digital Clock Managers (DCMs) DCMs provide flexible, complete control over clock frequency, phase shift and skew. Uses Delay-Locked Loop (DLL) Supports Clock Skew Elimination Clock skew increases setup/hold time requirements Frequency Synthesis Wide range of different frequencies derived from incoming clock Phase Shifting Shifts the phase of all output clock signals w.r.t. the input clock

32 Delay Locked Loop (DLL)

33 Instantiation of Design Elements Inferred or I1 or S) begin if (S==0) O = I0; else O = I1; Explicit MUXF5 MUXF5_inst (.O(O), // Output of MUX to general routing.i0(i0), // Input (tie directly to the output of LUT4).I1(I1), // Input (tie directly to the output of LUT4).S(S) // Input select to MUX Library guide for MUXF5 recommends inferred but some design elements can only be explicitly instantiated (e.g. KEEPER)

34 Initialization Set, Resets, and Synthesis Optimization Xilinx FPGA devices have abundant flip-flops. All architectures support an asynchronous reset for those registers and latches. Even though this capability exists, Xilinx does not recommend that you code for it. Using asynchronous resets may result in: More difficult timing analysis Less optimal optimization by the synthesis tool The timing hazard which an asynchronous reset poses on a synchronous system is well known. Less well known is the optimization trade-off which the asynchronous reset poses on a design. Global Set/Reset (GSR) All Xilinx FPGA devices have a dedicated asynchronous reset called Global Set/Reset (GSR). GSR is automatically asserted at the end of FPGA configuration, regardless of the design. For gate-level simulation, this GSR signal is also inserted to mimic this operation to allow accurate simulation of the initialized design as it happens in the silicon. Adding another asynchronous reset to the actual code only duplicates this dedicated feature. It is not necessary for device initialization or simulation initialization. Source: Xilinx Synthesis and Simulation Deign Guide (UG626)

35 Initialization Initial State of the Registers and Latches FPGA flip-flops are configured as either preset (asynchronous set) or clear (asynchronous reset) during startup. This is known as the initialization state, or INIT. The initial state of the register can be specified as follows: If the register is instantiated, it can be specified by setting the INIT generic/parameter value to either a 1or 0, depending on the desired state. For more information, see the Libraries Guides. If the register is inferred, the initial state can be specified by initializing the VHDL signal declaration or the Verilog reg declaration as shown in the following coding examples. Initial State of the Registers and Latches Verilog Coding Example One reg register1 = 1 b0; // specifying regsiter1 to start as a zero reg register2 = 1 b1; // specifying register2 to start as a one reg [3:0] register3 = 4 b1011; //specifying INIT value for 4-bit register Initial State of the Registers and Latches Verilog Coding Example Two Another possibility in Verilog is to use an initial statement: reg [3:0] register3; initial begin register3= 4 b1011; end Note: Not all synthesis tools support this initialization Note: Your simulation will match your implementation if you use this coding style. Otherwise your simulation will initialize registers to X whereas the registers will initialize to 0 on the FPGA. Source: Xilinx Synthesis and Simulation Deign Guide (UG626)

36 ECE2411 Summer 2016 Mid-Term Study guide 1 s and 2 s complement Know how to calculate Binary addition/subtraction using 2 s complement Parity Even and Odd DeMorgan s Be able to convert sum of products (SOP) to expression using only NAND or NOR gates K-Map Be able to simplify a given equation with and without don t cares Simple combinational circuit Truth table Schematic for equation Verilog code Simple sequential circuit Truth table Schematic Verilog code

37 Homework Due October 27

Topics. Midterm Finish Chapter 7

Topics. Midterm Finish Chapter 7 Lecture 9 Topics Midterm Finish Chapter 7 Xilinx FPGAs Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice