VERILOG QUICKSTART. Second Edition. A Practical Guide to Simulation and Synthesis in Verilog

Transcription

1 VERILOG QUICKSTART A Practical Guide to Simulation and Synthesis in Verilog Second Edition

2 VERILOG QUICKSTART A Practical Guide to Simulation and Synthesis in Verilog Second Edition James M. Lee SEVA Technologies KLUWER ACADEMIC PUBLISHERS New York / Boston / Dordrecht / London / Moscow

3 ebook ISBN: Print ISBN: Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print 1999 Kluwer Academic / Plenum Publishers New York All rights reserved No part of this ebook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's ebookstore at:

4 TABLE OF CONTENTS LIST OF FIGURES LIST OF EXAMPLES LIST OF TABLES 1 INTRODUCTION Framing Verilog Concepts The Design Abstraction Hierarchy Types of Simulation Types of Languages Simulation versus Programming HDL Learning Paradigms Where To Get More Information Reference Manuals Usenet Talk Verilog 2 INTRODUCTION TO THE VERILOG LANGUAGE Identifiers Escaped Identifiers White Space Comments Numbers Text Macros Modules Semicolons Value Set Strengths Numbers, Values, and Unknowns xii xiv xx

5 vi 3 STRUCTURAL MODELING Primitives Ports Ports in Primitives Ports in Modules Instances Hierarchy Hierarchical Names Connect by Name Top-Level Modules You Are Now Ready To Run Your First Simulations Exercise 1 The Hello Simulation Exercise 2 The 8-Bit Hierarchical Adder Verilog Quickstart BEHAVIORAL MODELING Starting Places for Places for Blocks of Behavioral Code The initial Keyword The always Keyword Delays begin-end Blocks fork-join Blocks System Tasks for Printing Out Results What Is a System Task? $display and Its Relatives Other Commands To Print Results Writing to Files Setting the Default Radix Exercise 3 Printing Out Results from Wires Buried in the Hierarchy Special Characters Suppressing Spaces in Your Output Data Objects in Verilog Nets Ranges Implicit Nets Registers Memories Initial Value of Regs Integers and Reals Time and Realtime Parameters Events Strings Multi-Dimensional Arrays Accessing Words and Bits of Multi-Dimensional Arrays

6 vii Procedural Assignments Ports and Registers 5 OPERATORS Binary Operators Unary Operators Reduction Operators Ternary Operator Equality Operators Concatenations Logical versus Bit-wise Operations Operations That Are Not Legal on Reals Working with Strings Combining Operators Sizing Expressions Signed Operations Signed Constants 6 WORKING WITH BEHAVIORAL MODELING Continuous Assignment Event Control The always Block for Combinatorial Logic Event Control Explained The if Statement The case Statement Exercise 4 Using Expressions and case Loops The forever Loop The repeat Loop The while Loop The for Loop Procedural Continuous Assignments tasks functions Exercise 5 Functions and Continuous Assignments A Reminder about Ports and Registers Modeling with inout Ports Named Blocks The disable Statement When is a Simulation Done? 7 USER-DEFINED PRIMITIVES

7 viii Combinatorial UDPs Optimistic Mux Pessimistic Mux The Gritty Details Sequential UDPs UDP Instances The Final Details Exercise 6 Using UDPs 8 PARAMETERIZED MODULES n-bit Mux n-bit Adder n By m Mux n By m Ram Using Parameterized Modules Parameter Passing by Name Parameter Passing By Order Parameter Passing by Names List Values of Parameters in Module Instances 9 STATE MACHINES State Machine Types State Machine Modeling Style State Encoding Methods Default Conditions Implicit State Machines Registered and Unregistered Outputs Factors in Choosing a State Machine Modeling Style 10 MODELING TIPS Modeling Combinatorial Logic Combinatorial Models Using Continuous Assignments Combinatorial Models Using the always Block and regs Combinatorial Models Using Functions Modeling Sequential Logic Sequential Models Using always Sequential Models Using initial Sequential Models Using tasks Modeling Asynchronous Circuits Modeling a One-Shot Modeling Asynchronous Systems Special-Purpose Models Verilog Quickstart

8 ix Two-Dimensional Arrays Z-Detectors Multiplier Examples A Proven, Successful Approach to Modeling 11 MODELING STYLE TRADE-OFFS Forces That Influence Modeling Style Evolution of a Model Modeling Style and Synthesis Is It Synthesizable? Learning From Other People s Mistakes When To Use UDPs Blocking and Non Blocking Asssignments 12 TEST BENCHES AND TEST MANAGEMENT Introduction to Testing Model Size versus Test Volume Functional Testing Regression Testing Self-Checking Test Benches Sign-Off System Test versus Unit Tests Response-Driven Stimulus Test Benches for Inouts Loading Files into Verilog Memories Test Benches with No Test Vectors Using a Script To Run Test Cases Modeling BIST The Surround and Capture Method 13 COMMON ERRORS Mismatched Ports Missing or Incorrect Declarations Missing Registers Missing Widths Reversed Ranges Improper Use of Procedural Continuous Assignments Missing initial or always Blocks Zero-Delay always Loops initial Instead of always Missing Initialization Overly Complex Code Unintended Storage

9 x Verilog Quickstart Timing Errors Negative Setup Time Zero-Delay Races 14 DEBUGGING A DESIGN Overview of Functional Debugging Where Are the Errors? Universal Techniques Printing Out Messages I am here. Values The Log File Using Waveforms Interactive Debugging Going Interactive The Prompts Special Keys in Interactive Mode Command History The Key File Traversing and Observing Back-Tracing Fan-In Using force and release Waveforms, Graphic User Interfaces, and Other Conveniences Catching Problems Later in a Simulation Isolating Differences in Models Summary of Debugging Appendix A GATE LEVEL DETAILS Primitive Descriptions Logic Gates AND NAND OR NOR XOR XNOR Buffers BUF NOT BUFIF0 BUFIF1 NOTIF0 NOTIF1 PULLDOWN

10 xi PULLUP Switches NMOS and RNMOS PMOS and RPMOS CMOS and RCMOS TRAN and RTRAN TRANIF0 and RTRANIF0 TRANIF1 and RTRANIF1 Instance Details Delays Delay Units Printing Out Time and the Timescale Strengths Displaying strengths with %v Strength reduction of switch primitives Appendix B EXAMPLE SUMMARY INDEX

11 xii Verilog Quickstart LIST OF FIGURES Figure 1-1 Design Abstraction Hierarchy Figure 1-2 Gate-Level Model Mux Schematic Figure 2-1 Number Format Figure 2-2 The Mux Example Figure 2-3 Three-State Buffer Figure 2-4 Two Three-State Buffers Figure 3-1 AND Gate Primitives Figure 3-2 Gate-Level Model Mux Schematic Figure 3-3 Connecting Two Muxes Figure 3-4 Hierarchical 4-Bit Mux Figure 3-5 Mux4 Hierarchy Expanded Figure 3-6 Syntax for Connect by Name Figure 3-7 Adder Schematic Figure 3-8 Adder2 Schematic Figure 3-9 Adder4 Schematic Figure 3-10 Adder8 Schematic Figure 6-1 Connecting 4 Registers to a Wire Figure 6-2 Rotate Left Figure 6-3 Logical Shift Left with 0 Fill Figure 6-4 Rotate Right Figure 6-5 Logical Shift Right with 0 Fill Figure 6-6 ALU Test Vector File alu_test.vec Figure 6-7 Relationships of Ports and Regs Figure 7-1 Adder Using Five Built-In Primitives Figure 7-2 Adder Using Two UDPs Figure 9-1 Moore State Machine Figure 9-2 Mealy State Machine Figure 10-1 State Diagram for Alarm System Figure 11-1 Forces That Act on Modeling Style Figure 11-2 Synthesizablility Flowchart Figure 12-1 Test Bench for an inout Figure 12-2 Logic Surrounded by BIST Figure 12-3 Surround and Capture Method Figure A-1 AND Gate Figure A-2 NAND Gate Figure A-3 OR Gate Figure A-4 NOR Gate Figure A-5 XOR Gate Figure A-6 XNOR Gate Figure A-7 BUF Gate Figure A-8 NOT Gate Figure A-9 BUFIF0 Gate

12 xiii Figure A-10 BUFIF1 Gate Figure A-11 NOTIF0 Gate Figure A-12 NOTIF1 Gate Figure A-13 Pulldown Figure A-14 Pullup Figure A-15 NMOS or RNMOS Transistor Figure A-16 PMOS or RPMOS Transistor Figure A-17 CMOS or RCMOS Transistor

13 xiv Verilog Quickstart LIST OF EXAMPLES Example 1-1 Abstract Model of a Phone Example 1-2 Verilog for Gate-Level Mux Example 2-1 Simple Hello Module Example 2-2 Hello Module without White Space Example 2-3 Hello Module with Extra White Space Example 2-4 Illegal Use of White Space Example 2-5 Comments Example 2-6 Numbers Example 2-7 Specifying a Text Macro Example 2-8 Using a Text Macro Example 2-9 Gate-Level Mux Verilog Code Example 3-1 Verilog Code for the 2-Input and 4-Input AND Gates Example 3-2 Verilog for Gate-Level Mux Example 3-3 Hierarchical 2-Bit Mux Example 3-4 Hierarchical 4-Bit Mux Example 3-5 Hierarchical Names Example 3-6 Mux Connected by Name Example 3-7 Hello Verilog Example 3-8 Adder Test Module Example 4-1 An initial Block Example 4-2 An always Block Example 4-3 Three initial Statements Example 4-4 Three initial Statements with Delay Example 4-5 Simple begin-end Block Example 4-6 begin-end Block with Delay Example 4-7 Multiple begin-end Blocks Example 4-8 fork-join Blocks Example 4-9 Combining begin-end and fork-join Blocks Example 4-10 Displaying a String Example 4-11 Displaying a Single Value Example 4-12 Displaying Multiple Values Example 4-13 Using Format Specifiers with $display Example 4-14 Two $display Statements Example 4-15 Combining $write and $display Example 4-16 Writing to a File Example 4-17 Writing to Multiple Files Example 4-18 $display with $time Example 4-19 Leading Spaces in $monitor with $time Example 4-20 Spaces used to print an 8-Bit value Example 4-21 Suppressing Leading Spaces and Zeroes Example 4-22 Net Declarations Example 4-23 Incorrect Net Declaration

14 xv Example 4-24 Setting Default Net Type Example 4-25 Register Declarations Example 4-26 Selecting Bits and Parts of a Register Example 4-27 Memory and Register Declarations Example 4-28 Selecting Bits in Registers and Words in Memories Example 4-29 Reg Declaration with Initialization Example 4-30 Declaring Integers and Reals Example 4-31 Declaring Variables of Type time Example 4-32 Parameters Example 4-33 Events Example 4-33 Strings Example 4-35 Multi-Dimensional Arrays of Nets Example 4-36 Multi-Dimensional Arrays of Regs Example 4-37 Accessing Multi-Dimensional Arrays Example 4-38 Simple Procedural Assignments Example 4-39 Procedural Assignments with fork-join Example 4-40 fork-join with Intra-assignment Delays Example 4-41 fork-join with Multiple Delays Example 4-42 fork-join with Simplified Delays Example 4-43 Effect of Intra-assignment Delays on Time Flow Example 4-44 Nonblocking Assignments Example 4-45 Output as a Register Example 5-1 Using Operators Example 5-2 Distinguishing between Bit-wise and Logical Operators Example 5-3 Using Reduction Operators Example 5-4 Ternary Operator Example 5-5 Using the Ternary Operator for a Three-State Buffer Example 5-6 Module To Test an Operator Example 5-7 Concatenations Example 5-8 Bit-wise and Logical operations Example 5-9 Operators and Strings Example 5-10 Combinations of operators for Exclusive-NOR Example 5-11 Signed Declarations Example 5-12 Signed Constants Example 5-13 Effect of Signed Constants Example 6-1 Three-State Buffer Using a Continuous Assignment Example 6-2 A 128-Bit Adder in a Continuous Assignment Example 6-3 Continuous Assignment Multiplier Example 6-4 Connecting Four Registers to a Wire Example 6-5 Alternate Form of Continuous Assignment Example 6-6 Many Forms of Continuous Assignments Example 6-7 Waiting for an Event Example 6-8 Mux Using Continuous Assignment Example 6-9 Mux Using always Block Example 6-10 Always Block Using Comma

15 xvi Verilog Quickstart Example 6-11 Combinatorial Always Block Example 6-12 Incorrect Mux Example 6-13 Using the event Data Type Example 6-14 Using Events To Simplify Modeling Example 6-15 always Explained Example 6-16 Using wait Example 6-17 Using wait To Detect an Unknown Example 6-18 Using always To Detect an Unknown Example 6-19 Simple if Example 6-20 if with else Example 6-21 Nested if with else Example 6-22 The case Statement Example 6-23 case Matching x and z Example 6-24 Using casez Example 6-25 Test Bench for the ALU Example 6-26 Oscillator Using always Example 6-27 Oscillator Using forever Example 6-28 Repeating Hello Verilog Example 6-29 Using repeat in a State Machine Example 6-30 A while Loop Example 6-31 A Simple for Loop Example 6-32 A for Loop with Expressions Not Referencing the Same Variable Example 6-33 A Simple Flip-Flop Example 6-34 A Flip-Flop with a Bad Reset Example 6-35 A Flip-Flop with Reset Example 6-36 A Flip-Flop with Incorrect Set and Reset Example 6-37 A Flip-flop with Correct Set and Reset Example 6-38 Incorrect Mux Example 6-39 Mux with PCA Example 6-40 Hello Verilog Tasks Example 6-41 task with Inputs, Outputs, and External References Example 6-42 Effect of task Port Size Example 6-43 Accessing a task Local Variable from Outside the task Example 6-44 Task Local and Module Items with the Same Name Example 6-45 Read Cycle task Example 6-46 Re-Entrant Task Example 6-47 Count Bits Function Example 6-48 Mux with Function and Continuous Assignment Example 6-49 Divide Function Returning Two 8-Bit Values Example 6-50 inout Port Connected to a Register Example 6-51 Register with Controllable Connection to inout Port Example 6-52 Named Blocks Example 6-53 The disable Statement Example 6-54 disable Used To Model Reset Example 6-55 Controlling When a Simulation Finishes

16 xvii Example 7-1 Optimistic Mux UDP Example 7-2 Pessimistic Mux UDP Example 7-3 One-Line UDP Example 7-4 Level-Sensitive D Latch Example 7-5 Edge-Sensitive D Flip-Flop Example 7-6 Flip-Flop Using Explicit Edge Definitions Example 7-7 initial Block in a UDP Example 8-1 parameter Statements Example 8-2 n-bit Wide 4-to-1 Mux Example 8-3 Parameterized Width Adder Example 8-4 Mux with Parameterized Width and Number of Inputs Example 8-5 Parameterized RAM Example 8-6 The defparam Statement Example 8-7 Using Parameterized Modules Example 8-8 Parameter Passing by Order Example 8-9 Parameter Passing by Named List Example 9-1 Style 1 Moore State Machine Example 9-2 Style 1 Mealy State Machine Example 9-3 Style 2 Moore Machine Example 9-4 Style 2 Mealy Machine Example 9-5 Style 3 Mealy Machine Example 9-6 Style 4 Moore Machine Example 9-7 Style 5 Moore Machine Example 9-8 Implicit State Machine Style Example 9-9 Combinatorial Outputs Example 9-10 Registered Outputs Example 10-1 A 2-to-1 Mux Using Continuous Assignment Example 10-2 A 4-to-1 Mux Using Continuous Assignment Example 10-3 Alternate 4-to-1 Mux Using Continuous Assignment Example 10-4 An 8-Bit Adder Using Continuous Assignment Example 10-5 Latch Using Continuous Assignment Example 10-6 The 2-to-1 Mux Using always Example 10-7 The 4-to-1 Mux Using always Example 10-8 The 8-Bit Adder Using always Example 10-9 Simplified 8-Bit Adder Using always Example Mux with Continuous Assignment and Function Example Simple Counter Example A Counter without always Example Sequential Stimulus Block Example Clock Source Example Memory Exerciser Example Tasks for Sequential Code Example Basic One-Shot Example Retriggerable One-Shot Example Behavioral Description of the Alarm

17 xviii Verilog Quickstart Example Alarm Test Bench Example Partial Implementation of Alarm Example Two-Dimensional Array Example Behavioral Z-detector Example Structural Z-Detector Example An 8-by-8 Booth Multiplier Example Wallace 8-by-8 Multiplier Example A 16-by-16 Multiplier Example A 16-by-16 Wallace Multiplier for Signed Numbers Example 11-1 Normal D Flip-Flop Example 11-2 Modified D-Hip-Flop Example 11-3 Bad Register Example 11-4 Improved Register Example 11-5 Tweaked Register Example 11-6 Bad Adder Example 11-7 Improved Adder Example 11-8 Adder Reduced to a Continuous Assignment Example 11-9 Bad Mux Example Improved Mux Example Bad Barrel Shifter Example Improved Barrel Shifter Example Blocking vs. Non Blocking Assignments Example 12-1 Adder Test Module Repeated Example 12-2 Using Verilog To Calculate Responses Example 12-3 Simplifying the Test Bench with a task Example 12-4 Using a Second Module To Check the Results Example 12-5 Generating x's for Miscompare Example 12-6 Printer Abstraction Example 12-7 Printer Test Bench with Guessed Timing Example 12-8 Response-Driven Printer Test Bench Example 12-9 Test Bench for a RAM Example Memory Declaration Example Reversed Memory Declaration Example Memory File adder8. vec Example Adder Test Bench Reading from a File Example PROM Data File prom.dat Example Simple PROM Example Test Bench with No Vectors Example LFSR Example Testing the ALU with a LFSR and MISR Example ALU Modified Capture of Inputs and Outputs Example ALU Test Bench Repeated Example 13-1 Missing Initialization Example 13-2 Negative Setup Time Example 13-3 Corrected Register

18 xix Example 14-1 Initial Block To Create VCD Wave File Example 14-2 Initial Block To Create SHM Wave File Example 14-3 Interactive Verilog Module Example 14-4 Single-Stepping Example 14-5 always Loop Module Example 14-6 my.key Command File Example 14-7 Hierarchical 8-Bit Adder Example A-1 Delays in Primitive Instances Example A-2 Time Scales Example A-3 Strength Declarations

19 xx Verilog Quickstart LIST OF TABLES Table 2-1 Radix Specifiers Table 2-2 Numbers and Their Values Table 3-1 Verilog Primitives Table 4-1 Format Specifiers Table 4-2 Screen and File Output Commands Table 4-3 Enumeration of All Output Commands Table 4-4 Format Specifiers Table 4-5 Net Types Table 5-1 Arithmetic Operators Table 5-2 Bit-wise Operators Table 5-3 Logical Operators Table 5-4 Negation Operators Table 5-5 Reduction Operators Table 5-6 Truth Table for Ternary Operator Table 5-7 Equality Operators Table 5-8 Truth Table for a == b Table 5-9 Truth Table for a === b Table 5-10 Truth Table for a!= b Table 5-11 Truth Table for a!== b Table 5-12 Truth Table for a < b Table 5-13 Truth Table for a <= b Table 5-14 Truth Table for a > b Table 5-15 Truth Table for a >= b Table 5-16 Operator Order of Precedence Table 5-17 Operators Not Legal on Reals Table 5-18 Radix Specifiers Table 6-1 Comparison of Procedural and Continuous Assignments Table 6-2 Summary of Case Values and Match per Case Type Table 6-3 ALU Exercise: Explanation of Opcodes Table 6-4 Summary of Assignment Types Table 7-1 Basic UDP Table Symbols Table 7-2 Symbols for Sequential UDP Tables Table 7-3 Summary of Instance Types Table 7-4 Complete List of UDP Table Symbols Table 9-1 State Machine Styles Table 9-2 Sequential State Encoding Table 9-3 Mapping State Code To Simplify Outputs Table 9-4 Gray State Encoding Table 9-5 States Compared with Outputs Table 9-6 Outputs as State Code Table 9-7 One-Hot State Encoding Table 14-1 Log File Options

20 xxi Table 14-2 Special Keys for Interactive Simulation Table 14-3 Keystroke-Related Commands Table 14-4 Commands for Traversing and Observing Table 14-5 The trace, save, and restart Commands Table 14-6 Debugging Commands, Keystrokes, and Command-Line Options Table A-1 Logic Table for and Primitive Table A-2 Logic Table for nand Primitive Table A-3 Logic Table for or Primitive Table A-4 Logic Table for nor Primitive Table A-5 Logic Table for xor Primitive Table A-6 Logic Table for xnor Primitive Table A-7 Logic Table for buf Primitive Table A-8 Logic Table for not Primitive Table A-9 Logic Table for bufif0 Primitive Table A-10 Logic Table for bufif1 Primitive Table A-11 Logic Table for notif0 Primitive Table A-12 Logic Table for notif1 Primitive Table A-13 Logic Table for nmos Primitive Table A-14 Logic Table for rnmos Primitive Table A-15 Logic Table for pmos Primitive Table A-16 Logic Table for rpmos Primitive Table A-17 Logic Table for cmos Primitive Table A-18 Logic Table for rcmos Primitive Table A-19 Delay and Precision Units Table A-20 Strengths Table A-21 Switch Strength Reduction