ENGIN 241 Digital Systems with Lab

Size: px
Start display at page:

Download "ENGIN 241 Digital Systems with Lab"

Transcription

1 ENGIN 241 Digital Systems with Lab (4) Dr. Honggang Zhang Engineering Department University of Massachusetts Boston 1

2 Introduction Hardware description language (HDL): Specifies logic function only Computer-aided design (CAD) tool produces or synthesizes optimized gates Most commercial designs built using HDLs, and two leading HDLs: VHDL 2008 Very High Speed Integrated circuit Hardware Description Language. Widely used to translate designs into bit patterns that program actual devices. Developed in 1981 by the Department of Defense IEEE standard (1076) in 1987 Updated in 2008 (IEEE STD ) SystemVerilog Developed in 1984 by Gateway Design Automation IEEE standard (1364) in 1995 Extended in 2005 (IEEE STD ) 2

3 HDL to Gates Simulation Inputs applied to circuit Outputs checked for correctness Millions of dollars saved by debugging in simulation instead of hardware Synthesis Transforms HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them) IMPORTANT: When using an HDL, think of the hardware that the HDL should produce 3

4 Example: timing simulation of a circuit described in HDL. 4

5 VHDL Modules Two types of Modules: Behavioral: describe what a module does. Structural: describe how it is built from simpler modules. 5

6 It is important to distinguish between hardware description languages & programming languages With both, a language is used to program a device. Computers operate by following a list of tasks, each of which must be done in sequential order. Speed of operation is determined by how fast the computer can execute each instruction. A digital logic circuit is limited in speed only by how quickly the circuitry can change its outputs in response to changes in the inputs. It is monitoring all inputs concurrently & responding to any changes. 6

7 Comparing operation of a computer and a logic circuit in performing the logical operation of y = AB. A y B The logic circuit is an AND gate. The output y will be HIGH within about 10 nanoseconds of the point when A and B are HIGH simultaneously. Within approximately 10 nanoseconds after either input goes LOW, the output y will be LOW. 7

8 Comparing operation of a computer and a logic circuit in performing the logical operation of y = AB. The computer must run a program of instructions that makes decisions. Each shape in the flowchart represents one instruction. If each takes 20 ns, it will take a minimum of two or three instructions (40 60 ns) to respond to changes in the inputs. 8

9 Implementing Logic Circuits With PLDs Programmable Logic Devices (PLDs) are devices that can be configured in many ways to perform logic functions. Internal connections are made electronically to program devices. 9

10 Implementing Logic Circuits With PLDs PLDs are configured electronically & their internal circuits are wired together electronically to form a logic circuit. This programmable wiring can be thought of as thousands of connections, either connected (1), or not connected (0). Each intersection of a row (horizontal wire) & column (vertical wire) is a programmable connection. 10

11 PLDs use a switch matrix that is often referred to as a programmable array. By deciding which intersections are connected & which are not, we can program the way the inputs are connected to the outputs of the array. 11

12 A program written in a hardware description language (e.g., VHDL) defines the connections to be made. The program is loaded into the device after translation by a compiler. 12

13 Programmable Logic Devices The reason for using programmable logic devices Lots of logic gates in a single IC. Control of the interconnection of these gates electronically. PLDs allow the design process to be automated. Designers identify inputs, outputs, and logical relationships. PLDs are electronically configured to form the defined logic circuits. 13

14 For out-of-system programming the PLD is placed in a programmer, connected to a PC. PC software translates and loads the information. In-system programming is done by connecting directly to portal pins while the IC remains in the system. An interface cable connects the PLD to a PC running the software that loads the device. 14

15 Logic circuits can be described using schematic diagrams, logic equations, truth tables, and HDL. PLD development software can convert any of these descriptions into 1s and 0s and loaded into the PLD. We will use Active-HDL software 15

16 A system is built from logic blocks. Each block is described by a design file. After testing it is compiled using development software. The compiled block is tested using a simulator for verify correct operation. A PLD is programmed to verify correct operation. 16

17 VHDL Format and Syntax 17

18 Format refers to a definition of inputs, outputs & how the output responds to the input (operation). Languages that are interpreted by computers must follows strict rules of syntax, which refers to the order of elements. Format of HDL files. 18

19 On the left side of the diagram is the set of inputs, and on the right is the set of outputs. The symbols in the middle define its operation. 19

20 A circuit described in HDL must be given a name. Start with input/output (I/O) definition, then, the definition of an operation is contained in a set of statements. Inputs & outputs (ports) must be assigned names and defined according to the nature of the port. The mode defines whether it is input or output. The type refers to the number of bits and how those bits are grouped and interpreted. A single bit input, can have only two values: 0 and 1. A four-bit binary number can have any one of 16 different values ( ). 20

21 The keyword ENTITY gives a name to the circuit block, which in this case is and_gate. The keyword PORT tells the compiler that we are defining inputs and outputs to this circuit block. The BIT description tells the compiler that each variable in the list is a single bit. The ARCHITECTURE declaration is used to describe the operation of everything inside the block, which is between BEGIN and VHDL is not case-sensitive. Here we use lowercase for variable names. END. 21

22 In many designs, there is a need to define signal points inside the circuit block called buried nodes or local signals. Points in the circuit that may be useful as a reference point, that are not inputs or outputs. 22

23 VHDL local signals: Keyword SIGNAL defines intermediate signal. Keyword BIT designates the type of signal 23

24 24

25 Representing Data in VHDL 25

26 Representing Data in HDL Every programming language & HDL has its own unique way of identifying number systems. Generally done with a prefix to indicate the system. When we read one of these number designations, we must think of it as a symbol that represents a binary bit pattern. These numeric values are referred to as scalars or literals. Binary Hexadecimal Decimal 26

27 In order to describe a port with more than one data bit we assign a name and the number of bits. This is called a bit array or bit vector. Each element (bit) has a unique index number (0 7) to describe position in the overall structure. HDLs & computer programming languages use this notation. 27

28 VHDL syntax a name for the bit vector is followed by the mode, the type, and the range. Enclosed in parenthesis, in the ENTITY section. To declare an eight-bit input port called p1 PORT (p1 :IN BIT_VECTOR (7 DOWNTO 0); 28

29 Intermediate variables can be declared as an array of bits in the ARCHITECTURE section Eight-bit temperature port p1 assigned to a signal named temp SIGNAL temp :BIT_VECTOR {7 DOWNTO 0}; BEGIN temp <= p1; END; 29

30 Representing numbers Numbers can be specified in binary, octal, decimal, or hexadecimal. The size, i.e., the number of bits, may optionally be given. Underscores in a number are ignored and can be helpful in breaking long numbers into more readable chunks. 30

31 STD_LOGIC numbers are written in binary and enclosed in single quotes: '0' and '1' indicate logic 0 and 1. The format for STD_LOGIC_VECTOR constants is NB"value", where N is the size in bits, B is a letter indicating the base. B for binary, O for octal, D for decimal, and X for hexadecimal. For example, 9X"25" indicates a 9-bit number with a value of =37 10 = If the base is omitted, it defaults to binary. If the size is not given, the number is assumed to have a size matching the number of bits specified in the value. 31

32 Examples Underscores in a number are ignored and can be helpful in breaking long numbers into more readable chunks. 32

33 Bit swizzling Operate on a subset of a bus or to concatenate (join together) signals to form a bus. () aggregate operator Example, y is given the 9-bit value c(2)c(1)d(0)d(0)d(0)c(0)101 using bit swizzling operations. y <=(c(2 downto 1), d(0), d(0), d(0), c(0), 3B"101"); z= , assuming z is a 8-bit STD_LOGIC_VECTOR. z <= ("10", 4 => '1', 2 downto 1 =>'1', others =>'0'); others => '0' and others => '1' fill all of the rest of the bits with 0 and 1, respectively. 33

34 z indicates a floating value, e.g., z is particularly useful for describing a tristate buffer, whose output floats when the enable is 0. e.g. all the tristate buffers driving a bus are OFF, the bus will float, indicated by z. VHDLs use x to indicate an invalid logic level. If a bus is simultaneously driven to 0 and 1 by two enabled tristate buffers (or other gates), the result is x, indicating contention. u indicates an unknown state e.g., a flip-flop s output initialized to u 34

35 In VHDL, STD_LOGIC signals are '0', '1', 'z', 'x', and 'u'. If a gate receives a floating input, it may produce an x output when it can t determine the correct output value. If a gate receives an illegal or uninitialized input, it may produce an x output. 35

36 If we see x or u values in simulation, this is almost always an indication of a bug or bad coding practice. In the synthesized circuit, this corresponds to a floating gate input, uninitialized state, or contention. The x or u may be interpreted randomly by the circuit as 0 or 1, leading to unpredictable behavior. 36

37 AND truth table More information: 37

38 Learn idioms, specific ways to describe various classes of logic. Combinational Logic 38

39 library IEEE; use IEEE.STD_LOGIC_1164.all; entity gates is port(a, b: in STD_LOGIC_VECTOR(3 downto 0); y1, y2, y3, y4, y5: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture synth of gates is begin -- five different two-input logic gates -- acting on 4-bit busses y1 <= a and b; y2 <= a or b; y3 <= a xor b; y4 <= a nand b; y5 <= a nor b; end; Bitwise operators not, xor, and, or are VHDL operators. a, b, and y1 are operands. An expression is a combination of operators and operands. A complete command such as y4 <= a nand b; is called a statement, ended with a semicolon. This is called concurrent signal assignment. Anytime the inputs change, the output recomputed, thus, combinational logic. 39

40 synthesized circuit library IEEE; use IEEE.STD_LOGIC_1164.all; entity gates is port(a, b: in STD_LOGIC_VECTOR(3 downto 0); y1, y2, y3, y4, y5: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture synth of gates is begin -- five different two-input logic gates -- acting on 4-bit busses y1 <= a and b; y2 <= a or b; y3 <= a xor b; y4 <= a nand b; y5 <= a nor b; end; 40

41 entity and8 is port(a: in STD_LOGIC_VECTOR(7 downto 0); y: out STD_LOGIC); end; architecture synth of and8 is begin y <= and a; -- and a is much easier to write than -- y <= a(7) and a(6) and a(5) and a(4) and -- a(3) and a(2) and a(1) and a(0); end; and in this code is a reduction operator which imply a multiple-input gate acting on a single bus. 41

42 library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux2 is port(d0, d1: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture synth of mux2 is begin y <= d1 when s else d0; end; Conditional signal assignments perform different operations depending on some condition. They are especially useful for describing a multiplexer. The conditional signal assignment sets y to d1 if s is 1. Otherwise it sets y to d0. Prior to the 2008 revision of VHDL, one had to write when s= '1' rather than when s. 42

43 A 4:1 multiplexer can select one of four inputs using multiple else clauses in the conditional signal assignment. library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux4 is port(d0, d1, d2, d3: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC_VECTOR(1 downto 0); y: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture synth1 of mux4 is begin y <= d0 when s = "00" else d1 when s = "01" else d2 when s = "10" else d3; end; 43

44 Selected signal assignment statements to provide a shorthand when selecting from one of several possibilities. This is analogous to using a switch/case statement in place of multiple if/else statements in some programming languages. The 4:1 multiplexer can be rewritten with selected signal assignment as follows: architecture synth2 of mux4 is begin with s select y <= d0 when "00", d1 when "01", d2 when "10", d3 when others; end; 44

45 VHDL operator precedence Unlike Boolean algebra, logical operations have equal precedence, thus parentheses are often necessary. 45

46 Truth Tables Using HDL - VHDL Circuits can be designed directly from truth tables, using VHDL. library IEEE; use IEEE.STD_LOGIC_1164.all; entity ex3 is port(a, b, c: in bit; y: out bit); end; architecture truth of ex3 is signal in_bits: bit_vector (2 downto 0); begin in_bits <= a & b & c; -- concatenate input bits into bit_vector with in_bits select y<= '0' when "000", '0' when "001", '0' when "010", '1' when "011", '0' when "100", '1' when "101", '1' when "110", '1' when "111"; end; 46

47 47

48 48

49 More examples on internal variables library IEEE; use IEEE.STD_LOGIC_1164.all; entity fulladder is port(a, b, cin: in STD_LOGIC; s, cout: out STD_LOGIC); end; architecture synth of fulladder is signal p, g: STD_LOGIC; begin p <= a xor b; g <= a and b; s <= p xor cin; cout <= g or (p and cin); end; Define intermediate signals, P and G Then we get, 49

50 A tristate buffer example library IEEE; use IEEE.STD_LOGIC_1164.all; entity tristate is port(a: in STD_LOGIC_VECTOR(3 downto 0); en: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture synth of tristate is begin y <= a when en else "ZZZZ"; end; 50

51 Delays HDL statements may be associated with delays specified in arbitrary units. helps a simulation to predict how fast a circuit will work for debugging to understand cause and effect These delays are ignored during synthesis the delay of a gate produced by the synthesizer depends on its t pd and t cd specifications, not on numbers in HDL code. 51

52 Structural modeling Describe a module in terms of how it is composed of simpler modules. Example: Assemble a 4:1 multiplexer from three 2:1 multiplexers. Each copy of the 2:1 multiplexer is an instance. Multiple instances of the same module are distinguished by distinct names, lowmux, highmux, and finalmux. 52

53 Assemble a 4:1 multiplexer from three 2:1 multiplexers. 53

54 library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux4 is port(d0, d1, d2, d3: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC_VECTOR(1 downto 0); y: out STD_LOGIC_VECTOR(3 downto 0) ); end; architecture struct of mux4 is component mux2 port(d0,d1: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end component; signal low, high: STD_LOGIC_VECTOR(3 downto 0); begin lowmux: mux2 port map(d0, d1, s(0), low); highmux: mux2 port map(d2, d3, s(0), high); finalmux: mux2 port map(low, high, s(1), y); end; 54

55 Construct a 2:1 multiplexer from a pair tristate buffers 55

56 library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux2 is port(d0, d1: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end; architecture struct of mux2 is component tristate port(a: in STD_LOGIC_VECTOR(3 downto 0); en: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end component; signal sbar: STD_LOGIC; begin sbar <= not s; t0: tristate port map(d0, sbar, y); t1: tristate port map(d1, s, y); end; Construct a 2:1 multiplexer from a pair tristate buffers. 56

57 An 8-bit wide 2:1 multiplexer is built using two of the 4-bit 2:1 multiplexers already defined, operating on the low and high nibbles of the byte. 57

58 library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux2_8 is port(d0, d1: in STD_LOGIC_VECTOR(7 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR(7 downto 0)); end; architecture struct of mux2_8 is component mux2 port(d0, d1: in STD_LOGIC_VECTOR(3 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR(3 downto 0)); end component; begin lsbmux: mux2 port map(d0(3 downto 0), d1(3 downto 0), s, y(3 downto 0)); msbmux: mux2 port map(d0(7 downto 4), d1(7 downto 4), s, y(7 downto 4)); end; An 8-bit wide 2:1 multiplexer is built using two of the 4-bit 2:1 multiplexers already defined, operating on the low and high nibbles of the byte. 58

59 Active-HDL We will use Active-HDL software to demonstrate the example programs listed here. set VHDL as the default specification for the VHDL compiler. 59

60 Demo burning GAL 22v10 isplever Universal programmer 60

Hardware Description Language VHDL (1) Introduction

Hardware Description Language VHDL (1) Introduction Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for

More information

Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University

Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.

More information

Digital Systems Design

Digital Systems Design Digital Systems Design Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits Dr. D. J. Jackson Lecture 2-1 Introduction to VHDL Designer writes a logic circuit description in

More information

Lecture 32: SystemVerilog

Lecture 32: SystemVerilog Lecture 32: SystemVerilog Outline SystemVerilog module adder(input logic [31:0] a, input logic [31:0] b, output logic [31:0] y); assign y = a + b; Note that the inputs and outputs are 32-bit busses. 17:

More information

HDLs and SystemVerilog. Digital Computer Design

HDLs and SystemVerilog. Digital Computer Design HDLs and SystemVerilog Digital Computer Design Logic Arrays Gates can be organized into regular arrays. If the connections are made programmable, these logic arrays can be configured to perform any function

More information

CSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\

CSCI Lab 3. VHDL Syntax. Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\ CSCI 250 - Lab 3 VHDL Syntax Due: Tuesday, week6 Submit to: \\fs2\csci250\lab-3\ Objectives 1. Learn VHDL Valid Names 2. Learn the presentation of Assignment and Comments 3. Learn Modes, Types, Array,

More information

Introduction to VHDL #1

Introduction to VHDL #1 ECE 3220 Digital Design with VHDL Introduction to VHDL #1 Lecture 3 Introduction to VHDL The two Hardware Description Languages that are most often used in industry are: n VHDL n Verilog you will learn

More information

Chapter 4 :: Topics. Introduction. SystemVerilog. Hardware description language (HDL): allows designer to specify logic function only.

Chapter 4 :: Topics. Introduction. SystemVerilog. Hardware description language (HDL): allows designer to specify logic function only. Chapter 4 :: Hardware Description Languages Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Chapter 4 :: Topics Introduction Combinational Logic Structural Modeling Sequential

More information

Chapter 4. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 4 <1>

Chapter 4. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 4 <1> Chapter 4 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 4 Chapter 4 :: Topics Introduction Combinational Logic Structural Modeling Sequential

More information

Chapter 4. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 4 <1>

Chapter 4. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 4 <1> Chapter 4 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 4 Chapter 4 :: Topics Introduction Combinational Logic Structural Modeling Sequential

More information

C-Based Hardware Design

C-Based Hardware Design LECTURE 6 In this lecture we will introduce: The VHDL Language and its benefits. The VHDL entity Concurrent and Sequential constructs Structural design. Hierarchy Packages Various architectures Examples

More information

Lecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1

Lecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1 Lecture 1: VHDL Quick Start Digital Systems Design Fall 10, Dec 17 Lecture 1 1 Objective Quick introduction to VHDL basic language concepts basic design methodology Use The Student s Guide to VHDL or The

More information

14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages

14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages 14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #22: Introduction to Verilog Hardware Description Languages Basic idea: Language constructs

More information

Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)

Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language) Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable

More information

Verilog Design Principles

Verilog Design Principles 16 h7fex // 16-bit value, low order 4 bits unknown 8 bxx001100 // 8-bit value, most significant 2 bits unknown. 8 hzz // 8-bit value, all bits high impedance. Verilog Design Principles ECGR2181 Extra Notes

More information

Lecture 3 Introduction to VHDL

Lecture 3 Introduction to VHDL CPE 487: Digital System Design Spring 2018 Lecture 3 Introduction to VHDL Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 Managing Design

More information

Contents. Appendix D Verilog Summary Page 1 of 16

Contents. Appendix D Verilog Summary Page 1 of 16 Appix D Verilog Summary Page 1 of 16 Contents Appix D Verilog Summary... 2 D.1 Basic Language Elements... 2 D.1.1 Keywords... 2 D.1.2 Comments... 2 D.1.3 Identifiers... 2 D.1.4 Numbers and Strings... 3

More information

Lecture 3: Modeling in VHDL. EE 3610 Digital Systems

Lecture 3: Modeling in VHDL. EE 3610 Digital Systems EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware

More information

VHDL 2 Combinational Logic Circuits. Reference: Roth/John Text: Chapter 2

VHDL 2 Combinational Logic Circuits. Reference: Roth/John Text: Chapter 2 VHDL 2 Combinational Logic Circuits Reference: Roth/John Text: Chapter 2 Combinational logic -- Behavior can be specified as concurrent signal assignments -- These model concurrent operation of hardware

More information

Combinational Logic COMB. LOGIC BLOCK. A Combinational Logic Block is one where the outputs depend only on the current inputs

Combinational Logic COMB. LOGIC BLOCK. A Combinational Logic Block is one where the outputs depend only on the current inputs Combinational Logic A Combinational Logic Block is one where the outputs depend only on the current inputs COMB. LOGIC BLOCK A combinational logic block can be implemented using simple gates or lookup

More information

ECE 545 Lecture 5. Data Flow Modeling in VHDL. George Mason University

ECE 545 Lecture 5. Data Flow Modeling in VHDL. George Mason University ECE 545 Lecture 5 Data Flow Modeling in VHDL George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 4, Concurrent Signal Assignment Statements of VHDL 2 Types of VHDL Description

More information

Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Part II

Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Part II Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Part II Ahmed Abu-Hajar, Ph.D. abuhajar@digitavid.net Digitavid, Inc San Jose, CA VHDL Lexical Description Code

More information

Concurrent Signal Assignment Statements (CSAs)

Concurrent Signal Assignment Statements (CSAs) Concurrent Signal Assignment Statements (CSAs) Digital systems operate with concurrent signals Signals are assigned values at a specific point in time. VHDL uses signal assignment statements Specify value

More information

ELCT 501: Digital System Design

ELCT 501: Digital System Design ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)

More information

VHDL Structural Modeling II

VHDL Structural Modeling II VHDL Structural Modeling II ECE-331, Digital Design Prof. Hintz Electrical and Computer Engineering 5/7/2001 331_13 1 Ports and Their Usage Port Modes in reads a signal out writes a signal inout reads

More information

Introduction to VHDL. Main language concepts

Introduction to VHDL. Main language concepts Introduction to VHDL VHSIC (Very High Speed Integrated Circuit) Hardware Description Language Current standard is IEEE 1076-1993 (VHDL-93). Some tools still only support VHDL-87. Tools used in the lab

More information

Chapter 6 Combinational-Circuit Building Blocks

Chapter 6 Combinational-Circuit Building Blocks Chapter 6 Combinational-Circuit Building Blocks Commonly used combinational building blocks in design of large circuits: Multiplexers Decoders Encoders Comparators Arithmetic circuits Multiplexers A multiplexer

More information

Review of Digital Design with VHDL

Review of Digital Design with VHDL Review of Digital Design with VHDL Digital World Digital world is a world of 0 and 1 Each binary digit is called a bit Eight consecutive bits are called a byte Hexadecimal (base 16) representation for

More information

ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic

ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level

More information

UNIT I Introduction to VHDL VHDL: - V -VHSIC, H - Hardware, D - Description, L Language Fundamental section of a basic VHDL code Library :

UNIT I Introduction to VHDL VHDL: - V -VHSIC, H - Hardware, D - Description, L Language Fundamental section of a basic VHDL code Library : UNIT I Introduction to VHDL VHDL stands for very high-speed integrated circuit hardware description language. Which is one of the programming languages used to model a digital system by dataflow, behavioral

More information

Lecture 4. VHDL Fundamentals. George Mason University

Lecture 4. VHDL Fundamentals. George Mason University Lecture 4 VHDL Fundamentals George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 3, Basic Language Constructs of VHDL 2 Design Entity ECE 448 FPGA and ASIC Design with

More information

Verilog Design Principles

Verilog Design Principles 16 h7fex // 16-bit value, low order 4 bits unknown 8 bxx001100 // 8-bit value, most significant 2 bits unknown. 8 hzz // 8-bit value, all bits high impedance. Verilog Design Principles ECGR2181 Extra Notes

More information

VHDL for FPGA Design. by : Mohamed Samy

VHDL for FPGA Design. by : Mohamed Samy VHDL for FPGA Design by : Mohamed Samy VHDL Vhdl is Case insensitive myvar = myvar = MYVAR IF = if = if Comments start with -- Comments can exist anywhere in the line Semi colon indicates the end of statements

More information

Menu. Introduction to VHDL EEL3701 EEL3701. Intro to VHDL

Menu. Introduction to VHDL EEL3701 EEL3701. Intro to VHDL 3-Jul-1 4:34 PM VHDL VHDL: The Entity VHL: IEEE 1076 TYPE VHDL: IEEE 1164 TYPE VHDL: The Architecture Mixed-Logic in VHDL VHDL MUX examples See also example file on web: Creating graphical components (Component_Creation.pdf)

More information

Logic and Computer Design Fundamentals VHDL. Part 1 Chapter 4 Basics and Constructs

Logic and Computer Design Fundamentals VHDL. Part 1 Chapter 4 Basics and Constructs Logic and Computer Design Fundamentals VHDL Part Chapter 4 Basics and Constructs Charles Kime & Thomas Kaminski 24 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Overview

More information

ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic

ECE 448 Lecture 3. Combinational-Circuit Building Blocks. Data Flow Modeling of Combinational Logic ECE 448 Lecture 3 Combinational-Circuit Building Blocks Data Flow Modeling of Combinational Logic George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 3, RT-level

More information

Introduction. Why Use HDL? Simulation output. Explanation

Introduction. Why Use HDL? Simulation output. Explanation Introduction Verilog HDL is a Hardware Description Language (HDL) HDL is a language used to describe a digital system, for example, a computer or a component of a computer. Most popular HDLs are VHDL and

More information

VHDL. Chapter 1 Introduction to VHDL. Course Objectives Affected. Outline

VHDL. Chapter 1 Introduction to VHDL. Course Objectives Affected. Outline Chapter 1 Introduction to VHDL VHDL VHDL - Flaxer Eli Ch 1-1 Course Objectives Affected Write functionally correct and well-documented VHDL code, intended for either simulation or synthesis, of any combinational

More information

Digital Systems Design

Digital Systems Design IAY 0600 Example: HalfAdder Behavior Structure Digital Systems Design a b Sum Carry 0 0 0 0 0 1 1 0 a b HalfAdder Sum Carry 1 0 1 0 VHDL discussion Dataflow Style Combinational Design 1 1 0 1 a Sum Sum

More information

EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 4 Introduction to VHDL

EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 4 Introduction to VHDL EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 4 Introduction to VHDL Read before class: Chapter 2 from textbook (first part) Outline VHDL Overview VHDL Characteristics and Concepts

More information

Chapter 2 Basic Logic Circuits and VHDL Description

Chapter 2 Basic Logic Circuits and VHDL Description Chapter 2 Basic Logic Circuits and VHDL Description We cannot solve our problems with the same thinking we used when we created them. ----- Albert Einstein Like a C or C++ programmer don t apply the logic.

More information

What Is VHDL? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE 1076 standard (1987, 1993)

What Is VHDL? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE 1076 standard (1987, 1993) What Is VHDL? VHSIC (Very High Speed Integrated Circuit) Hardware Description Language IEEE 1076 standard (1987, 1993) Only possible to synthesize logic from a subset of VHDL Subset varies according to

More information

Introduction to VHDL

Introduction to VHDL Introduction to VHDL Agenda Introduce VHDL Basic VHDL constructs Implementing circuit functions Logic, Muxes Clocked Circuits Counters, Shifters State Machines FPGA design and implementation issues FPGA

More information

CCE 3202 Advanced Digital System Design

CCE 3202 Advanced Digital System Design CCE 3202 Advanced Digital System Design Lab Exercise #2 Introduction You will use Xilinx Webpack v9.1 to allow the synthesis and creation of VHDLbased designs. This lab will outline the steps necessary

More information

Two HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design

Two HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design Two HDLs used today Introduction to Structured VLSI Design VHDL I VHDL and Verilog Syntax and ``appearance'' of the two languages are very different Capabilities and scopes are quite similar Both are industrial

More information

COE 405 Design Methodology Based on VHDL

COE 405 Design Methodology Based on VHDL COE 405 Design Methodology Based on VHDL Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Elements of VHDL Top-Down Design Top-Down Design with

More information

Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design

Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two major languages Verilog (IEEE 1364), latest version is

More information

Lecture 4. VHDL Fundamentals. Required reading. Example: NAND Gate. Design Entity. Example VHDL Code. Design Entity

Lecture 4. VHDL Fundamentals. Required reading. Example: NAND Gate. Design Entity. Example VHDL Code. Design Entity Required reading Lecture 4 VHDL Fundamentals P. Chu, RTL Hardware Design using VHDL Chapter 3, Basic Language Constructs of VHDL George Mason University 2 Example: NAND Gate Design Entity a b z a b z 0

More information

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital

More information

Contents. Appendix D VHDL Summary Page 1 of 23

Contents. Appendix D VHDL Summary Page 1 of 23 Appendix D VHDL Summary Page 1 of 23 Contents Appendix D VHDL Summary...2 D.1 Basic Language Elements...2 D.1.1 Comments...2 D.1.2 Identifiers...2 D.1.3 Data Objects...2 D.1.4 Data Types...2 D.1.5 Data

More information

structure syntax different levels of abstraction

structure syntax different levels of abstraction This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital

More information

Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this

Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital

More information

CDA 4253 FPGA System Design Introduction to VHDL. Hao Zheng Dept of Comp Sci & Eng USF

CDA 4253 FPGA System Design Introduction to VHDL. Hao Zheng Dept of Comp Sci & Eng USF CDA 4253 FPGA System Design Introduction to VHDL Hao Zheng Dept of Comp Sci & Eng USF Reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 1, Gate-level combinational circuits Two purposes of using

More information

Embedded Systems CS - ES

Embedded Systems CS - ES Embedded Systems - 1 - REVIEW Hardware/System description languages VDHL VHDL-AMS SystemC TLM - 2 - VHDL REVIEW Main goal was modeling of digital circuits Modelling at various levels of abstraction Technology-independent

More information

VHDL. Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit

VHDL. Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit VHDL VHDL Official Definition: VHSIC Hardware Description Language VHISC Very High Speed Integrated Circuit VHDL Alternative (Student Generated) Definition Very Hard Digital Logic language VHDL Design

More information

Computer-Aided Digital System Design VHDL

Computer-Aided Digital System Design VHDL بس م اهلل الر حم ن الر حی م Iran University of Science and Technology Department of Computer Engineering Computer-Aided Digital System Design VHDL Ramin Rajaei ramin_rajaei@ee.sharif.edu Modeling Styles

More information

CMPT 250: Computer Architecture. Using LogicWorks 5. Tutorial Part 1. Somsubhra Sharangi

CMPT 250: Computer Architecture. Using LogicWorks 5. Tutorial Part 1. Somsubhra Sharangi CMPT 250: Computer Architecture Using LogicWorks 5 Tutorial Part 1 Somsubhra Sharangi What is VHDL? A high level language to describe digital circuit Different that a programming language ( such as Java)

More information

EECE-4740/5740 Advanced VHDL and FPGA Design. Lecture 3 Concurrent and sequential statements

EECE-4740/5740 Advanced VHDL and FPGA Design. Lecture 3 Concurrent and sequential statements EECE-4740/5740 Advanced VHDL and FPGA Design Lecture 3 Concurrent and sequential statements Cristinel Ababei Marquette University Department of Electrical and Computer Engineering Overview Components hierarchy

More information

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation A Verilog Primer An Overview of Verilog for Digital Design and Simulation John Wright Vighnesh Iyer Department of Electrical Engineering and Computer Sciences College of Engineering, University of California,

More information

Multi-valued Logic. Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized

Multi-valued Logic. Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized Multi-valued Logic Standard Logic IEEE 1164 Type std_ulogic is ( U, uninitialized X, unknown 0, logic 0 1, logic 1 Z, high impedance W, unknown L, logic 0 weak H, logic 1 weak - ); don t care Standard

More information

Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification

Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Digital Design Using VHDL Using Xilinx s Tool for Synthesis and ModelSim for Verification Ahmed Abu-Hajar, Ph.D. abuhajar@digitavid.net Digitavid, Inc San Jose, CA Session One Outline Introducing VHDL

More information

!"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"

!#$%&&'(')*+%,%-.#'/'.001$$ !"#$%&&"'(')"*+"%,%-".#"'/"'.001$$"!!"#$%&'#()#*+"+#,-."/0110#230#4."50",+"+#)6# 6+-+#(.6+-0#)4475.8)60#0/#.65-0#230#9+**+"+# 2.48).-0#(.6+-0#! 2+"*5."5*:#,."/0110#;)**0! *),".6*:#-.99-0*0"5."+#2+660,.40"5)#;)*)2)#

More information

6.111 Lecture # 5. Entity section describes input and output. VHDL: Very High speed integrated circuit Description Language:

6.111 Lecture # 5. Entity section describes input and output. VHDL: Very High speed integrated circuit Description Language: 6.111 Lecture # 5 VHDL: Very High speed integrated circuit Description Language: All VHDL files have two sections: architecture and entity -- Massachusetts (Obsolete) Stoplight Example library ieee; use

More information

Introduction to VHDL #3

Introduction to VHDL #3 ECE 322 Digital Design with VHDL Introduction to VHDL #3 Lecture 7 & 8 VHDL Modeling Styles VHDL Modeling Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral (sequential)

More information

CS232 VHDL Lecture. Types

CS232 VHDL Lecture. Types CS232 VHDL Lecture VHSIC Hardware Description Language [VHDL] is a language used to define and describe the behavior of digital circuits. Unlike most other programming languages, VHDL is explicitly parallel.

More information

1. Defining and capturing the design of a system. 2. Cost Limitations (low profit margin must sell millions)

1. Defining and capturing the design of a system. 2. Cost Limitations (low profit margin must sell millions) What is an Embedded System? A type of computer system ECEN 4856: Embedded System Design Lecture 2: Embedded System Standards Traditional Definitions Limited in hardware and software vs the PC Designed

More information

Lab 3: Standard Combinational Components

Lab 3: Standard Combinational Components Lab 3: Standard Combinational Components Purpose In this lab you will implement several combinational circuits on the DE1 development board to test and verify their operations. Introduction Using a high-level

More information

IT T35 Digital system desigm y - ii /s - iii

IT T35 Digital system desigm y - ii /s - iii UNIT - V Introduction to Verilog Hardware Description Language Introduction HDL for combinational circuits Sequential circuits Registers and counters HDL description for binary multiplier. 5.1 INTRODUCTION

More information

Basic Language Constructs of VHDL

Basic Language Constructs of VHDL Basic Language Constructs of VHDL Chapter 3 1 Outline 1. Basic VHDL program 2. Lexical elements and program format 3. Objects 4. Data type and operators Chapter 3 2 1. Basic VHDL program Chapter 3 3 Design

More information

A Brief Introduction to Verilog Hardware Definition Language (HDL)

A Brief Introduction to Verilog Hardware Definition Language (HDL) www.realdigital.org A Brief Introduction to Verilog Hardware Definition Language (HDL) Forward Verilog is a Hardware Description language (HDL) that is used to define the structure and/or behavior of digital

More information

Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog

Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog Verilog Radek Pelánek and Šimon Řeřucha Contents 1 Computer Aided Design 2 Basic Syntax 3 Gate Level Modeling 4 Behavioral Modeling Computer Aided Design Hardware Description Languages (HDL) Verilog C

More information

Outline. CPE/EE 422/522 Advanced Logic Design L05. Review: General Model of Moore Sequential Machine. Review: Mealy Sequential Networks.

Outline. CPE/EE 422/522 Advanced Logic Design L05. Review: General Model of Moore Sequential Machine. Review: Mealy Sequential Networks. Outline CPE/EE 422/522 Advanced Logic Design L05 Electrical and Computer Engineering University of Alabama in Huntsville What we know Combinational Networks Sequential Networks: Basic Building Blocks,

More information

VHDL VS VERILOG.

VHDL VS VERILOG. 1 VHDL VS VERILOG http://www.cse.cuhk.edu.hk/~mcyang/teaching.html 2 VHDL & Verilog They are both hardware description languages for modeling hardware. They are each a notation to describe the behavioral

More information

ECE4401 / CSE3350 ECE280 / CSE280 Digital Design Laboratory

ECE4401 / CSE3350 ECE280 / CSE280 Digital Design Laboratory ECE4401 / CSE3350 ECE280 / CSE280 Digital Design Laboratory Instructor John Chandy Office: ITEB 437 Office Hours: W10-12 Tel: (860) 486-5047 Email: john.chandy@uconn chandy@uconn.edu Class home page: HuskyCT

More information

VHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language

VHDL. VHDL History. Why VHDL? Introduction to Structured VLSI Design. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language VHDL Introduction to Structured VLSI Design VHDL I Very High Speed Integrated Circuit (VHSIC) Hardware Description Language Joachim Rodrigues A Technology Independent, Standard Hardware description Language

More information

Experiment 8 Introduction to VHDL

Experiment 8 Introduction to VHDL Experiment 8 Introduction to VHDL Objectives: Upon completion of this laboratory exercise, you should be able to: Enter a simple combinational logic circuit in VHDL using the Quartus II Text Editor. Assign

More information

VHDL Sample Slides Rev Sample Slides from the 2-day and 4-day VHDL Training Courses

VHDL Sample Slides Rev Sample Slides from the 2-day and 4-day VHDL Training Courses VHDL Sample Slides from the 2-day and 4-day VHDL Training Courses Rev. 4.7 VHDL 2011 TM Associates, Inc. 1-1 These sample slides are taken from the 4-day basic VHDL training course. They are from a variety

More information

Very High Speed Integrated Circuit Har dware Description Language

Very High Speed Integrated Circuit Har dware Description Language Very High Speed Integrated Circuit Har dware Description Language Industry standard language to describe hardware Originated from work in 70 s & 80 s by the U.S. Departm ent of Defence Root : ADA Language

More information

Hardware description language (HDL)

Hardware description language (HDL) Hardware description language (HDL) A hardware description language (HDL) is a computer-based language that describes the hardware of digital systems in a textual form. It resembles an ordinary computer

More information

Digital Systems Design

Digital Systems Design IAY 0600 Digital Systems Design VHDL discussion Dataflow Style Combinational Design Tallinn University of Technology Combinational systems Combinational systems have no memory. A combinational system's

More information

CPE/EE 422/522. Chapter 8 - Additional Topics in VHDL. Dr. Rhonda Kay Gaede UAH. 8.1 Attributes - Signal Attributes that return a value

CPE/EE 422/522. Chapter 8 - Additional Topics in VHDL. Dr. Rhonda Kay Gaede UAH. 8.1 Attributes - Signal Attributes that return a value CPE/EE 422/522 Chapter 8 - Additional Topics in VHDL Dr. Rhonda Kay Gaede UAH 1 8.1 Attributes - Signal Attributes that return a value A event true if a has just occurred A active true if A has, even if

More information

Physics 364, Fall 2012, reading due your answers to before the end of Wednesday s lab.

Physics 364, Fall 2012, reading due your answers to before the end of Wednesday s lab. Physics 364, Fall 2012, reading due 2012-11-28. Email your answers to ashmansk@hep.upenn.edu before the end of Wednesday s lab. Course materials and schedule are at http://positron.hep.upenn.edu/p364 Assignment:

More information

HDL. Hardware Description Languages extensively used for:

HDL. Hardware Description Languages extensively used for: HDL Hardware Description Languages extensively used for: Describing (digital) hardware (formal documentation) Simulating it Verifying it Synthesizing it (first step of modern design flow) 2 main options:

More information

Lecture 12 VHDL Synthesis

Lecture 12 VHDL Synthesis CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?

More information

FPGA BASED SYSTEM DESIGN. Dr. Tayab Din Memon Lecture 9 & 10 : Combinational and Sequential Logic

FPGA BASED SYSTEM DESIGN. Dr. Tayab Din Memon Lecture 9 & 10 : Combinational and Sequential Logic FPGA BASED SYSTEM DESIGN Dr. Tayab Din Memon tayabuddin.memon@faculty.muet.edu.pk Lecture 9 & 10 : Combinational and Sequential Logic Combinational vs Sequential Logic Combinational logic output depends

More information

VHDL Part 2. What is on the agenda? Basic VHDL Constructs. Examples. Data types Objects Packages and libraries Attributes Predefined operators

VHDL Part 2. What is on the agenda? Basic VHDL Constructs. Examples. Data types Objects Packages and libraries Attributes Predefined operators VHDL Part 2 Some of the slides are taken from http://www.ece.uah.edu/~milenka/cpe428-02s/ What is on the agenda? Basic VHDL Constructs Data types Objects Packages and libraries Attributes Predefined operators

More information

Combinational Logic II

Combinational Logic II Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic

More information

VHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning

VHDL. ELEC 418 Advanced Digital Systems Dr. Ron Hayne. Images Courtesy of Cengage Learning VHDL ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Cengage Learning Design Flow 418_02 2 VHDL Modules 418_02 3 VHDL Libraries library IEEE; use IEEE.std_logic_1164.all; std_logic Single-bit

More information

IE1204 Digital Design L7: Combinational circuits, Introduction to VHDL

IE1204 Digital Design L7: Combinational circuits, Introduction to VHDL IE24 Digital Design L7: Combinational circuits, Introduction to VHDL Elena Dubrova KTH / ICT / ES dubrova@kth.se This lecture BV 38-339, 6-65, 28-29,34-365 IE24 Digital Design, HT 24 2 The multiplexer

More information

Basic Language Concepts

Basic Language Concepts Basic Language Concepts Sudhakar Yalamanchili, Georgia Institute of Technology ECE 4170 (1) Describing Design Entities a sum b carry Primary programming abstraction is a design entity Register, logic block,

More information

EITF35: Introduction to Structured VLSI Design

EITF35: Introduction to Structured VLSI Design EITF35: Introduction to Structured VLSI Design Part 1.2.2: VHDL-1 Liang Liu liang.liu@eit.lth.se 1 Outline VHDL Background Basic VHDL Component An example FSM Design with VHDL Simulation & TestBench 2

More information

Verilog Module 1 Introduction and Combinational Logic

Verilog Module 1 Introduction and Combinational Logic Verilog Module 1 Introduction and Combinational Logic Jim Duckworth ECE Department, WPI 1 Module 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog

More information

Introduction. Purpose. Intended Audience. Conventions. Close

Introduction. Purpose. Intended Audience. Conventions. Close Introduction Introduction Verilog-XL is a simulator that allows you to test the logic of a design. The process of logic simulation in Verilog-XL is as follows: 1. Describe the design to Verilog-XL. 2.

More information

Synthesis from VHDL. Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology Sweden

Synthesis from VHDL. Krzysztof Kuchcinski Department of Computer Science Lund Institute of Technology Sweden Synthesis from VHDL Krzysztof Kuchcinski Krzysztof.Kuchcinski@cs.lth.se Department of Computer Science Lund Institute of Technology Sweden March 23, 2006 Kris Kuchcinski (LTH) Synthesis from VHDL March

More information

Introduction to Verilog

Introduction to Verilog Introduction to Verilog COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Hardware Description Language Logic Simulation versus Synthesis

More information

Software Engineering 2DA4. Slides 2: Introduction to Logic Circuits

Software Engineering 2DA4. Slides 2: Introduction to Logic Circuits Software Engineering 2DA4 Slides 2: Introduction to Logic Circuits Dr. Ryan Leduc Department of Computing and Software McMaster University Material based on S. Brown and Z. Vranesic, Fundamentals of Digital

More information

1 ST SUMMER SCHOOL: VHDL BOOTCAMP PISA, JULY 2013

1 ST SUMMER SCHOOL: VHDL BOOTCAMP PISA, JULY 2013 MARIE CURIE IAPP: FAST TRACKER FOR HADRON COLLIDER EXPERIMENTS 1 ST SUMMER SCHOOL: VHDL BOOTCAMP PISA, JULY 2013 Introduction to VHDL Calliope-Louisa Sotiropoulou PhD Candidate/Researcher Aristotle University

More information

Design units can NOT be split across different files

Design units can NOT be split across different files Skeleton of a Basic VHDL Program This slide set covers the components to a basic VHDL program, including lexical elements, program format, data types and operators A VHDL program consists of a collection

More information

ECE 3401 Lecture 10. More on VHDL

ECE 3401 Lecture 10. More on VHDL ECE 3401 Lecture 10 More on VHDL Outline More on VHDL Some VHDL Basics Data Types Operators Delay Models VHDL for Simulation VHDL for Synthesis 1 Data Types Every signal has a type, type specifies possible

More information

Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28

Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28 99-1 Under-Graduate Project Verilog Simulation & Debugging Tools Speaker: Shao-Wei Feng Adviser: Prof. An-Yeu Wu Date: 2010/09/28 ACCESS IC LAB Outline Basic Concept of Verilog HDL Gate Level Modeling

More information