NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni


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1 NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering EE6301 Digital Logic Circuits PartA (10 x 2 = 20 Marks) 1. What is meant by Non weighted Code? 1. Determine (377) 10 in Octal and HexaDecimal equivalent. 1. Compare the totem pole output with open collector output? 1. Which IC family offers a) Low Propagation delay and b) Low Power Dissipation? 1. Give examples for weighted codes. 2. Why should we take care while using CMOS devices? 2. What are the advantages of ECL over TTL? 2. Compare the propagation delay and power dissipation characteristics of ECL and CMOS. 2. What are the advantages of CMOS? 2. Show that the Excess 3 code is selfcomplementing. 3. Realize XOR gate using suitable MUX. 3. How many don t care condition will be there in the truth table of a BCD adder? 3. Plot the function F= (0, 1, 3, 7) on KMap? 3. Define essential and Nonessential prime implicant. 3. Define Carry look ahead logic.
2 4. Define Multiplexer. 4. State Demorgan s theorem. 4. How does don t care condition in K map help for circuit simplification. 4. Draw the truth table and logic circuit of half adder. 4. Convert the given expression in Canonical SOP form Y= AC+AB+BC 5. Write the excitation table for JK Flip Flop. 5. Write the Characteristic table for SR Flip Flop. 5. Write the characteristic equation of JK Flip Flop. 5. What are the different types of Shift register? 5. How does the state transition diagram of a Moore model differ from Mealy model? 6. State the rules for State Assignment. 6. Convert T flip flop to D flip flop. 6. What is the drawback of RS flip flop? 6. How many flip flops are required to design mod 25 counter? 6. Draw truth table for JK flip flop. 7. What are the disadvantages of asynchronous sequential circuit? 7. Define racing? 7. What is the difference between asynchronous and synchronous sequential circuits? 7. What is the difference between flow table and Transition table? 7. Differentiate Critical race and NonCritical race. 8. Name the types of ROM. 8. State the hazard in asynchronous sequential circuits.
3 8. What is meant by transition table? 8. Draw the block diagram of PLA. 8. What is fundamental mode of operation in asynchronous sequential sequential circuits? 9. When can RTL be used to represent digital systems? 9. What is the function of wait statement in VHDL package? 9. What is the meaning of the following RTL Statement? T 1 : ACC ACC and MDR 9. Write a VHDL code for 2x1 MUX. 9. State the advantage of package declaration over component declaration. 10. What is a test bench? 10. List out the operators used in VHDL. 10. Write the VHDL code for Half adder. 10. What is a package in VHDL? 10. Write the behavioral modeling code for a D Flip Flop. Part B ( 5 x 13 = 65 Marks) 11.a. 11.a. (i)convert the binary number to its equivalent decimal number (ii) Convert the number to its equivalent decimal number. (iii) Convert the following binary number to its hexadecimal equivalent (iv) Convert to its octal equivalent. (13) (i) Draw and explain the circuit diagram of an ECL ORNOR gate. (ii) Explain the working of a CMOS logic gate. (13)
4 11.a. (i)perform the following addition using BCD and Excess3 addition ( ). (7) (ii) Encode the binary word 1011 into seven bit even parity Hamming code. (6) 11.a. (i) With circuit schematic, explain the operation of a two input TTL NAND gate with totempole output. (ii) Compare totem pole and open collector outputs. (13) 11.a. Compare the characteristic features of TTL, ECL, CMOS digital logic families. (13) 11.b. (i)given that a frame with bit sequence is transmitted, it has been received as Determine the method of detecting the error using any one error detecting code. (ii)draw the MOS logic circuit for NOT gate and explain its operation. (13) 11.b. What are the different types of binary codes? Explain each in detail? (13) 11.b. (i)explain Hamming code with an example. State its advantages over parity codes. (ii)design a TTL logic circuit for a 3input NAND gate. (13) 11.b. Discuss in detail the various manipulations in binary number system. (13) 11.b. Write short notes on error detection and correction codes with suitable examples. (13) 12.a. 12.a. 12.a. (i)simplify the following using Kmap X=A B+A B C+ABC +AB C (5) (ii)convert SOP into equivalent POS. A B C + A B C+A BC+AB C+ABC (4) (iii)using Boolean laws and rules simplify the logic expression. Z=(A +B)(A+B) (4) (i) Realize the Boolean expression f= m (4, 5, 7, 8, 10, 12, 15) using 4 to 1 line multiplexer and external gates. (8) (ii) Write about BCD adder in detail. (5) Design a combinational circuit that converts 4 bit Gray code to a 4 bit binary number. Implement the circuit. (13) 12.a. (i)design a 4x1 multiplexer circuit. (5)
5 (ii)implement the function using multiplexer F= (0, 1, 3, 4, 8, 9, 15). (8) 12.a. (i) How is the carry look ahead adder faster than a ripple carry adder? Explain in detail with neat sketches. (6) (ii) Express the Boolean functions F=A+B C in a sum of minterms. (7) 12.b. (i) Reduce the following function using Kmap. F(A,B,C,D)=ΠM(0,2,3,8,9,12,13,15). (ii)design a full adder using two half adders and an OR gate. (13) 12.b (i)design a BCD to Excess 3 code converter. (ii) Design a 2421 to excess3 code converter. (13) 12.b. (i)minimize the function F(a,b,c,d)= (0,4,6,8,9,10,12) with d= (2,13).Implement the function using only NOR gates.(ii)design a full subtractor and implement it using logic gates. (13) 12.b. Design a Combinational circuit which converts Excess 3 code to BCD code. (13) 12.b. Design a combinational circuit that converts a decimal digit from the 2, 4, 2, 1 code to the 8, 4, 2, 1 code. (13) 13.a. (i) Define triggering and mention its types. (3) (ii)explain the working of an RS Flip Flop and discuss its limitation. (5) (iii)describe the operation of masterslave JK flip flop. (5) 13.a. What are the applications of counters? Design a counter to count the following sequence (13) 13.a. (i) Describe a JK FF with its characteristic table and characteristic equation. (6) (ii)with a neat sketch describe a 3 bit synchronous up/down counter. Draw the timing waveform. (7) 13.a. Design a sequential circuit with two D FFs A and B and one input x. When x=0, the state of the circuit remains the same. When x=1, the circuit goes through the state transitions from
6 13.a. Design a sequential pattern detector that receives a stream of input bits. The circuit should recognize the pattern 010 and produce an output whenever this pattern is received. (13) 13.b. (i)explain the functioning of a recirculating shift register with various modes of operation. (7) (ii)discuss the working of a 4 bit Johnson counter with a neat block diagram. (6) 13.b. (i) Design a 3 bit bidirectional shift register. (ii) Design a MOD5 synchronous counter using JK flip flops. (13) 13.b. Design a BCD ripple counter using JK flip flop. (13) 13.b. Design a BCD counter using T flip flop. (13) 13.b. Design a sequential pattern detector that receives a stream of input bits. The circuit should recognize the pattern 010 or 110 and produce an output whenever these patterns are received. (13) (i)implement binary to excess 3 code converter using ROM. (ii) Illustrate the concept of 16x8 bit ROM arrangement with a diagram. (13) (i) Explain programmable array logic. (ii) Explain the term hazard with reference to combinational circuit with an appropriate example in brief. (13) Explain the problem of non critical and critical races in asynchronous sequential circuits with suitable examples. (13) An asynchronous sequential circuit is described by the excitation and output functions. Y= X 1 X 2 + (X1 + X 2 ) y: z=y. Draw the logic diagram of the circuit. Also derive the transition table and output map. (13) Explain the structure of PAL and PLA. How a combinational logic function is implemented in PAL and PLA? Explain with an example for each. (13)
7 14.b. (i)explain the different types of hazards. Design a hazard free circuit for y=x 1 x 2 + x 2 x 3. (7) (ii)implement the following function using PLA: F(x,y,z)= m(1,2,4,6) (6) 14.b. Design an asynchronous sequential circuit that has two inputs X 2 and X 1 and one output Z. When X 1 =0, the output Z is 0. The first change in X 2 that occurs while X 1 is 1 will cause output Z to be 1. The output Z will remain 1 until X 1 returns to 0. (13) 14.b. (i)design a ROM to convert 6 bit binary number to its corresponding 2digit BCD number. (7) (ii) Derive the PLA program table for a combinatorial circuit that squares a 3 bit number. Minimize the number of product terms. (6) 14.b. Illustrate the analysis procedure of asynchronous sequential circuit with an example. (13) 14.b. 15.a. (i)design a combinatorial circuit using ROM. The circuit accepts 3bit binary number and generates an output binary number equal to the square of the input number. (ii) Repeat the above problem using PLA. (13) Write the VHDL code to realize a full adder using (i) Behavioral modeling (ii) Structrural modeling. (13) 15.a. Write the VHDL code to realize a 3bit Gray code counter using case statement. (13) 15.a. Write VHDL code for Binary UP/DOWN counter using JK Flip Flops. (13) 15.a. 15.a. (i)explain in detail the various programming constructs used in VHDL for designing a logic circuit. (ii)discuss the various packages. Write a VHDL code for the implementation of a demultiplexer.(13) (i) Write HDL for two to one line multiplexer with data flow description and behavioral description.(ii)write HDL for four bit adder. (13) 15.b. Write HDL for four bit binary counter with parallel load and explain. (13) 15.b. Write VHDL code for full adder and 8x1 multiplexer. (13)
8 15.b. Write VHDL code for JK master slave flip flops and using JK Flip Flop as structural element write code for 4 bit Asynchronous counter. (13) 15.b. Write the VHDL code for mod 6 counter. (13) 15.b. Describe the RTL in VHDL. (13) Part C ( 1 x 15 = 15 Marks) 16.a. A sequential circuit has 2D ff s A and B an input x and output y is specified by the following next state and output equations. A (t+1)= Ax + Bx B (t+1)= A x Y= (A+B) x i) Draw the logic diagram of the circuit. ii) Derive the state table. iii) Derive the state diagram. (15 marks) 16.a. Discuss in detail where you come across digital system design in your real life scenario with suitable illustrations and examples. Also possibly quote wherever field it is being applied. 16.a. Design a asynchronous sequential circuit with 2 inputs T and C. The output attains a value of 1 when T = 1 & C moves from 1 to 0. Otherwise the output is 0. (15 Marks) 16.a. 16.a. 16.b. Design a sequence detector that produces an output 1 whenever the nonoverlapping sequence 1010 is detected. Design a 2 bit synchronous UP/DOWN counter using T flip flop. Consider a JK flip flop, i.e, a JK flop flop with an inverter between external input K and internal input K. Obtain the flip flop characteristic table. Obtain the Characteristic equation. Show that tying the two external inputs together forms a D flip flop.
9 16.b. Design a combinational circuit whose input is a 4 bit number and whose output is the 2 s complement of the input number. 16.b. Implement the Boolean function F(A,B,C,D)= (0,1,3,4,8,9,15) with an 8x1 Multiplexer with A, B and D connected to selection lines s 2, s 1, and s 0, respectively. 16.b. Where will you apply the pattern detector concept in your real time life? Justify your answer by designing a suitable application with the help of pattern detector concept. 16.b. Develop an algorithm and flowchart for monitoring the traffic in a signal using traffic light controller. (Assume only Digital related concept).
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