EECS 140/141 Introduction to Digital Logic Design Spring Semester 2017 Exam #1 Date: 27 February 2017


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1 EECS 4/4 Introduction to Digital Logic Design Spring Semester 27 Exam # Date: 27 February 27 NAME: KUID: General Instructions. This exam is closedbook. You are allowed a noncommunicating calculator and one side of one page (8.5" X ") of notes. 2. A reference sheet of the Boolean Algebra axioms and properties is supplied for your use. 3. Put your KUID on each page, in case the exam pages get separated. 4. There are points possible on this exam. 5. When logic network diagrams are requested, you must draw them using your logic template. Failure to do this will be penalized. 6. Clearly indicate your final answer to each problem by putting a box around it (not necessary for logic network diagrams). 7. Show your work: a. If your answer is incorrect, partial credit may be awarded based on the work shown. Even if your answer is correct, you will not receive full credit unless you have shown some work on the exam pages. b. In particular, if you are asked to prove a relationship using algebraic manipulations from Boolean Algebra, you should justify each step with a property number from the Boolean Algebra reference sheet. c. Show all work on the exam pages. Ihave tried to leave lots of room for you to show (and check) your work. Please do not use any other pages unless absolutely necessary. If you do use other paper, clearly indicate on the problem page that there is additional work elsewhere (and where that additional work is). d. You may use the logic network diagrams and Kmaps printed on the exam pages to show some of your work  you do not need to recopy them unless you wish to. e. The bottom line is this: the easier it is for me to figure out what you are trying to do, the more likely I will be to award partial credit. 8. Stay calm. If you are having trouble with one problem (or part of a problem), leave it and go on. Even if you are not able to work one part of a problem, you may still be able to work subsequent parts. Prof. Petr Copyright 27 David W. Petr Spring 27
2 EECS 4/4 Exam # 2 KUID:. This problem has to do with the following mintermform specification for a logic function: F(A, B, C, D) =Σm(, 3, 4, 6, 8,, 4) a. (8 points) Draw the Truth Table for this function in the space below. You must list the 4 variables in the order given (A on the left and D on the right). b. (8 points) Draw the Karnaugh Map (KMap) for this function in the space below. You must list the values for the AB pair across the top and the values for the CD pair down the side. Prof. Petr Copyright 27 David W. Petr Spring 27
3 EECS 4/4 Exam # 3 KUID: 2. ( points) Prove the following Boolean identity using Boolean Algebra properties. Each step must use one and only one Boolean Algebra property from the provided reference sheet (but you may use the same property more than once in one step). Identify which property that you used for agiven step with the number of the property. You may not use a Truth Table or Kmap or Venn diagram to prove the identity. B(A + C) = ABC + ABC + ABC Prof. Petr Copyright 27 David W. Petr Spring 27
4 EECS 4/4 Exam # 4 KUID: 3. This problem deals with the following KMap for function F(A,B,C). Each d in the KMap indicates a do n t care output. C AB d In this problem, you will be working with a Product of Sums (PoS) synthesis for this function, as follows: a. (3 points) Identify all of the PoS Prime Implicants (PIs) for this logic function, writing a logic expression for each one. b. (3 points) Identify all of the PoS Essential Prime Implicants (EPIs) for this logic function, writing a logic expression for each one. c. (3 points) Find the minimumcost PoS synthesis for this function; write an expression for it. Prof. Petr Copyright 27 David W. Petr Spring 27
5 EECS 4/4 Exam # 5 KUID: d. (3 points) Find the cost (as we have defined it in this course) for your minimumcost PoS synthesis in part (c). e. (8 points) In the space below, draw (using your logic template) the logic network for your minimumcost PoS synthesis in part (c), using only NOR gates; you should use only NOR gates even for generating the complement of an input (normally done by a NOT gate). Prof. Petr Copyright 27 David W. Petr Spring 27
6 EECS 4/4 Exam # 6 KUID: 4. This problem deals with the following KMap for function G(A,B,C,D). AB CD In this problem, you will be working with several different syntheses for this function, as follows: a. (3 points) If you were to synthesize this function with a Canonical Sum of Products (CSoP) synthesis, what would be its cost? Note that you do not have to actually find such asynthesis. b. (3 points) If you were to synthesize this function with a Canonical Product of Sums (CPoS) synthesis, what would be its cost? Note that you do not have to actually find such asynthesis. Prof. Petr Copyright 27 David W. Petr Spring 27
7 EECS 4/4 Exam # 7 KUID: The remaining parts deal with finding a minimumcost Sum of Products (SoP) synthesis for this function. c. (4 points) For a Sum of Products (SoP) synthesis, identify all of the Prime Implicants (PIs) for this logic function, writing a logic expression for each one. d. (4 points) Identify all of the Essential Prime Implicants (EPIs) for this logic function, writing a logic expression for each one. e. (6 points) Construct the minimumcost SoP synthesis for this function. You must explain how you constructed your synthesis; that is, give the order in which you added product terms, and why you chose each product term. When you have constructed the synthesis, write an expression for it. Youshould not draw alogic diagram for your synthesis. Prof. Petr Copyright 27 David W. Petr Spring 27
8 EECS 4/4 Exam # 8 KUID: 5. Two functions P and Q both have the same set of inputs (e, g,h,j). The KMap of each function is given below. hj eg hj eg Function P Function Q The minimumcost Sum of Products (SoP) synthesis for each function is given below, along with the cost (as we have defined it in this course) of each individual function: P = e g + e g + (either e h jorg h j) cost = 4 Q = h j + e h cost = 9 For this problem, you will focus on a jointlyminimized SoP synthesis for the 4input (e, g,h,j), 2output (P, Q) function. That is, your are trying to minimize the cost of the resulting 4input, 2output logic circuit. a. (8 points) Give a logic expression for each output (P and Q) that will result in a jointlyminimized Sum of Products (SoP) synthesis for the 4input, 2output function. Provide an explanation of your synthesis if you think it will be helpful. Prof. Petr Copyright 27 David W. Petr Spring 27
9 EECS 4/4 Exam # 9 KUID: b. (5 points) Draw the jointlyminimized, 4input, 2output logic circuit with AND/OR/NOT gates (using your logic template). c. (3 points) What is the cost (as we have defined it in this course) of your jointlyminimized, 4input, 2output logic circuit? Prof. Petr Copyright 27 David W. Petr Spring 27
10 EECS 4/4 Exam #  KUID: 6. ( points) This problem requires you to convert a word description of a situation into a Boolean Algebra logic expression. Students at a certain school are categorized as being either tall or short in height and either fast or slow in speed. To be eligible to be on the basketball team, a student must be either tall or fast. However, a student is ineligible (not eligible) to be on the team if the student has failed a class or if the student has failed a drug test. Let E be a binary variable that has value if astudent at this school is eligible to be on the basketball team and has value if the student is not eligible. Using the rules given above, write a Boolean expression for the function E in terms of FOUR binary inputs. Use Boolean Algebra properties as needed to express E in a Sum of Products (SoP) form. Youdo not need to identify each Boolean Algebra property that you use. Your expression for E need not (indeed, should not) be in Canonical Sum of Products (CSoP) form. You do need to clearly define each of the FOUR "input" variables and what each variable s binary values represent. Notice that I have done this for the binary "output" variable (E) that represents whether or not astudent at this school is eligible to be on the basketball team. There is more space for this problem on the next page. Prof. Petr Copyright 27 David W. Petr Spring 27
11 EECS 4/4 Exam #  KUID: More space for the problem on the previous page. Prof. Petr Copyright 27 David W. Petr Spring 27
12 EECS 4/4 Exam # 2 KUID: 7. (8 points) This problem concerns the NMOS logic circuit shown below inv olving three NMOS transistors (A, B, and C). R Hi V F V B V A V C Lo Recalling the operation of NMOS transistors, fill in the value (Hi or Lo) for the output voltage V f for each combination of input voltage values given inthe table below. V A V B V C V F Lo Lo Lo Lo Lo Hi Lo Hi Lo Lo Hi Hi Hi Lo Lo Hi Lo Hi Hi Hi Lo Hi Hi Hi Prof. Petr Copyright 27 David W. Petr Spring 27
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