INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad


 Eunice Griffin
 4 years ago
 Views:
Transcription
1 INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : Coordinator : Mr. C Srihari,Assistant Professor, Department Of ECE Faculty : Mr. Mohd. Khadir, Assistant Professor, Department Of ECE Mrs. J Swetha, Assistant Professor, Department Of ECE Mrs. C DeviSupraja, Assistant Professor, Department Of ECE COURSE OBJECTIVES: The course should enable the students to: S. No Description I Analyze and explore the uses of logic functions for building digital logic circuits II Explore the combinational logic circuits. III Examine the operation of sequential (synchronous and asynchronous) circuits IV Know the concepts of basic memory system.. COURSE LEARNING OUTCOMES: Students, who complete the course, will have demonstrated the ability to do the following: CAEC CAEC CAEC CAEC CAEC CAEC CAEC CAEC CAEC number systems, binary addition and subtraction, 2 s complement representation and operations with this representation and understand the different binary codes. Explain switching algebra theorems and apply them for logic functions. Identify the importance of SOP and POS canonical forms in the minimization or other optimization of Boolean formulas in general and digital circuits. Discuss about digital logic gates and their properties. Evaluate the functions using various types of minimizing algorithms like Boolean algebra. Evaluate the functions using various types of minimizing algorithms like Karnaugh map method. Design and implementation of Gate level minimization using KMaps. Analyze the design procedures of Combinational logic circuits. bistable elements and different types of latches and flipflops. Analyze the design procedures of small sequential circuits. the concept of Shift Registers. Analyze the design procedures of Synchronous Counters.(Johnson Counters, Ring Counters). 1 P a g e
2 3 4 5 Analyze the design procedures of Asynchronous Counters(Ripple Carry Counter). and analyze the design of a Programmable logic devices (PLA s,pal s). Design various arithmetic, logic, and memory components, e.g., ALUs, Shifters, Decoders, Multiplexers, RAMs, and ROMs; TUTORIAL QUESTION BANK S. No Question UNITI NUMBERS SYSTEMS AND CODES PARTA(Short Answer Questions) 1. Write short notes on binary number systems? 2. Discuss 1 s and 2 s complement methods of subtraction? 3. Discuss octal number system? 4. Discuss about BCD code? 5. Solve If (2.3) 4 +(1.2) 4 =(y) 4 then find y? 6. Write a short note on four bit BCD codes? 7. Explain the specialty of unit distance code? State where they are used? 8. Write a short note on error correcting codes? 9. Solve (127) 8 to all number systems? 10. Discuss what a logic design is and what do u mean by positive logic system? 11. Convert (4085) 8 into base5? 12. Convert (4085) 8 into base3? 13. Write the steps involved in unsigned binary subtraction using complements with examples? 14. Explain the addition of two signed binary number along with examples? 15. Differentiate between binary code and BCD code? 16. Solve subtraction between 95 using xs3? 17. Convert (4085)9 into base4? 18. Convert to octal equivalent and hexadecimal equivalent 19. Convert the octal numbers into binary,decimal and Hexadecimal numbers (45.5)octal,(32.2)octal 20. Convert the following Hexadecimal numbers to their Dec equivalent EAF1 PARTB(Long Answer Questions) 1. (a) Solve the subtraction with the following unsigned binary numbers by taking the 2's complement of the subtrahend: i ii (b) Construct a table for weighted code and write 2421 using this code.write short notes on binary number systems. 2. (a) Solve arithmetic operation indicated below. Follow signed bit notation: i ii (b) 2 P a g e
3 Explain the importance of gray code? 3. Solve ( ) 10 using 10's complement? 4. Explain Self complemented codes? 5. Solve (a) Divide by (b) Given that (292)10 =(1204)b determine `b' 6. Differentiate between BCD code and 2421 code and XS3? 7. Solve (a) Find ( ) using 9's complement. (b) Show the weights of three different 4 bit self complementing codes whose only negative weight is  4 and write down number system from 0 to Solve ( ) 10 using 9's complement with XS3? 9. State using XS3? 10. Solve the following numbers, (a) Add by (b) Given that (292) 10 =(1204) b determine `b' 11. Solve (a) What is the gray code equivalent of the Hex Number 3A7 (b) Find 9's complement (25.639) Apply the representation of +65 and 65 in sign magnitude, Sign 1 s complement and sign 2 s complement representation? 13. State different ways for representing the signed binary numbers? 14. Solve addition and subtraction of (456) and (341) using BCD and XS3? 15. Define weighted codes and non weighted codes with examples? 16. Explain what do you mean by error detecting and correcting codes? 17. Illustrate the rules for XS3 addition and subtraction? 18. Explain error occurred in the data transmission can be detected using parity bit? 19. Solve addition between 95 and 62 using BCD and XS3 Method? 20. Solve subtraction 67 and 73 using BCD and Xs3 Method? PARTC(Problem Solving Critical Thinking Questions) 1. Solve Subtraction and Addition 617 and 732 using BCD and Xs3 Method? 2. Convert the octal numbers into binary, decimal, BCD and Hexadecimal numbers (36.6) 8,(45.5) 8,(26.3) 8,(48) Solve Subtraction and Addition 4327 and 1562 using BCD and Xs3 Method? C 4. Find transmitted 11 bits for when hamming code is used? 5. Explain about Codes? 6. write the octal representation of the following fractional numbers:(0.5)d,( 1.5)d, (2.333)d,( 3.875)d, (13.125)d, (14.666)d. 7. Find the illegal representation in the following: (120A)d, 3 P a g e
4 ( )BCD, (0208)octal, ( )b, (GC0A)h. 8. Convert the binary number to hexadecimal number: i , ii Convert the hexadecimal number to binary number: 0x5A9F, 42D by two examples that two s compliment of a number taken twice returns the original number? UNITII BOOLEAN ALGEBRA AND GATE LEVEL MINIMIZATION PARTA(Short Answer Questions) 1. Define Kmap? Name its advantages and disadvantages? CAEC Define Implicant, Prime Implicant and Essential Prime CAEC020.2 Implicant? 3. Define Consensus Theorem? CAEC Describe types of minimization techniques? CAEC Summarize the Boolean function x yz + x yz + xy z + xy z CAEC020.2 using Kmap? 6. Explain three variable kmap with example? CAEC Solve AB 1 +BC+CA=AB+BC CAEC Design the two graphic symbols for NAND gate? CAEC Design the two graphic symbols for NOR gate? CAEC Summarize the Boolean function x yz + x yz + xy z + xy z CAEC020.6 without using K map? 11. Explain the properties of EXOR gate? CAEC Solve the function of fig with ANDOR INVRET implementation CAEC Solve the following Boolean function using Kmap CAEC Solve the following using NAND gates? a) (A+B)(C+D) b) A.B+CD(AB I +CD) CAEC Sketch the following equation using kmap and realize it using CAEC020.6 NAND gate? Y= m(4,5,8,9,11,12,13,15) 16 Solve Y=AB I +CD+(A I B+C I D I ) using NAND gate? CAEC State that ANDOR network is equivalent to NANDNAND CAEC020.2 network? 18 Show both NAND and NOR gates are called Universal gates? CAEC P a g e
5 19 Sketch the following logic function using kmap and implement it using logic gates? Y(A,B,C,D)= m(0,1,2,3,4,7,8,9,10,11,12,14) CAEC Summarize the rules and limitations of Kmap simplification? CAEC Analyze the steps for simplification of POS expression? CAEC020.6 PARTB(Long Answer Questions) 1. A combinational circuit has 4 inputs(a,b,c,d) and three outputs(x,y,z)xyz represents a binary number whose value equals the number of 1's at the input (i) state the minterm CAEC020.6 expansion for the X,Y,Z (ii). state the maxterm expansion for the Y and Z 2. Minimize the following function using Kmap. F (A, B, C, D) = m (1,3,5,7,9,10,11,12,15) CAEC Minimize the following function using Kmap f = m CAEC020.6 (1,2,3,5,12,13,15) 4. Design BCD to Gray code converter and realize using logic CAEC020.2 gates? 5. Design all logic gates using Nand? CAEC compile the following expression using Karnaugh map (B A + CAEC020.2 A B + AB ) 7. Design a circuit with three inputs(a,b,c) and two outputs(x,y) CAEC020.6 where the outputs are the binary count of the number of ON" (HIGH) inputs? 8. Implement the INVERTER gate, OR gate and AND gate using CAEC020.2 NAND gate, NOR gate? 9. Design a circuit with four inputs and one output where the CAEC020.2 output is 1 if the input is divisible by 3 or 7? 10. Implement Half adder using 4 NAND gates? CAEC Implement the Boolean function F = AB + CD + E using CAEC020.6 NAND gates only? 12. Summarize the Boolean function F(w, x, y, z) = Σ(1, 3, 7, 11, CAEC ) + Σd(0. 2, 5) 13. Implement following expression f= a+b+c in to canonical sop CAEC020.6 and convert it to pos using kmap 14. Implement following expression f= abc in to canonical pos CAEC020.6 and convert it to sop using kmap 15. Identify all the prime implicants and essential prime implicants CAEC020.6 of the following functions Using k map F = Σm (0, 1, 2, 3, 4, 10, 11, 14, 15) 16. Identify all the prime implicants and essential prime implicants of the following functions Using k map. F(A,B,C,D) = Σm(0,1,2,5,6,7,8,9,10,13,14,15). CAEC Identify all the prime implicants and essential prime implicants of the following functions Using k map. CAEC P a g e
6 F(A,B,C) = Σm(0,1,2,6,7).+ d(3,5) 18. Design alternate symbols for all the gates CAEC Design all the logic gates using NOR gate CAEC Identify all the prime implicants and essential prime implicants of the following functions Using k map. F(A,B,C,D) = πm(0,1,2,5,6,7,8,9,10,13,14,15). CAEC020.6 PARTC(Problem Solving Critical Thinking Questions) 1. Use DeMorgan theorem to simplify F=(A+B+C.D.E) 1. CAEC State that for constructing XOR from NANDs we need four CAEC020.2 NAND gates? 3. Convert A.B.C+A.D expression into standard SOP format? CAEC Convert (A+B+C).(A+D) expression into standard POS CAEC020.2 format? 5. Construct XOR and XNOR from NAND and NOR gates? CAEC Construct SOP expression and POS expression for a four input CAEC020.2 NAND gate? 7. and explain five variable kmap with an example? CAEC Find the logic function F=(AB+BC+E) 1 using ANDOR two level realization? CAEC Design a 5variable k map. F(A,B,C,D,E) = CAEC020.6 πm(0,1,2,5,6,7,8,9,10,13,14,15,17,19,20).πd(3,25,28,30,31) 10 Design a 5variable k map. F(A,B,C,D,E) = CAEC020.6 m(0,1,2,5,6,7,8,9,10,17,19,20)+ d(3,12,15,18,25,28,30,31) UNITIII DESIGN OF COMBINATIONAL CIRCUITS PARTA(Short Answer Questions CIE I) 1. Explain the design procedure for combinational circuits? 2. Apply various code conversion methods? 3. Design a 4bit binary to BCD converter? 4. Design and implement a 8421 Gray code converter? Design a combinational logic circuit with 3 input variables that 5. will produce logic 1 output when more than one input variables are logic 1? 6. Compose and explain the block diagram of 4bit parallel adder? 7. Design a logic circuit to convert BCD and gray code? 8. Design a full adder using two half adders? 9. Explain magnitude comparator? Design a 1bit comparator using logic gates? 10. Compose the circuit for 3 to 8 decoder and explain it with logic gate? PARTA(1) (Short Answer QuestionsCIE II) 1. Construct the logic circuit for full subtractor using decoder? 2. Define binary decoder? Explain the working of 2:4 binary decoder? 3. Design Full adder using a suitable Decoder? 6 P a g e
7 4. Define encoder? Design octal to binary encoder? 5. Design a 4bit priority encoder? 6. Design the block diagram of a 4:1 multiplexer using 2:1 multiplexer? 7. Define Multiplexer and demultiplexer? 8. Explain how decoder acts as a demultiplexer? 9. Differentiate multiplexer and demultiplexer? 10. Explain the working of 8:1 multiplexer? PARTB(Long Answer QuestionsCIEI) 1. Design a combinational circuit that generates logic 1 for odd inputs? 2. Design a logic circuit to convert gray code to binary code? 3. Design circuit to detect invalid BCD number and implement using NAND gate only? 4. Explain the design procedure for code converter with the help of example? 5. Construct half subtractor using NAND gates? 6. Explain the working of carry lookahead generator? 7. Explain carry propagation in parallel adder with neat diagram? 8. Explain the circuit diagram of full subtractor and full adder? 9. Construct and explain the working of decimal adder? 10. Design 2digit BCD adder with the help of binary adders? 11. Design Full Adder using NAND gates? PARTB(1)(Long Answer QuestionsCIEII) 12. State the procedure to implement Boolean function using decoder and also mention the uses of decoders? 13. Design Multiply by using binary multiplication method? 14. Design an 2bit Magnitude Comparator? 15. Summarize the following Boolean function using 8:1 mux F(A,B,C,D)=πM(0,3,5,8,9,10,12,14) 16. Design and implement a full adder circuit using a 3:8 decoder? 17. Design Full Subtractor using NAND gates? 18. Design Full Subtractor using NOR gates? 19. Design Full Adder using NOR gates? 20. Design 4 input Priority Encoder? PARTC(Problem Solving Critical Thinking Questions CIEI) 1. Design a combinational logic circuit that produces the product of 2 binary number of following function A=(A 1,A 0 )*B=(B 1, B 0 ) 2. Solve the function using multiplexer F(x,y,z)= (0,2,6,7) 3. A combinational circuit has 4 inputs(a,b,c,d) and three outputs(x,y,z)xyz represents a binary number whose value equals the number of 1's at the input: i. Find the minterm expansion for the X,Y,Z ii. Find the maxterm expansion for the Y and Z 4. Design a combinational logic circuit with 4 inputs A, B, C, D. 7 P a g e
8 The output Y goes High if and only if A and C inputs go High. i. Draw the truth table. ii. Minimize the Boolean function using Kmap. iii. Draw the circuit diagram? 5. Design a logic circuit to convert excess3 code to BCD code? 6. Design a logic circuit to convert BCD code to XS3 code? PARTC(1)( Problem Solving Critical Thinking Questions CIEII) 7. Design a multiple circuit to multiply the following binary number A=A 0 A 1 A 2 A 3 and B=B 0 B 1 B 2 B 3 using required number of binary parallel adders? 8. Solve the following Boolean functions using decoder and OR gates: F 1 (A,B,C,D)= (2,4,7,9) F 2 (A,B,C,D)= (10,13,14,15) 9. Solve the following Boolean functions using decoder and OR gates: F 1 (A,B,C,D)= (3,5,6,8) F 2 (A,B,C,D)= (11,12,13,15) 10. Solve the following Boolean function using 8:1 mux F(A,B,C,D)= m(1,3,5,7,8,9,0,2,,13) 11. Solve the following Boolean function using 8:1 mux F(A,B,C,D)= m(1,3,5,7,8,9,0,2,10,12,13) UNITIV DESIGN OF SEQUENTIAL CIRCUITS PARTA(Short Answer Questions) 1. Differentiate combinational and sequential logic circuits? CAEC Explain basic difference between a shift register and counter? CAEC Illustrate applications of shift registers? 2 4. Define bidirectional shift register? 2 5. Differentiate Flipflop and latch? 2 6. Define Counter? 2 7. Classify the basic types of counters? 2 8. Differentiate the advantages and disadvantages of ripple 2 counters? 9. Describe the applications of Counters? Design Dlatch using NAND? Design and explain gated latch logic diagram? Define race around condition? How it can be avoided? 13. Convert a JK Flip Flop to i) SR ii) T iii) D Convert a SR FlipFlop to i) JK ii) D iii) T Explain what is a synchronous latch? Construct a latch using universal gates? Explain what do you mean a stable state? Define a FlipFlop? Define applications of FlipFlops? 2 8 P a g e
9 20. Explain what is meant by clocked flipflop? 2 PARTB(Long Answer Questions) 1. Explain the design of Synchronous Sequential circuit with an CAEC020.9 example? 2. Write short notes on shift register? Mention its application CAEC020.9 along with the Serial Transfer in 4bit shift Registers? 3. Explain about Binary Ripple Counter? What is MOD counter? 2 4. Define BCD Counter and Draw its State table for BCD 2 Counter? 5. Explain the state reduction and state assignment in designing 2 sequential circuit. Consider one example in the above process? 6. Design a sequential circuit with two D flipflops A and B. and 2 one input x. When, x=0, the state of the circuit remains the same. When, x=1, the circuit goes through the state transition from 00 to 11 to 11 to 10 back to 00.and repeats? 7. Design a Modulo12 up Synchronous counter Using TFlip Flops and draw the Circuit diagram? 2 8. Explain the Ripple counter design. Also the decade counters 2 design? 9. Design a 3 bit ring counter? Discuss how ring counters differ 2 from twisted ring counter? 10. Design a Johnson counter? Design Johnson counters and state its advantages and 2 disadvantages? 12. Explain with the help of a block diagram, the basic components 2 of a Sequential Circuit? 13. Explain about RS and JK flipflops? Define T Flipflop with the help of a logic diagram and 2 characteristic table? 15. Define Latch. Explain about Different types of Latches in 2 detail? 16. Define JK Flipflop with the help of a logic diagram and 2 characteristic table? 17. List the characteristic equations for all FlipFlops? Construct the transition table for the following flipflops 2 i) SR FF ii) ii) D FF 19. Describe the steps involved in design of asynchronous 2 sequential circuit in detail with an example? 20. Differentiate Synchronous and Asynchronous counters? 2 PARTC(Problem Solving Critical Thinking Questions) 1. Explain the JK and Master slave Flipflop? Give its timing waveform? 2 9 P a g e
10 2. A sequential circuit has 3 flipflops, A,B and C and one input,x it is described by the following flip flop input functions? D A =(BC I +B I C)x+(BC+B I C I )x I D B =A D C =B i)derive the state table for circuit ii)draw two state diagrams: One for x=0 and for x=1 3. Design and implement 4bit binary counter (using D flip flops) which counts all possible odd numbers only? 4. Design Moore Machine and draw state diagram and assignment? 5. Design Mealy Machine and draw state diagram and assignment? 6. Design a MOD5 synchronous counter using flip flops and implement it? Also draw the timing diagram? 7. Design a Ring counter using JK flipflop? 2 8. Design a Twisted Ring counter using JK flipflop? 2 9. Design MOD5 up and Down counter? 3 UNITV MEMORY PARTA(Short Answer Questions) 1. Explain what is PROM? 4 2. Explain in detail about RAM and types of RAM? 4 3. Illustrate the features of a ROM cell? 4 4. Explain in detail about ROM and types of ROM? 4 5. Explain is ROM is volatile Memory? 4 6. Describe what is meant by memory expansion? Mention its 4 limits? 7. List a note on magnetic tape? 4 8. State the advantages and disadvantages of magnetic tape and 5 magnetic disk? 9. Differentiate static and dynamic RAM? Explain what is the use of cache memory? Design and explain the following mapping techniques of cache: 5 a) Direct mapping b) Associative mapping 12. Explain different replacement algorithms in detail? Explain what is EPROM? Differentiate between PROM and EPROM? Explain what is EEPROM? Explain what is PLA? Explain how is the capacity of PLA specified? Explain what is PLD? Explain PLA with the help of block diagram? Explain the advantage of PROM over PLD? 4 10 P a g e
11 PARTB(Long Answer Questions) 1. List How many address bits are needed to operate a 2 K *8 5 ROM? 2. Construct a logic diagram of memory cell? 5 3. Distinguish between SRAM and DRAM? 5 4. Explain the read and write operation a RAM can perform? 4 5. Explain the operation of DRAM 5 6. Construct the signals of a 32*8 RAM with control input. Show 4 the external connections necessary to have a 128*8 RAM using decoder and replication of this RAM? 7. To implement 2bit squaring time no of address lines and data 5 lines used in ROM? 8. To implement 2bit multiplication time no of address lines and 4 data lines used in ROM? 9. Explain two way set associative mapping and four way set 5 associative mapping techniques with an example for each? 10. Explain how a program gets executed faster using a cache 4 memory? 11. Design a BCD to Excess3 code converter and implement using 5 Suitable PLA? 12. Construct the block diagram of PLA. Which are the teams 4 programmable? How inverter is useful in PLA construction at the output? 13. Sketch the PLA program table for the four Boolean functions. 5 Minimize the number of product terms? A(x,y,z)= (0,1,3,5) B(x,y,z)= (2,6) C(x,y,z)= (1,2,3,5,7) D(x,y,z)= (0,1,6) 14. Sketch a PLA circuit to implement the logic functions 4 A I BC+AB I C+AC I and A I B I C I +BC. 15. Explain in detail various cache memory organizations? Sketch the ROM for the four Boolean functions. Minimize the 5 number of product terms? A(x,y,z)= (1,2,4,7) B(x,y,z)= (0,1,3,5,6) C(x,y,z)= (0,2,4,5,7) D(x,y,z)= (3,5,6,7) 17. Explain the techniques used to perform the write operations in 5 cache memory? 18. Explain in detail about the operation of SRAM? Differentiate PAL with PLA with examples? Memory hierarchy design is based on the principle of Locality of reference. Explain the principle? 5 11 P a g e
12 PARTC(Problem Solving Critical Thinking Questions) 1. Solve the following two Boolean functions using a PLA having 3inputs,4 product terms and 2 outputs? F 1 (A,B,C)= (0,1,2,4) F 2 (A,B,C)= (0,5,6,7) 5 2. Design 1k*8 RAM using two 1k*4 IC? 5 3. Solve 2048*8 memories using 256*8 memory chip.also show 4 the memory address associated with each memory chip? 4. Calculate the utilization factor of tape, if the gap length is 0.5 in, the storage density S=3000 bytes/in and data storage capacity is 6 k bytes? 5. A two way set associative cache memory uses block of four words. The cache accommodate a total of 2048 words from main memory. The main memory size is 128k*32 i. Find how many bits are there in tag index, block and word field of address format? ii. Findthe size of cache memory? 6. Solve the following multi boolean function using 3*4*2 PLA PLD? F 1 (a 2, a 1, a 0 )= m(0,1,3,5) F 2 (a 2, a 1, a 0 )= m(3,5,7) 7. Design and implement 3bit binary to gray code converter using PLA? 8. Calculate the average access time of memory for a computer with cache access time of 100ns,a main memory access of 1000ns and a hit ratio is 0.9? 9. A direct mapped cache has the following parameters: cache size=1k words, Block size=128 words and main memory size is 64 k words. Find the number of bits in TAG, WORD and BLOCK in main memory address? 10. Design a combinational circuit using PLA. The circuit accepts 3bit number and generates an output binary number equal to square of input number? Prepared By: Mr. C Srihari, Assistant Professor, Department of ECE. Mr. Mohd Khadir, Assistant Professor, Department of ECE. Mrs. G Shruthi, Assistant Professor, Department of ECE. Mrs. C DeviSupraja Assistant Professor, Department of ECE. HOD, CSE 12 P a g e
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad  500043 Course Name : DIGITAL LOGIC DESISN Course Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : 2018 2019
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 20152016 (ODD
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY & COMPUTER SCIENCE AND ENGINEERING QUESTION BANK II SEMESTER CS6201 DIGITAL PRINCIPLE AND SYSTEM DESIGN
More informationR10. II B. Tech I Semester, Supplementary Examinations, May
SET  1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) 48 and +31
More informationSUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3
UNIT  I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented
More informationBHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS
BHARATHIDASAN ENGINEERING COLLEGE Degree / Branch : B.E./ECE Year / Sem : II/ III Sub.Code / Name : EC6302/DIGITAL ELECTRONICS FREQUENTLY ASKED QUESTIONS UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES
More informationVALLIAMMAI ENGINEERING COLLEGE
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur 603 203 DEPARTMENT OF INFORMATION TECHNOLOGY QUESTION BANK Academic Year 2018 19 III SEMESTER CS8351DIGITAL PRINCIPLES AND SYSTEM DESIGN Regulation
More informationInjntu.com Injntu.com Injntu.com R16
1. a) What are the three methods of obtaining the 2 s complement of a given binary (3M) number? b) What do you mean by Kmap? Name it advantages and disadvantages. (3M) c) Distinguish between a halfadder
More informationDHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY
DHANALAKSHMI SRINIVASAN COLLEGE OF ENGINEERING AND TECHNOLOGY Dept/Sem: II CSE/03 DEPARTMENT OF ECE CS8351 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT I BOOLEAN ALGEBRA AND LOGIC GATES PART A 1. How many
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is  Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationSIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road QUESTION BANK (DESCRIPTIVE)
SIDDHARTH GROUP OF INSTITUTIONS :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : STLD(16EC402) Year & Sem: IIB.Tech & ISem Course & Branch: B.Tech
More informationCOLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS UNIT I
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK SUBJECT CODE & NAME: EC 1312 DIGITAL LOGIC CIRCUITS YEAR / SEM: III / V UNIT I NUMBER SYSTEM & BOOLEAN ALGEBRA
More informationHANSABA COLLEGE OF ENGINEERING & TECHNOLOGY (098) SUBJECT: DIGITAL ELECTRONICS ( ) Assignment
Assignment 1. What is multiplexer? With logic circuit and function table explain the working of 4 to 1 line multiplexer. 2. Implement following Boolean function using 8: 1 multiplexer. F(A,B,C,D) = (2,3,5,7,8,9,12,13,14,15)
More informationENDTERM EXAMINATION
(Please Write your Exam Roll No. immediately) ENDTERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA103 Subject: Digital Electronics Time: 3 Hours Maximum
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012DIGITAL
More informationPART B. 3. Minimize the following function using Kmap and also verify through tabulation method. F (A, B, C, D) = +d (0, 3, 6, 10).
II B. Tech II Semester Regular Examinations, May/June 2015 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, ECE, ECC, EIE.) Time: 3 hours Max. Marks: 70 Note: 1. Question Paper consists of two parts (PartA
More informationSHRI ANGALAMMAN COLLEGE OF ENGINEERING. (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI
SHRI ANGALAMMAN COLLEGE OF ENGINEERING AND TECHNOLOGY (An ISO 9001:2008 Certified Institution) SIRUGANOOR, TIRUCHIRAPPALLI 621 105 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC1201 DIGITAL
More informationII/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Answer ONE question from each unit.
Hall Ticket Number: 14CS IT303 November, 2017 Third Semester Time: Three Hours Answer Question No.1 compulsorily. II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Digital Logic
More informationPrinciples of Digital Techniques PDT (17320) Assignment No State advantages of digital system over analog system.
Assignment No. 1 1. State advantages of digital system over analog system. 2. Convert following numbers a. (138.56) 10 = (?) 2 = (?) 8 = (?) 16 b. (1110011.011) 2 = (?) 10 = (?) 8 = (?) 16 c. (3004.06)
More informationNADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni
NADAR SARASWATHI COLLEGE OF ENGINEERING AND TECHNOLOGY Vadapudupatti, Theni625531 Question Bank for the Units I to V SEMESTER BRANCH SUB CODE 3rd Semester B.E. / B.Tech. Electrical and Electronics Engineering
More informationR07
www..com www..com SET  1 II B. Tech I Semester Supplementary Examinations May 2013 SWITCHING THEORY AND LOGIC DESIGN (Com. to EEE, EIE, BME, ECC) Time: 3 hours Max. Marks: 80 Answer any FIVE Questions
More informationR07. Code No: V0423. II B. Tech II Semester, Supplementary Examinations, April
SET  1 II B. Tech II Semester, Supplementary Examinations, April  2012 SWITCHING THEORY AND LOGIC DESIGN (Electronics and Communications Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions
More information10EC33: DIGITAL ELECTRONICS QUESTION BANK
10EC33: DIGITAL ELECTRONICS Faculty: Dr.Bajarangbali E Examination QuestionS QUESTION BANK 1. Discuss canonical & standard forms of Boolean functions with an example. 2. Convert the following Boolean function
More informationR a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method
SET  1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove demorgan laws c) Implement two input EXOR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What
More informationCode No: 07A3EC03 Set No. 1
Code No: 07A3EC03 Set No. 1 II B.Tech I Semester Regular Examinations, November 2008 SWITCHING THEORY AND LOGIC DESIGN ( Common to Electrical & Electronic Engineering, Electronics & Instrumentation Engineering,
More informationScheme G. Sample Test PaperI
Sample Test PaperI Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN
SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.201718 INSTRUCTOR: Sri A.M.K.KANNA
More informationDigital logic fundamentals. Question Bank. Unit I
Digital logic fundamentals Question Bank Subject Name : Digital Logic Fundamentals Subject code: CA102T Staff Name: R.Roseline Unit I 1. What is Number system? 2. Define binary logic. 3. Show how negative
More informationUNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS PARTA (2 MARKS)
SUBJECT NAME: DIGITAL LOGIC CIRCUITS YEAR / SEM : II / III DEPARTMENT : EEE UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. What is variable mapping? 2. Name the two canonical forms for Boolean algebra.
More informationDE Solution Set QP Code : 00904
DE Solution Set QP Code : 00904 1. Attempt any three of the following: 15 a. Define digital signal. (1M) With respect to digital signal explain the terms digits and bits.(2m) Also discuss active high and
More information(ii) Simplify and implement the following SOP function using NOR gates:
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING QUESTION BANK NAME OF THE SUBJECT: EE 2255 DIGITAL LOGIC CIRCUITS YEAR / SEM: II / IV UNIT I BOOLEAN ALGEBRA AND COMBINATIONAL
More informationKING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:0011:50AM Class
More informationSwitching Theory & Logic Design/Digital Logic Design Question Bank
Switching Theory & Logic Design/Digital Logic Design Question Bank UNIT I NUMBER SYSTEMS AND CODES 1. A 12bit Hamming code word containing 8bits of data and 4 parity bits is read from memory. What was
More informationCS6201DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PARTB UNITI BOOLEAN ALGEBRA AND LOGIC GATES.
CS6201DIGITAL PRINCIPLE AND SYSTEM DESIGN I YEAR/II SEM PARTB UNITI BOOLEAN ALGEBRA AND LOGIC GATES. 1) Simplify the boolean function using tabulation method. F = (0, 1, 2, 8, 10, 11, 14, 15) List all
More informationCONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)
CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...
More informationCOPYRIGHTED MATERIAL INDEX
INDEX Absorption law, 31, 38 Acyclic graph, 35 tree, 36 Addition operators, in VHDL (VHSIC hardware description language), 192 Algebraic division, 105 AND gate, 48 49 Antisymmetric, 34 Applicable input
More informationUPY14602DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan
UPY14602DIGITAL ELECTRONICS AND MICROPROCESSORS Lesson Plan UNIT I  NUMBER SYSTEMS AND LOGIC GATES Introduction to decimal Binary Octal Hexadecimal number systemsinter conversionsbcd code Excess
More informationHours / 100 Marks Seat No.
17333 13141 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Illustrate your answers with neat sketches wherever necessary. (4)
More informationHours / 100 Marks Seat No.
17320 21718 3 Hours / 100 Seat No. Instructions (1) All Questions are Compulsory. (2) Answer each next main Question on a new page. (3) Figures to the right indicate full marks. (4) Assume suitable data,
More informationAPPENDIX A SHORT QUESTIONS AND ANSWERS
APPENDIX A SHORT QUESTIONS AND ANSWERS Unit I Boolean Algebra and Logic Gates Part  A 1. Define binary logic? Binary logic consists of binary variables and logical operations. The variables are designated
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationMGUBCA205 Second Sem Core VI Fundamentals of Digital Systems MCQ s. 2. Why the decimal number system is also called as positional number system?
MGUBCA205 Second Sem Core VI Fundamentals of Digital Systems MCQ s Unit1 Number Systems 1. What does a decimal number represents? A. Quality B. Quantity C. Position D. None of the above 2. Why the
More informationDIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER.
DIRECTORATE OF TECHNICAL EDUCATION DIPLOMA IN ELECTRICAL AND ELECTRONICS ENGINEERING II YEAR M SCHEME IV SEMESTER 2015 2016 onwards DIGITAL ELECTRONICS CURRICULUM DEVELOPMENT CENTRE Curriculum Development
More informationDIGITAL ELECTRONICS. Vayu Education of India
DIGITAL ELECTRONICS ARUN RANA Assistant Professor Department of Electronics & Communication Engineering Doon Valley Institute of Engineering & Technology Karnal, Haryana (An ISO 9001:2008 ) Vayu Education
More informationLogic design Ibn Al Haitham collage /Computer science Eng. Sameer
DEMORGAN'S THEOREMS One of DeMorgan's theorems stated as follows: The complement of a product of variables is equal to the sum of the complements of the variables. DeMorgan's second theorem is stated as
More informationPhiladelphia University Student Name: Student Number:
Philadelphia University Student Name: Student Number: Faculty of Engineering Serial Number: Final Exam, First Semester: 2018/2019 Dept. of Computer Engineering Course Title: Logic Circuits Date: 03/01/2019
More informationDigital Design Using Digilent FPGA Boards  Verilog / ActiveHDL Edition
Digital Design Using Digilent FPGA Boards  Verilog / ActiveHDL Edition Table of Contents 1. Introduction to Digital Logic 1 1.1 Background 1 1.2 Digital Logic 5 1.3 Verilog 8 2. Basic Logic Gates 9
More informationR.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai
L T P C R.M.D. ENGINEERING COLLEGE R.S.M. Nagar, Kavaraipettai 601206 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC8392 UNIT  I 3 0 0 3 OBJECTIVES: To present the Digital fundamentals, Boolean
More information3. The high voltage level of a digital signal in positive logic is : a) 1 b) 0 c) either 1 or 0
1. The number of level in a digital signal is: a) one b) two c) four d) ten 2. A pure sine wave is : a) a digital signal b) analog signal c) can be digital or analog signal d) neither digital nor analog
More informationCourse Batch Semester Subject Code Subject Name. B.EMarine Engineering B.E ME16 III UBEE307 Integrated Circuits
Course Batch Semester Subject Code Subject Name B.EMarine Engineering B.E ME16 III UBEE307 Integrated Circuits PartA 1 Define DeMorgan's theorem. 2 Convert the following hexadecimal number to decimal
More informationCS/IT DIGITAL LOGIC DESIGN
CS/IT 214 (CR) Total No. of Questions :09] [Total No. of Pages : 02 II/IV B.Tech. DEGREE EXAMINATIONS, DECEMBER 2016 First Semester CS/IT DIGITAL LOGIC DESIGN Time: Three Hours 1. a) FlipFlop Answer
More informationii) Do the following conversions: output is. (a) (101.10) 10 = (?) 2 i) Define XNOR gate. (b) (10101) 2 = (?) Gray (2) /030832/31034
No. of Printed Pages : 4 Roll No.... rd 3 Sem. / ECE Subject : Digital Electronics  I SECTIONA Note: Very Short Answer type questions. Attempt any 15 parts. (15x2=30) Q.1 a) Define analog signal. b)
More informationDIGITAL ELECTRONICS. P41l 3 HOURS
UNIVERSITY OF SWAZILAND FACUL TY OF SCIENCE AND ENGINEERING DEPARTMENT OF PHYSICS MAIN EXAMINATION 2015/16 TITLE OF PAPER: COURSE NUMBER: TIME ALLOWED: INSTRUCTIONS: DIGITAL ELECTRONICS P41l 3 HOURS ANSWER
More information1. Draw general diagram of computer showing different logical components (3)
Tutorial 1 1. Draw general diagram of computer showing different logical components (3) 2. List at least three input devices (1.5) 3. List any three output devices (1.5) 4. Fill the blank cells of the
More information2. (a) Compare the characteristics of a floppy disk and a hard disk. (b) Discuss in detail memory interleaving. [8+7]
Code No: A109211202 R09 Set No. 2 1. (a) Explain the purpose of the following registers: i. IR ii. PC iii. MDR iv. MAR. (b) Explain with an example the steps in subtraction of two ndigit unsigned numbers.
More informationQuestion Total Possible Test Score Total 100
Computer Engineering 2210 Final Name 11 problems, 100 points. Closed books, closed notes, no calculators. You would be wise to read all problems before beginning, note point values and difficulty of problems,
More informationINSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad ELECTRONICS AND COMMUNICATIONS ENGINEERING
INSTITUTE OF AERONAUTICAL ENGINEERING Dundigal, Hyderabad  00 0 ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK Course Name : DIGITAL DESIGN USING VERILOG HDL Course Code : A00 Class : II  B.
More informationGATE CSE. GATE CSE Book. November 2016 GATE CSE
GATE CSE GATE CSE Book November 2016 GATE CSE Preface This book is made thanks to the effort of GATE CSE members and Praneeth who made most of the latex notes for GATE CSE. Remaining work of completing
More informationComputer Logical Organization Tutorial
Computer Logical Organization Tutorial COMPUTER LOGICAL ORGANIZATION TUTORIAL Simply Easy Learning by tutorialspoint.com tutorialspoint.com i ABOUT THE TUTORIAL Computer Logical Organization Tutorial Computer
More informationMLR Institute of Technology
MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad 500 043 Course Name Course Code Class Branch ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK : DIGITAL DESIGN
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationSWITCHING THEORY AND LOGIC CIRCUITS
SWITCHING THEORY AND LOGIC CIRCUITS COURSE OBJECTIVES. To understand the concepts and techniques associated with the number systems and codes 2. To understand the simplification methods (Boolean algebra
More informationMULTIMEDIA COLLEGE JALAN GURNEY KIRI KUALA LUMPUR
STUDENT IDENTIFICATION NO MULTIMEDIA COLLEGE JALAN GURNEY KIRI 54100 KUALA LUMPUR SECOND SEMESTER FINAL EXAMINATION, 2013/2014 SESSION ITC2223 COMPUTER ORGANIZATION & ARCHITECTURE DSEWEF 1/13 18 FEBRUARY
More informationUNIT V COMBINATIONAL LOGIC DESIGN
UNIT V COMBINATIONAL LOGIC DESIGN NOTE: This is UNITV in JNTUK and UNITIII and HALF PART OF UNITIV in JNTUA SYLLABUS (JNTUK)UNITV: Combinational Logic Design: Adders & Subtractors, Ripple Adder, Look
More informationSpecifying logic functions
CSE4: Components and Design Techniques for Digital Systems Specifying logic functions Instructor: Mohsen Imani Slides from: Prof.Tajana Simunic and Dr.Pietro Mercati We have seen various concepts: Last
More informationNH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 1 BOOLEAN ALGEBRA AND LOGIC GATES Review of binary
More informationFinal Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)
Your Name: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS
More informationECE 331: N0. Professor Andrew Mason Michigan State University. Opening Remarks
ECE 331: N0 ECE230 Review Professor Andrew Mason Michigan State University Spring 2013 1.1 Announcements Opening Remarks HW1 due next Mon Labs begin in week 4 No class nextnext Mon MLK Day ECE230 Review
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed ElSaied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationNODIA AND COMPANY. GATE SOLVED PAPER Computer Science Engineering Digital Logic. Copyright By NODIA & COMPANY
No part of this publication may be reproduced or distributed in any form or any means, electronic, mechanical, photocopying, or otherwise without the prior permission of the author. GATE SOLVED PAPER Computer
More informationThis tutorial gives a complete understanding on Computer Logical Organization starting from basic computer overview till its advanced architecture.
About the Tutorial Computer Logical Organization refers to the level of abstraction above the digital logic level, but below the operating system level. At this level, the major components are functional
More informationCHAPTER  2 : DESIGN OF ARITHMETIC CIRCUITS
Contents i SYLLABUS osmania university UNIT  I CHAPTER  1 : BASIC VERILOG HDL Introduction to HDLs, Overview of Digital Design With Verilog HDL, Basic Concepts, Data Types, System Tasks and Compiler
More informationChap.3 3. Chap reduces the complexity required to represent the schematic diagram of a circuit Library
3.1 Combinational Circuits 2 Chap 3. logic circuits for digital systems: combinational vs sequential Combinational Logic Design Combinational Circuit (Chap 3) outputs are determined by the present applied
More informationUnit 6 1.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2.Programmable Logic
EE 200: Digital Logic Circuit Design Dr Radwan E AbdelAal, COE Unit 6.Random Access Memory (RAM) Chapter 3 Combinational Logic Design 2. Logic Logic and Computer Design Fundamentals Part Implementation
More informationGet Free notes at ModuleI One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationSECTIONA
M.Sc(CS) ( First Semester) Examination,2013 Digital Electronics Paper: Fifth  SECTIONA I) An electronics circuit/ device
More informationDIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES
DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the
More informationDigital Logic Design Exercises. Assignment 1
Assignment 1 For Exercises 15, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationBHARATHIDASAN ENGINEERING COLLEGE
BHARATHIDASAN ENGINEERING COLLEGE CS6201 DIGITAL PRINCIPLES AND SYSTEM DESIGN (FOR COMMON TO 2 SEM CSE & IT) Lecturer notes Prepared by L.Gopinath M.tech Assistant professor UNIT 1 BOOLEAN ALGEBRS AND
More informationCOMBINATIONAL LOGIC CIRCUITS
COMBINATIONAL LOGIC CIRCUITS 4.1 INTRODUCTION The digital system consists of two types of circuits, namely: (i) Combinational circuits and (ii) Sequential circuits A combinational circuit consists of logic
More informationII/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION. Discrete Mathematical Structures. Answer ONE question from each unit.
14CS IT302 November,2016 II/IV B.Tech (Regular/Supplementary) DEGREE EXAMINATION Common for CSE & IT Discrete Mathematical Structures (4X12=48 Marks) 1. Answer all questions (1X12=12 Marks) a (Pv~P) is
More informationUNIT  V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
UNIT  V MEMORY P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents Memory: Introduction, RandomAccess memory, Memory decoding, ROM, Programmable Logic Array, Programmable Array Logic, Sequential programmable
More informationCombinational Circuits
Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables
More informationQUESTION BANK (DESCRIPTIVE) UNIT I Binary Systems, Boolean Alegebra & Logic Gates. 1. What are the characteristics of Digital Systems.
SIDDHARTH INSTITUTE OF ENGINEERING & TECHNOLOGY :: PUTTUR Siddharth Nagar, Narayanavanam Road 517583 QUESTION BANK (DESCRIPTIVE) Subject with Code : Digital Logic Design(18CS502 ) Year & Sem: IB.Tech
More informationTEACHING & EXAMINATION SCHEME For the Examination COMPUTER SCIENCE. B.Sc. PartI
TEACHING & EXAMINATION SCHEME For the Examination 2015 COMPUTER SCIENCE THEORY B.Sc. PartI CS.101 Paper I Computer Oriented Numerical Methods and FORTRAN Pd/W Exam. Max. (45mts.) Hours Marks 150 2 3
More informationD I G I T A L C I R C U I T S E E
D I G I T A L C I R C U I T S E E Digital Circuits Basic Scope and Introduction This book covers theory solved examples and previous year gate question for following topics: Number system, Boolean algebra,
More informationBOOLEAN ALGEBRA. Logic circuit: 1. From logic circuit to Boolean expression. Derive the Boolean expression for the following circuits.
COURSE / CODE DIGITAL SYSTEMS FUNDAMENTAL (ECE 421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE 422) BOOLEAN ALGEBRA Boolean Logic Boolean logic is a complete system for logical operations. It is used in countless
More informationChapter 3. GateLevel Minimization. Outlines
Chapter 3 GateLevel Minimization Introduction The Map Method FourVariable Map FiveVariable Map Outlines Product of Sums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel
More informationModel EXAM Question Bank
VELAMMAL COLLEGE OF ENGINEERING AND TECHNOLOGY, MADURAI Department of Information Technology Model Exam 1 1. List the main difference between PLA and PAL. PLA: Both AND and OR arrays are programmable
More informationDLD VIDYA SAGAR P. potharajuvidyasagar.wordpress.com. Vignana Bharathi Institute of Technology UNIT 3 DLD P VIDYA SAGAR
DLD UNIT III Combinational Circuits (CC), Analysis procedure, Design Procedure, Combinational circuit for different code converters and other problems, Binary Adder Subtractor, Decimal Adder, Binary Multiplier,
More informationSt.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad
St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad500 014 Subject: Digital Design Using Verilog Hdl Class : ECEII Group A (Short Answer Questions) UNITI 1 Define verilog HDL? 2 List levels of
More informationPresentation 4: Programmable Combinational Devices
Presentation 4: Programmable Combinational Devices Asst. Prof Dr. Ahmet ÖZKURT DEUEEE Based on the Presentation by Prof. Kim, Young Ho Dept. of Information Computer Engineering Email : yhkim@hyowon.cs.pusan.ac.kr
More informationPROGRAMMABLE LOGIC DEVICES
PROGRAMMABLE LOGIC DEVICES Programmable logic devices (PLDs) are used for designing logic circuits. PLDs can be configured by the user to perform specific functions. The different types of PLDs available
More informationWritten exam for IE1204/5 Digital Design Thursday 29/
Written exam for IE1204/5 Digital Design Thursday 29/10 2015 9.0013.00 General Information Examiner: Ingo Sander. Teacher: William Sandqvist phone 087904487 Exam text does not have to be returned when
More informationSRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR
SRM ARTS AND SCIENCE COLLEGE SRM NAGAR, KATTANKULATHUR 603203 DEPARTMENT OF COMPUTER SCIENCE & APPLICATIONS LESSON PLAN (207208) Course / Branch : B.Sc CS Total Hours : 50 Subject Name : Digital Electronics
More information