INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad


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1 INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad COMPUTER SCIENCE AND ENGINEERING TUTORIAL QUESTION BANK Name : DIGITAL LOGIC DESISN Code : AEC020 Class : B Tech III Semester Branch : CSE Academic Year : Coordinator : Mr. C Srihari,Assistant Professor, Department Of ECE Faculty : Mr. Mohd. Khadir, Assistant Professor, Department Of ECE Mrs. J Swetha, Assistant Professor, Department Of ECE Mrs. C DeviSupraja, Assistant Professor, Department Of ECE COURSE OBJECTIVES: The course should enable the students to: S. No Description I Analyze and explore the uses of logic functions for building digital logic circuits II Explore the combinational logic circuits. III Examine the operation of sequential (synchronous and asynchronous) circuits IV Know the concepts of basic memory system.. COURSE LEARNING OUTCOMES: Students, who complete the course, will have demonstrated the ability to do the following: CAEC CAEC CAEC CAEC CAEC CAEC CAEC CAEC CAEC number systems, binary addition and subtraction, 2 s complement representation and operations with this representation and understand the different binary codes. Explain switching algebra theorems and apply them for logic functions. Identify the importance of SOP and POS canonical forms in the minimization or other optimization of Boolean formulas in general and digital circuits. Discuss about digital logic gates and their properties. Evaluate the functions using various types of minimizing algorithms like Boolean algebra. Evaluate the functions using various types of minimizing algorithms like Karnaugh map method. Design and implementation of Gate level minimization using KMaps. Analyze the design procedures of Combinational logic circuits. bistable elements and different types of latches and flipflops. Analyze the design procedures of small sequential circuits. the concept of Shift Registers. Analyze the design procedures of Synchronous Counters.(Johnson Counters, Ring Counters). 1 P a g e
2 3 4 5 Analyze the design procedures of Asynchronous Counters(Ripple Carry Counter). and analyze the design of a Programmable logic devices (PLA s,pal s). Design various arithmetic, logic, and memory components, e.g., ALUs, Shifters, Decoders, Multiplexers, RAMs, and ROMs; TUTORIAL QUESTION BANK S. No Question UNITI NUMBERS SYSTEMS AND CODES PARTA(Short Answer Questions) 1. Write short notes on binary number systems? 2. Discuss 1 s and 2 s complement methods of subtraction? 3. Discuss octal number system? 4. Discuss about BCD code? 5. Solve If (2.3) 4 +(1.2) 4 =(y) 4 then find y? 6. Write a short note on four bit BCD codes? 7. Explain the specialty of unit distance code? State where they are used? 8. Write a short note on error correcting codes? 9. Solve (127) 8 to all number systems? 10. Discuss what a logic design is and what do u mean by positive logic system? 11. Convert (4085) 8 into base5? 12. Convert (4085) 8 into base3? 13. Write the steps involved in unsigned binary subtraction using complements with examples? 14. Explain the addition of two signed binary number along with examples? 15. Differentiate between binary code and BCD code? 16. Solve subtraction between 95 using xs3? 17. Convert (4085)9 into base4? 18. Convert to octal equivalent and hexadecimal equivalent 19. Convert the octal numbers into binary,decimal and Hexadecimal numbers (45.5)octal,(32.2)octal 20. Convert the following Hexadecimal numbers to their Dec equivalent EAF1 PARTB(Long Answer Questions) 1. (a) Solve the subtraction with the following unsigned binary numbers by taking the 2's complement of the subtrahend: i ii (b) Construct a table for weighted code and write 2421 using this code.write short notes on binary number systems. 2. (a) Solve arithmetic operation indicated below. Follow signed bit notation: i ii (b) 2 P a g e
3 Explain the importance of gray code? 3. Solve ( ) 10 using 10's complement? 4. Explain Self complemented codes? 5. Solve (a) Divide by (b) Given that (292)10 =(1204)b determine `b' 6. Differentiate between BCD code and 2421 code and XS3? 7. Solve (a) Find ( ) using 9's complement. (b) Show the weights of three different 4 bit self complementing codes whose only negative weight is  4 and write down number system from 0 to Solve ( ) 10 using 9's complement with XS3? 9. State using XS3? 10. Solve the following numbers, (a) Add by (b) Given that (292) 10 =(1204) b determine `b' 11. Solve (a) What is the gray code equivalent of the Hex Number 3A7 (b) Find 9's complement (25.639) Apply the representation of +65 and 65 in sign magnitude, Sign 1 s complement and sign 2 s complement representation? 13. State different ways for representing the signed binary numbers? 14. Solve addition and subtraction of (456) and (341) using BCD and XS3? 15. Define weighted codes and non weighted codes with examples? 16. Explain what do you mean by error detecting and correcting codes? 17. Illustrate the rules for XS3 addition and subtraction? 18. Explain error occurred in the data transmission can be detected using parity bit? 19. Solve addition between 95 and 62 using BCD and XS3 Method? 20. Solve subtraction 67 and 73 using BCD and Xs3 Method? PARTC(Problem Solving Critical Thinking Questions) 1. Solve Subtraction and Addition 617 and 732 using BCD and Xs3 Method? 2. Convert the octal numbers into binary, decimal, BCD and Hexadecimal numbers (36.6) 8,(45.5) 8,(26.3) 8,(48) Solve Subtraction and Addition 4327 and 1562 using BCD and Xs3 Method? C 4. Find transmitted 11 bits for when hamming code is used? 5. Explain about Codes? 6. write the octal representation of the following fractional numbers:(0.5)d,( 1.5)d, (2.333)d,( 3.875)d, (13.125)d, (14.666)d. 7. Find the illegal representation in the following: (120A)d, 3 P a g e
4 ( )BCD, (0208)octal, ( )b, (GC0A)h. 8. Convert the binary number to hexadecimal number: i , ii Convert the hexadecimal number to binary number: 0x5A9F, 42D by two examples that two s compliment of a number taken twice returns the original number? UNITII BOOLEAN ALGEBRA AND GATE LEVEL MINIMIZATION PARTA(Short Answer Questions) 1. Define Kmap? Name its advantages and disadvantages? CAEC Define Implicant, Prime Implicant and Essential Prime CAEC020.2 Implicant? 3. Define Consensus Theorem? CAEC Describe types of minimization techniques? CAEC Summarize the Boolean function x yz + x yz + xy z + xy z CAEC020.2 using Kmap? 6. Explain three variable kmap with example? CAEC Solve AB 1 +BC+CA=AB+BC CAEC Design the two graphic symbols for NAND gate? CAEC Design the two graphic symbols for NOR gate? CAEC Summarize the Boolean function x yz + x yz + xy z + xy z CAEC020.6 without using K map? 11. Explain the properties of EXOR gate? CAEC Solve the function of fig with ANDOR INVRET implementation CAEC Solve the following Boolean function using Kmap CAEC Solve the following using NAND gates? a) (A+B)(C+D) b) A.B+CD(AB I +CD) CAEC Sketch the following equation using kmap and realize it using CAEC020.6 NAND gate? Y= m(4,5,8,9,11,12,13,15) 16 Solve Y=AB I +CD+(A I B+C I D I ) using NAND gate? CAEC State that ANDOR network is equivalent to NANDNAND CAEC020.2 network? 18 Show both NAND and NOR gates are called Universal gates? CAEC P a g e
5 19 Sketch the following logic function using kmap and implement it using logic gates? Y(A,B,C,D)= m(0,1,2,3,4,7,8,9,10,11,12,14) CAEC Summarize the rules and limitations of Kmap simplification? CAEC Analyze the steps for simplification of POS expression? CAEC020.6 PARTB(Long Answer Questions) 1. A combinational circuit has 4 inputs(a,b,c,d) and three outputs(x,y,z)xyz represents a binary number whose value equals the number of 1's at the input (i) state the minterm CAEC020.6 expansion for the X,Y,Z (ii). state the maxterm expansion for the Y and Z 2. Minimize the following function using Kmap. F (A, B, C, D) = m (1,3,5,7,9,10,11,12,15) CAEC Minimize the following function using Kmap f = m CAEC020.6 (1,2,3,5,12,13,15) 4. Design BCD to Gray code converter and realize using logic CAEC020.2 gates? 5. Design all logic gates using Nand? CAEC compile the following expression using Karnaugh map (B A + CAEC020.2 A B + AB ) 7. Design a circuit with three inputs(a,b,c) and two outputs(x,y) CAEC020.6 where the outputs are the binary count of the number of ON" (HIGH) inputs? 8. Implement the INVERTER gate, OR gate and AND gate using CAEC020.2 NAND gate, NOR gate? 9. Design a circuit with four inputs and one output where the CAEC020.2 output is 1 if the input is divisible by 3 or 7? 10. Implement Half adder using 4 NAND gates? CAEC Implement the Boolean function F = AB + CD + E using CAEC020.6 NAND gates only? 12. Summarize the Boolean function F(w, x, y, z) = Σ(1, 3, 7, 11, CAEC ) + Σd(0. 2, 5) 13. Implement following expression f= a+b+c in to canonical sop CAEC020.6 and convert it to pos using kmap 14. Implement following expression f= abc in to canonical pos CAEC020.6 and convert it to sop using kmap 15. Identify all the prime implicants and essential prime implicants CAEC020.6 of the following functions Using k map F = Σm (0, 1, 2, 3, 4, 10, 11, 14, 15) 16. Identify all the prime implicants and essential prime implicants of the following functions Using k map. F(A,B,C,D) = Σm(0,1,2,5,6,7,8,9,10,13,14,15). CAEC Identify all the prime implicants and essential prime implicants of the following functions Using k map. CAEC P a g e
6 F(A,B,C) = Σm(0,1,2,6,7).+ d(3,5) 18. Design alternate symbols for all the gates CAEC Design all the logic gates using NOR gate CAEC Identify all the prime implicants and essential prime implicants of the following functions Using k map. F(A,B,C,D) = πm(0,1,2,5,6,7,8,9,10,13,14,15). CAEC020.6 PARTC(Problem Solving Critical Thinking Questions) 1. Use DeMorgan theorem to simplify F=(A+B+C.D.E) 1. CAEC State that for constructing XOR from NANDs we need four CAEC020.2 NAND gates? 3. Convert A.B.C+A.D expression into standard SOP format? CAEC Convert (A+B+C).(A+D) expression into standard POS CAEC020.2 format? 5. Construct XOR and XNOR from NAND and NOR gates? CAEC Construct SOP expression and POS expression for a four input CAEC020.2 NAND gate? 7. and explain five variable kmap with an example? CAEC Find the logic function F=(AB+BC+E) 1 using ANDOR two level realization? CAEC Design a 5variable k map. F(A,B,C,D,E) = CAEC020.6 πm(0,1,2,5,6,7,8,9,10,13,14,15,17,19,20).πd(3,25,28,30,31) 10 Design a 5variable k map. F(A,B,C,D,E) = CAEC020.6 m(0,1,2,5,6,7,8,9,10,17,19,20)+ d(3,12,15,18,25,28,30,31) UNITIII DESIGN OF COMBINATIONAL CIRCUITS PARTA(Short Answer Questions CIE I) 1. Explain the design procedure for combinational circuits? 2. Apply various code conversion methods? 3. Design a 4bit binary to BCD converter? 4. Design and implement a 8421 Gray code converter? Design a combinational logic circuit with 3 input variables that 5. will produce logic 1 output when more than one input variables are logic 1? 6. Compose and explain the block diagram of 4bit parallel adder? 7. Design a logic circuit to convert BCD and gray code? 8. Design a full adder using two half adders? 9. Explain magnitude comparator? Design a 1bit comparator using logic gates? 10. Compose the circuit for 3 to 8 decoder and explain it with logic gate? PARTA(1) (Short Answer QuestionsCIE II) 1. Construct the logic circuit for full subtractor using decoder? 2. Define binary decoder? Explain the working of 2:4 binary decoder? 3. Design Full adder using a suitable Decoder? 6 P a g e
7 4. Define encoder? Design octal to binary encoder? 5. Design a 4bit priority encoder? 6. Design the block diagram of a 4:1 multiplexer using 2:1 multiplexer? 7. Define Multiplexer and demultiplexer? 8. Explain how decoder acts as a demultiplexer? 9. Differentiate multiplexer and demultiplexer? 10. Explain the working of 8:1 multiplexer? PARTB(Long Answer QuestionsCIEI) 1. Design a combinational circuit that generates logic 1 for odd inputs? 2. Design a logic circuit to convert gray code to binary code? 3. Design circuit to detect invalid BCD number and implement using NAND gate only? 4. Explain the design procedure for code converter with the help of example? 5. Construct half subtractor using NAND gates? 6. Explain the working of carry lookahead generator? 7. Explain carry propagation in parallel adder with neat diagram? 8. Explain the circuit diagram of full subtractor and full adder? 9. Construct and explain the working of decimal adder? 10. Design 2digit BCD adder with the help of binary adders? 11. Design Full Adder using NAND gates? PARTB(1)(Long Answer QuestionsCIEII) 12. State the procedure to implement Boolean function using decoder and also mention the uses of decoders? 13. Design Multiply by using binary multiplication method? 14. Design an 2bit Magnitude Comparator? 15. Summarize the following Boolean function using 8:1 mux F(A,B,C,D)=πM(0,3,5,8,9,10,12,14) 16. Design and implement a full adder circuit using a 3:8 decoder? 17. Design Full Subtractor using NAND gates? 18. Design Full Subtractor using NOR gates? 19. Design Full Adder using NOR gates? 20. Design 4 input Priority Encoder? PARTC(Problem Solving Critical Thinking Questions CIEI) 1. Design a combinational logic circuit that produces the product of 2 binary number of following function A=(A 1,A 0 )*B=(B 1, B 0 ) 2. Solve the function using multiplexer F(x,y,z)= (0,2,6,7) 3. A combinational circuit has 4 inputs(a,b,c,d) and three outputs(x,y,z)xyz represents a binary number whose value equals the number of 1's at the input: i. Find the minterm expansion for the X,Y,Z ii. Find the maxterm expansion for the Y and Z 4. Design a combinational logic circuit with 4 inputs A, B, C, D. 7 P a g e
8 The output Y goes High if and only if A and C inputs go High. i. Draw the truth table. ii. Minimize the Boolean function using Kmap. iii. Draw the circuit diagram? 5. Design a logic circuit to convert excess3 code to BCD code? 6. Design a logic circuit to convert BCD code to XS3 code? PARTC(1)( Problem Solving Critical Thinking Questions CIEII) 7. Design a multiple circuit to multiply the following binary number A=A 0 A 1 A 2 A 3 and B=B 0 B 1 B 2 B 3 using required number of binary parallel adders? 8. Solve the following Boolean functions using decoder and OR gates: F 1 (A,B,C,D)= (2,4,7,9) F 2 (A,B,C,D)= (10,13,14,15) 9. Solve the following Boolean functions using decoder and OR gates: F 1 (A,B,C,D)= (3,5,6,8) F 2 (A,B,C,D)= (11,12,13,15) 10. Solve the following Boolean function using 8:1 mux F(A,B,C,D)= m(1,3,5,7,8,9,0,2,,13) 11. Solve the following Boolean function using 8:1 mux F(A,B,C,D)= m(1,3,5,7,8,9,0,2,10,12,13) UNITIV DESIGN OF SEQUENTIAL CIRCUITS PARTA(Short Answer Questions) 1. Differentiate combinational and sequential logic circuits? CAEC Explain basic difference between a shift register and counter? CAEC Illustrate applications of shift registers? 2 4. Define bidirectional shift register? 2 5. Differentiate Flipflop and latch? 2 6. Define Counter? 2 7. Classify the basic types of counters? 2 8. Differentiate the advantages and disadvantages of ripple 2 counters? 9. Describe the applications of Counters? Design Dlatch using NAND? Design and explain gated latch logic diagram? Define race around condition? How it can be avoided? 13. Convert a JK Flip Flop to i) SR ii) T iii) D Convert a SR FlipFlop to i) JK ii) D iii) T Explain what is a synchronous latch? Construct a latch using universal gates? Explain what do you mean a stable state? Define a FlipFlop? Define applications of FlipFlops? 2 8 P a g e
9 20. Explain what is meant by clocked flipflop? 2 PARTB(Long Answer Questions) 1. Explain the design of Synchronous Sequential circuit with an CAEC020.9 example? 2. Write short notes on shift register? Mention its application CAEC020.9 along with the Serial Transfer in 4bit shift Registers? 3. Explain about Binary Ripple Counter? What is MOD counter? 2 4. Define BCD Counter and Draw its State table for BCD 2 Counter? 5. Explain the state reduction and state assignment in designing 2 sequential circuit. Consider one example in the above process? 6. Design a sequential circuit with two D flipflops A and B. and 2 one input x. When, x=0, the state of the circuit remains the same. When, x=1, the circuit goes through the state transition from 00 to 11 to 11 to 10 back to 00.and repeats? 7. Design a Modulo12 up Synchronous counter Using TFlip Flops and draw the Circuit diagram? 2 8. Explain the Ripple counter design. Also the decade counters 2 design? 9. Design a 3 bit ring counter? Discuss how ring counters differ 2 from twisted ring counter? 10. Design a Johnson counter? Design Johnson counters and state its advantages and 2 disadvantages? 12. Explain with the help of a block diagram, the basic components 2 of a Sequential Circuit? 13. Explain about RS and JK flipflops? Define T Flipflop with the help of a logic diagram and 2 characteristic table? 15. Define Latch. Explain about Different types of Latches in 2 detail? 16. Define JK Flipflop with the help of a logic diagram and 2 characteristic table? 17. List the characteristic equations for all FlipFlops? Construct the transition table for the following flipflops 2 i) SR FF ii) ii) D FF 19. Describe the steps involved in design of asynchronous 2 sequential circuit in detail with an example? 20. Differentiate Synchronous and Asynchronous counters? 2 PARTC(Problem Solving Critical Thinking Questions) 1. Explain the JK and Master slave Flipflop? Give its timing waveform? 2 9 P a g e
10 2. A sequential circuit has 3 flipflops, A,B and C and one input,x it is described by the following flip flop input functions? D A =(BC I +B I C)x+(BC+B I C I )x I D B =A D C =B i)derive the state table for circuit ii)draw two state diagrams: One for x=0 and for x=1 3. Design and implement 4bit binary counter (using D flip flops) which counts all possible odd numbers only? 4. Design Moore Machine and draw state diagram and assignment? 5. Design Mealy Machine and draw state diagram and assignment? 6. Design a MOD5 synchronous counter using flip flops and implement it? Also draw the timing diagram? 7. Design a Ring counter using JK flipflop? 2 8. Design a Twisted Ring counter using JK flipflop? 2 9. Design MOD5 up and Down counter? 3 UNITV MEMORY PARTA(Short Answer Questions) 1. Explain what is PROM? 4 2. Explain in detail about RAM and types of RAM? 4 3. Illustrate the features of a ROM cell? 4 4. Explain in detail about ROM and types of ROM? 4 5. Explain is ROM is volatile Memory? 4 6. Describe what is meant by memory expansion? Mention its 4 limits? 7. List a note on magnetic tape? 4 8. State the advantages and disadvantages of magnetic tape and 5 magnetic disk? 9. Differentiate static and dynamic RAM? Explain what is the use of cache memory? Design and explain the following mapping techniques of cache: 5 a) Direct mapping b) Associative mapping 12. Explain different replacement algorithms in detail? Explain what is EPROM? Differentiate between PROM and EPROM? Explain what is EEPROM? Explain what is PLA? Explain how is the capacity of PLA specified? Explain what is PLD? Explain PLA with the help of block diagram? Explain the advantage of PROM over PLD? 4 10 P a g e
11 PARTB(Long Answer Questions) 1. List How many address bits are needed to operate a 2 K *8 5 ROM? 2. Construct a logic diagram of memory cell? 5 3. Distinguish between SRAM and DRAM? 5 4. Explain the read and write operation a RAM can perform? 4 5. Explain the operation of DRAM 5 6. Construct the signals of a 32*8 RAM with control input. Show 4 the external connections necessary to have a 128*8 RAM using decoder and replication of this RAM? 7. To implement 2bit squaring time no of address lines and data 5 lines used in ROM? 8. To implement 2bit multiplication time no of address lines and 4 data lines used in ROM? 9. Explain two way set associative mapping and four way set 5 associative mapping techniques with an example for each? 10. Explain how a program gets executed faster using a cache 4 memory? 11. Design a BCD to Excess3 code converter and implement using 5 Suitable PLA? 12. Construct the block diagram of PLA. Which are the teams 4 programmable? How inverter is useful in PLA construction at the output? 13. Sketch the PLA program table for the four Boolean functions. 5 Minimize the number of product terms? A(x,y,z)= (0,1,3,5) B(x,y,z)= (2,6) C(x,y,z)= (1,2,3,5,7) D(x,y,z)= (0,1,6) 14. Sketch a PLA circuit to implement the logic functions 4 A I BC+AB I C+AC I and A I B I C I +BC. 15. Explain in detail various cache memory organizations? Sketch the ROM for the four Boolean functions. Minimize the 5 number of product terms? A(x,y,z)= (1,2,4,7) B(x,y,z)= (0,1,3,5,6) C(x,y,z)= (0,2,4,5,7) D(x,y,z)= (3,5,6,7) 17. Explain the techniques used to perform the write operations in 5 cache memory? 18. Explain in detail about the operation of SRAM? Differentiate PAL with PLA with examples? Memory hierarchy design is based on the principle of Locality of reference. Explain the principle? 5 11 P a g e
12 PARTC(Problem Solving Critical Thinking Questions) 1. Solve the following two Boolean functions using a PLA having 3inputs,4 product terms and 2 outputs? F 1 (A,B,C)= (0,1,2,4) F 2 (A,B,C)= (0,5,6,7) 5 2. Design 1k*8 RAM using two 1k*4 IC? 5 3. Solve 2048*8 memories using 256*8 memory chip.also show 4 the memory address associated with each memory chip? 4. Calculate the utilization factor of tape, if the gap length is 0.5 in, the storage density S=3000 bytes/in and data storage capacity is 6 k bytes? 5. A two way set associative cache memory uses block of four words. The cache accommodate a total of 2048 words from main memory. The main memory size is 128k*32 i. Find how many bits are there in tag index, block and word field of address format? ii. Findthe size of cache memory? 6. Solve the following multi boolean function using 3*4*2 PLA PLD? F 1 (a 2, a 1, a 0 )= m(0,1,3,5) F 2 (a 2, a 1, a 0 )= m(3,5,7) 7. Design and implement 3bit binary to gray code converter using PLA? 8. Calculate the average access time of memory for a computer with cache access time of 100ns,a main memory access of 1000ns and a hit ratio is 0.9? 9. A direct mapped cache has the following parameters: cache size=1k words, Block size=128 words and main memory size is 64 k words. Find the number of bits in TAG, WORD and BLOCK in main memory address? 10. Design a combinational circuit using PLA. The circuit accepts 3bit number and generates an output binary number equal to square of input number? Prepared By: Mr. C Srihari, Assistant Professor, Department of ECE. Mr. Mohd Khadir, Assistant Professor, Department of ECE. Mrs. G Shruthi, Assistant Professor, Department of ECE. Mrs. C DeviSupraja Assistant Professor, Department of ECE. HOD, CSE 12 P a g e
INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
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