Student Name: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science
|
|
- Matthew Baker
- 6 years ago
- Views:
Transcription
1 University of alifornia at erkeley ollege of Engineering epartment of Electrical Engineering and omputer Science EES 5 all 2 R. H. Katz IRST MITERM EXMINTION Tuesday, 3 October 2 INSTRUTIONS RE THEM NOW! ll work is to be done on these pages. Partial credit is given only if we can evaluate your approach: indicate your assumptions and write as neatly as possible. Points are assigned to problems based on our estimates of how long they should take point equals minute. PE YOURSEL ORINGLY: it is better to get partial credit on all of the problems than to complete a handful of them. This is a closed book examination. You will not need a calculator or other information appliance. You may use a single 8.5 by piece of paper with prepared notes. Write your name and Student I Number at the top of each examination page. Please refrain from discussing the examination after you have taken it. small number of students are taking a late examination due to special circumstances. It is a sad fact of life that cheating sometimes happens. It will not be tolerated. y signing below, you assert that all of the work included herein is your own, and that you understand the harsh penalties that will be imposed should cheating be detected a on the examination, and a letter of reprimand to your file: (Signature) (Name Please Print!) QUESTION POINTS SSIGNE POINTS OTINE TOTL 9 S 5 Midterm # Page 3 October 2; 2:-3:3 PM
2 Question. Terminology (i) Prime Implicants (5 Points): In a 3-variable K-map, show a function and its prime implicants that illustrates the fact that there is more than one equally good minimized Sum of Products realizations of the function. (a) ill in the K-map for (,,) below. (b) Identify the prime implicants by suitable circlings. (c) Select two different covers from the prime implicants, each with the same number of product terms and literals. irst minimized implementation of (,,) = Second minimized implementation of (,,) = (ii) Product of Sums versus Sums of Products (5 Points): Give a K-map and an example function whose minimized PoS form has fewer literals in it than its minimized SoP form. (a) ill in the K-map for (,,) below. (b) Indicate the minimized SoP and PoS realizations you obtain. (c) How many literals is in each realization? Minimized SoP realization of (,,) = Number of literals is: Minimized PoS realization of (,,) = Number of literals is: S 5 Midterm # Page 2 3 October 2; 2:-3:3 PM
3 Question 2. Minimization (5 Points) Given the following four four-variable functions: W(,,,) = Sm(,2,4,5,8,,2,3) X(,,,) = Sm(,2,5,7,3,5) Y(,,,) = Sm(4,5,6,8,,2,3,4) Z(,,,) = Sm(5,6,7,8,,3,4,5) Use K-maps to independently minimize the functions in Sum of Products form. W X Y Z W = X = Y = Z = The number of unique product terms is: Now resolve for W, X, Y, Z when the target of implementation is a Programmable Logic rray (PL): W = X = Y = Z = The number of unique product terms is: S 5 Midterm # Page 3 3 October 2; 2:-3:3 PM
4 Question 3. Minimization (2 Points) onsider the following function: (,,,) = Sm(,5,6,9,2,5) (a) What is the minimized Sum of Products form? How many literals does it have? = Literal ount is (b) What is the minimized Product of Sums form? How many literals does it have? (c) In addition to N, OR, omplement (NOT) functions, assume that you can also use the XOR function as a primitive gate. They cost no more to use than simple gates like N and OR. How do you obtain an implementation with a minimized literal count now? Write down your answer as a twolevel oolean expression using XOR, N, OR, NOT functions. = = Literal ount is Literal ount is Show your work below: S 5 Midterm # Page 4 3 October 2; 2:-3:3 PM
5 Question 4. ircuits with eedback (5 points) onsider the following circuit schematic and timing waveform. ssume that all gates have identical gate delays. Each time division in the waveform diagram represents a gate delay. t time T, the switch has been open long enough for the signals to have reached a steady initial state. t T, the switch closes. ill in the waveform diagram. E T T TIME What kind of periodic signal does this circuit generate? S 5 Midterm # Page 5 3 October 2; 2:-3:3 PM
6 Question 5. Multiplexer esign (5 Points) esign a subsystem using multiplexer components that can do the following function: ata Inputs:,,, ontrol Inputs: S, S Outputs: W, X, Y, Z The behavior of the system is described by the following functional truth table: Rotate Inputs Right Rotate Inputs Left rithmetic Shift Inputs Right rithmetic Shift Inputs Left raw a wiring diagram for your implementation below: S S W X Y Z S S 2 3 S S 2 3 S S 2 3 S S 2 3 S 5 Midterm # Page 6 3 October 2; 2:-3:3 PM
7 Question 6. Multiplexer Implementation (5 Points) Given the five variable function (,,,,E) = Sm(,,3,4,8,9,,,2,4,6,2,2,23,26,3), show how to implement this using a single 8: multiplexer and no other logic gates (you may assume that variables and their complements are available at no cost to your implementation). HINT: Use,, E as the multiplexer control inputs. Show the wiring below: S2 S S Show your approach below: S 5 Midterm # Page 7 3 October 2; 2:-3:3 PM
8 Question 7. esign Problem ( Points) It is well known from the X-iles that liens have two arms and three fingers on each hand. So it is not so surprising that they have a base 6 number system. esign a digital subsystem that takes as input a binary coded hexary (H) digit (i.e., through 5 is represented by the binary numbers through ) and a mode input that outputs the H digit plus when mode = and H when mode =. (a) Identify your inputs and outputs. raw a block diagram: H Increment/ ecrement y (b) State your assumptions about the behavior of the circuit. ocument your understanding of the function with a truth table: (c) Implement it in minimized Sum of Products form. raw filled in K-maps, circled implicants, and the minimized oolean equations for your outputs: S 5 Midterm # Page 8 3 October 2; 2:-3:3 PM
ENEL Digital Circuits Midterm Examination
Name: Lecture Section: L0 N. artley :-:50 L02 S. Norman, 2:-2:50 ENEL 353 - igital ircuits Midterm Examination Wednesday, October 30, 203 Instructions: Time allowed is 90 minutes. In order to minimize
More informationENEL 353: Digital Circuits Midterm Examination
NAME: SECTION: L01: Norm Bartley, ST 143 L02: Steve Norman, ST 145 When you start the test, please repeat your name and section, and add your U of C ID number at the bottom of the last page. Instructions:
More informationSection 001. Read this before starting! You may use one sheet of scrap paper that you will turn in with your test.
Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Fall Semester,
More informationCprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Minimization CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev Administrative
More informationThere are only 16 possible 2-input gates Let s examine all of them. Some we already know, others are just silly.
ll the Gates There are only 6 possible 2-input gates Let s examine all of them. Some we already know, others are just silly. Do we really need all of these gates? How many of these gates can be implemented
More informationChapter 2 Part 4 Combinational Logic Circuits
University of Wisconsin - Madison EE/omp Sci 352 Digital Systems undamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 hapter 2 Part 4 ombinational Logic ircuits Originals by: harles R. Kime and Tom Kamisnski
More informationMidterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil
Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final
More informationStudent Name: University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science
SI: University of alifornia at erkeley ollege of ngineering epartment of lectrical ngineering and omputer Science S Fall 00 MITRM XMINTION Monday, October 00 I. Stoica INSTRUTIONS R THM NOW! This examination
More informationRead this before starting!
Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Spring Semester,
More informationDr. S. Shirani COE2DI4 Midterm Test #1 Oct. 14, 2010
Dr. S. Shirani COE2DI4 Midterm Test #1 Oct. 14, 2010 Instructions: This examination paper includes 9 pages and 20 multiple-choice questions starting on page 3. You are responsible for ensuring that your
More informationCS Spring Combinational Examples - 1
S 5 - Spring 2 - ombinational Examples - ombinational Logic esign ase Studies General esign Procedure for ombinational Logic General design procedure Examples alendar subsstem to 7-segment displa controller
More informationChapter 3 working with combinational logic
hapter 3 working with combinational logic ombinational Logic opyright 24, Gaetano orriello and Randy H. Katz Working with combinational logic Simplification two-level simplification exploiting don t cares
More informationRead this before starting!
Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Spring Semester,
More information/90 TOTAL. 1(a) 8pts. fiv(a,b) is called the function.
Your Name: SID Number: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO SANTA BARBARA SANTA CRUZ Department of Electrical Engineering and Computer
More informationRead this before starting!
Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Spring Semester,
More informationFinal Examination (Open Katz, asynchronous & test notes only, Calculators OK, 3 hours)
Your Name: UNIVERSITY OF CALIFORNIA AT BERKELEY BERKELEY DAVIS IRVINE LOS ANGELES RIVERSIDE SAN DIEGO SAN FRANCISCO Department of Electrical Engineering and Computer Sciences SANTA BARBARA SANTA CRUZ CS
More informationSection 001. Read this before starting!
Points missed: Student's Name: Total score: / points East Tennessee State University Department of Computer and Information Sciences CSCI 25 (Tarnoff) Computer Organization TEST 2 for Fall Semester, 25
More information2/8/2017. SOP Form Gives Good Performance. ECE 120: Introduction to Computing. K-Maps Can Identify Single-Gate Functions
University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing Two-Level Logic SOP Form Gives Good Performance s you know, one can use a K-map
More informationChapter 3 Part 1 Combinational Logic Design
Universit of Wisconsin - Madison EE/omp Sci 352 igital Sstems undamentals Kewal K. Saluja and Yu Hen Hu Spring 22 hapter 3 Part ombinational Logic esign Originals b: harles R. Kime and Tom Kamisnski Modified
More informationFinal Exam Solution Sunday, December 15, 10:05-12:05 PM
Last (family) name: First (given) name: Student I.D. #: Circle section: Kim Hu Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 352 Digital System Fundamentals
More informationSimplification of two-level combinational logic
ombinational logic optimization! lternate representations of oolean functions " cubes " karnaugh maps! Simplification " two-level simplification " exploiting don t cares " algorithm for simplification
More information9/10/2016. ECE 120: Introduction to Computing. The Domain of a Boolean Function is a Hypercube. List All Implicants for One Variable A
University of Illinois at Urbana-Champaign Dept. of Electrical and Computer Engineering ECE 120: Introduction to Computing To Simplify, Write Function as a Sum of Prime Implicants One way to simplify a
More informationAdministrivia. CSE 370 Spring 2006 Introduction to Digital Design Lecture 9: Multilevel Logic
SE 370 Spring 2006 Introduction to igital esign Lecture 9: Multilevel Logic Last Lecture Introduction to Verilog Today Multilevel Logic Hazards dministrivia Hand in Homework #3 Homework #3 posted this
More informationRead this before starting!
Points missed: Student's Name: Total score: /1 points East Tennessee State University Department of Computer and Information Sciences CSCI 215 (Tarnoff) Computer Organization Section 1 TEST 1 for Fall
More informationChapter 3. Gate-Level Minimization. Outlines
Chapter 3 Gate-Level Minimization Introduction The Map Method Four-Variable Map Five-Variable Map Outlines Product of Sums Simplification Don t-care Conditions NAND and NOR Implementation Other Two-Level
More informationDigital Logic Design (3)
Digital Logic Design (3) ENGG1015 1 st Semester, 2010 Dr. Kenneth Wong Dr. Hayden So Department of Electrical and Electronic Engineering Last lecture ll logic functions can be represented as (1) truth
More informationCS 151 Midterm. (Last Name) (First Name)
CS 151 Midterm Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 13 pages including this cover. 2. Write down your Student-Id on the top
More informationLast Name Student Number. Last Name Student Number
University of Toronto Faculty of Applied Science and Engineering Department of Electrical and Computer Engineering Midterm Examination ECE 241F - Digital Systems Wednesday October 13, 2004, 6:00pm [5]
More informationDate Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS
Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 09 MULTIPLEXERS OBJECTIVES: To experimentally verify the proper operation of a multiplexer.
More informationChapter 2 Combinational Logic Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization Overview Part Gate Circuits and Boolean Equations Binary Logic and Gates Boolean Algebra Standard
More informationDigital Circuits ECS 371
Digital Circuits ECS 37 Dr. Prapun Suksompong prapun@siit.tu.ac.th Lecture 7 Office Hours: KD 36-7 Monday 9:-:3, :3-3:3 Tuesday :3-:3 Announcement HW2 posted on the course web site Chapter 4: Write down
More informationRead this before starting!
Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Spring Semester,
More informationECE/Comp. Sci. 352 { Digital System Fundamentals
epartment of Electrical and Computer Engineering University of Wisconsin - Madison Final uggested olution ECE/Comp. ci. 352 { igital ystem Fundamentals. (25 points) hort Questions (a)(5points) Convert
More informationECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two 26 February 2014
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
More informationRead this before starting!
Points missed: Student's Name: Total score: /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) Computer Organization TEST 1 for Fall Semester,
More informationSolutions for 3824 Midterm Exam 3/4/ Truth table. A B C Z
Solutions for 3824 Midterm Exam 3/4/04 1. Truth table. ----------- 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 2. When analyzing a circuit built with NN-gates, the easiest approach
More informationSimplification of Boolean Functions
COM111 Introduction to Computer Engineering (Fall 2006-2007) NOTES 5 -- page 1 of 5 Introduction Simplification of Boolean Functions You already know one method for simplifying Boolean expressions: Boolean
More informationR10. II B. Tech I Semester, Supplementary Examinations, May
SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31
More informationCMPE223/CMSE222 Digital Logic
CMPE223/CMSE222 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Terminology For a given term, each
More informationChapter 3. Boolean Algebra and Digital Logic
Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how
More information1. Mark the correct statement(s)
1. Mark the correct statement(s) 1.1 A theorem in Boolean algebra: a) Can easily be proved by e.g. logic induction b) Is a logical statement that is assumed to be true, c) Can be contradicted by another
More informationRevision: August 31, E Main Suite D Pullman, WA (509) Voice and Fax
Exercise 7: Combinational rithmetic Circuits Revision: ugust 3, 29 25 E Main uite D Pullman, W 9963 (59) 334 636 Voice and Fax TUDENT I am submitting my own work, and I understand penalties will be assessed
More information2 Combinational Logic
2 ombinational Logic O purblind race of miserable men, How many among us at this very hour o forge a lifelong trouble for ourselves, y taking true for false, and false for true! lfred, Lord Tennyson It
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationExperiment 4 Boolean Functions Implementation
Experiment 4 Boolean Functions Implementation Introduction: Generally you will find that the basic logic functions AND, OR, NAND, NOR, and NOT are not sufficient to implement complex digital logic functions.
More information1. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z
CS W3827 05S Solutions for Midterm Exam 3/3/05. Fill in the entries in the truth table below to specify the logic function described by the expression, AB AC A B C Z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2.
More informationECE380 Digital Logic
ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8- Terminology For
More informationDepartment of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals.
Last (family) name: First (given) name: Student I.D. #: Circle section: Lipasti Kim Department of Electrical and Computer Engineering University of isconsin - Madison ECE/CS 352 Digital System Fundamentals
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Intro to Verilog CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationUNCA CSCI 255 Exam 1 Spring February, This is a closed book and closed notes exam. It is to be turned in by 1:45 PM.
UNCA CSCI 255 Exam 1 Spring 2017 27 February, 2017 This is a closed book and closed notes exam. It is to be turned in by 1:45 PM. Communication with anyone other than the instructor is not allowed during
More informationChapter 4 Arithmetic Functions
Logic and Computer Design Fundamentals Chapter 4 Arithmetic Functions Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Overview Iterative combinational
More informationDigital Logic Design. Midterm #1
The University of Toleo f7ms_il7.fm - EES: Digital Logic Design Stuent Name_ Digital Logic Design Miterm # Problems Points. 3. 4 3. 6 4. Total 5 Was the eam fair? yes no //7 The University of Toleo f7ms_il7.fm
More informationGood Evening! Welcome!
University of Florida EEL 3701 Fall 2011 Dr Eric M Schwartz Page 1/11 Exam 2 Instructions: Turn off all cell phones, beepers and other noise making devices Show all work on the front of the test papers
More informationReal Digital Problem Set #6
Real igital Problem et #6. (2 points) ketch a block diagram for a magnitude comparator bit-slice circuit. Create K-maps to define the bit-slice circuit, and use them to find optimal logic equations. ketch
More informationChapter 2 Combinational
Computer Engineering 1 (ECE290) Chapter 2 Combinational Logic Circuits Part 2 Circuit Optimization HOANG Trang 2008 Pearson Education, Inc. Overview Part 1 Gate Circuits and Boolean Equations Binary Logic
More informationDepartment of Electrical and Computer Engineering University of Wisconsin - Madison. ECE/CS 352 Digital System Fundamentals.
Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/C 352 Digital ystem Fundamentals Quiz #2 Thursday, March 7, 22, 7:15--8:3PM 1. (15 points) (a) (5 points) NAND, NOR
More information2.6 BOOLEAN FUNCTIONS
2.6 BOOLEAN FUNCTIONS Binary variables have two values, either 0 or 1. A Boolean function is an expression formed with binary variables, the two binary operators AND and OR, one unary operator NOT, parentheses
More informationChapter 2. Boolean Expressions:
Chapter 2 Boolean Expressions: A Boolean expression or a function is an expression which consists of binary variables joined by the Boolean connectives AND and OR along with NOT operation. Any Boolean
More informationAnnouncements. Chapter 2 - Part 1 1
Announcements If you haven t shown the grader your proof of prerequisite, please do so by 11:59 pm on 09/05/2018 (Wednesday). I will drop students that do not show us the prerequisite proof after this
More informationCS2100 Computer Organisation Tutorial #8: MSI Components Answers to Selected Questions
C Computer Organisation Tutorial #8: MI Components Answers to elete Questions. Realize the following funtion with (a) an 8: multiplexer, an (b) a 4: multiplexer using the first input variables as the seletor
More informationLogic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 3 Additional Gates and Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 3 Additional Gates and Circuits Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View
More information4 Operations On Data 4.1. Foundations of Computer Science Cengage Learning
4 Operations On Data 4.1 Foundations of Computer Science Cengage Learning Objectives After studying this chapter, the student should be able to: List the three categories of operations performed on data.
More informationEECS 270 Midterm Exam
EECS 270 Midterm Exam Fall 2009 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1 /11 2 /4
More informationDigital Logic Design Exercises. Assignment 1
Assignment 1 For Exercises 1-5, match the following numbers with their definition A Number Natural number C Integer number D Negative number E Rational number 1 A unit of an abstract mathematical system
More informationArithmetic-logic units
Arithmetic-logic units An arithmetic-logic unit, or ALU, performs many different arithmetic and logic operations. The ALU is the heart of a processor you could say that everything else in the CPU is there
More informationCS8803: Advanced Digital Design for Embedded Hardware
CS883: Advanced Digital Design for Embedded Hardware Lecture 2: Boolean Algebra, Gate Network, and Combinational Blocks Instructor: Sung Kyu Lim (limsk@ece.gatech.edu) Website: http://users.ece.gatech.edu/limsk/course/cs883
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 5 & 6 Minimization with Karnaugh Maps Karnaugh maps lternate way of representing oolean function ll rows
More informationDigital Logic Design. Final Examination
The University of Toleo Section s5fs_il7.fm - EECS: igital Logic esign r. nthony. Johnson Stuent name igital Logic esign Final Examination Problems Points... Total 5 Was the exam fair? yes no The University
More informationCHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey
CHAPTER-2 STRUCTURE OF BOOLEAN FUNCTION USING GATES, K-Map and Quine-McCluskey 2. Introduction Logic gates are connected together to produce a specified output for certain specified combinations of input
More informationECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two Solutions 26 February 2014
Problem 1 (4 parts, 21 points) Encoders and Pass Gates Part A (8 points) Suppose the circuit below has the following input priority: I 1 > I 3 > I 0 > I 2. Complete the truth table by filling in the input
More informationStandard Forms of Expression. Minterms and Maxterms
Standard Forms of Expression Minterms and Maxterms Standard forms of expressions We can write expressions in many ways, but some ways are more useful than others A sum of products (SOP) expression contains:
More informationCSC 220: Computer Organization Unit 10 Arithmetic-logic units
College of Computer and Information Sciences Department of Computer Science CSC 220: Computer Organization Unit 10 Arithmetic-logic units 1 Remember: 2 Arithmetic-logic units An arithmetic-logic unit,
More informationLecture 7 Logic Simplification
Lecture 7 Logic Simplification Simplification Using oolean lgebra simplified oolean expression uses the fewest gates possible to implement a given expression. +(+)+(+) Simplification Using oolean lgebra
More informationAustin Herring Recitation 002 ECE 200 Project December 4, 2013
1. Fastest Circuit a. How Design Was Obtained The first step of creating the design was to derive the expressions for S and C out from the given truth tables. This was done using Karnaugh maps. The Karnaugh
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is ----- Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Intro to Verilog CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationOverview. EECS Components and Design Techniques for Digital Systems. Lec 16 Arithmetic II (Multiplication) Computer Number Systems.
Overview EE 15 - omponents and Design Techniques for Digital ystems Lec 16 Arithmetic II (Multiplication) Review of Addition Overflow Multiplication Further adder optimizations for multiplication LA in
More informationLogic Design (Part 2) Combinational Logic Circuits (Chapter 3)
Digital Logic Circuits Logic Design (Part ) Combinational Logic Circuits (Chapter 3) ² We saw how we can build the simple logic gates using transistors ² Use these gates as building blocks to build more
More informationStandard Boolean Forms
Standard Boolean Forms In this section, we develop the idea of standard forms of Boolean expressions. In part, these forms are based on some standard Boolean simplification rules. Standard forms are either
More informationLecture 6: Signed Numbers & Arithmetic Circuits. BCD (Binary Coded Decimal) Points Addressed in this Lecture
Points ddressed in this Lecture Lecture 6: Signed Numbers rithmetic Circuits Professor Peter Cheung Department of EEE, Imperial College London (Floyd 2.5-2.7, 6.1-6.7) (Tocci 6.1-6.11, 9.1-9.2, 9.4) Representing
More informationObjectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure
Objectives: 1. Design procedure. 2. undamental circuits. 1. Design procedure Design procedure has five steps: o Specification. o ormulation. o Optimization. o Technology mapping. o Verification. Specification:
More informationEXPERIMENT #8: BINARY ARITHMETIC OPERATIONS
EE 2 Lab Manual, EE Department, KFUPM EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS OBJECTIVES: Design and implement a circuit that performs basic binary arithmetic operations such as addition, subtraction,
More informationStudent Number: UTORid: Question 0. [1 mark] Read and follow all instructions on this page, and fill in all fields.
CSC 258H1 Y 2016 Midterm Test Duration 1 hour and 50 minutes Aids allowed: none Student Number: UTORid: Last Name: First Name: Question 0. [1 mark] Read and follow all instructions on this page, and fill
More information4 Operations On Data 4.1. Foundations of Computer Science Cengage Learning
4 Operations On Data 4.1 Foundations of Computer Science Cengage Learning Objectives After studying this chapter, the student should be able to: List the three categories of operations performed on data.
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.6 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Outlines Boolean Operations Laws of Boolean Algebra Rules of
More informationCS 31: Intro to Systems Digital Logic
CS 3: Intro to Systems Digital Logic Martin Gagné Swarthmore College January 3, 27 You re going to want scratch papr today borrow some if needed. Quick nnouncements Late Policy Reminder 3 late days total
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationECE 752 Adv. Computer Architecture I
. UIVERSIY OF WISCOSI ECE 752 Adv. Computer Architecture I Midterm Exam 1 Held in class Wednesday, March 9, 2005 ame: his exam is open books, open notes, and open all handouts (including previous homeworks
More informationCombinational Logic Circuits Part III -Theoretical Foundations
Combinational Logic Circuits Part III -Theoretical Foundations Overview Simplifying Boolean Functions Algebraic Manipulation Karnaugh Map Manipulation (simplifying functions of 2, 3, 4 variables) Systematic
More informationSystem Design. Final Review. ILGWEON KANG
System esign Final Review ILGWEON KANG igkang@ucsd.edu 1 SYSTEM ESIGN: uestion 1: Implement the following algorithm. 2 ESIGN A ATA SUBSYSTEM Table to list the instructions and the corresponding components.
More informationTWO-LEVEL COMBINATIONAL LOGIC
TWO-LEVEL COMBINATIONAL LOGIC OVERVIEW Canonical forms To-level simplification Boolean cubes Karnaugh maps Quine-McClusky (Tabulation) Method Don't care terms Canonical and Standard Forms Minterms and
More informationSummary. Boolean Addition
Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse
More informationDIGITAL CIRCUIT LOGIC UNIT 7: MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES
DIGITAL CIRCUIT LOGIC UNIT 7: MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES 1 iclicker Question 13 Considering the K-Map, f can be simplified as (2 minutes): A) f = b c + a b c B) f = ab d + a b d AB CD
More informationCARLETON UNIVERSITY. Laboratory 2.0
CARLETON UNIVERSITY Department of Electronics ELEC 267 Switching Circuits Jan 3, 28 Overview Laboratory 2. A 3-Bit Binary Sign-Extended Adder/Subtracter A binary adder sums two binary numbers for example
More informationDigital Logic Design. Midterm #1
The University of Toleo s7ms_il7.fm - EECS: igital Logic esign r. nthony. Johnson Stuent Name_ igital Logic esign Miterm # Problems Points. 3. 4 3. 6 4. Total 5 Was the eam fair? yes no /6/7 The University
More informationCS 151 Final. Q1 Q2 Q3 Q4 Q5 Total Credit Score. Instructions: Student ID. (Last Name) (First Name) Signature
CS 151 Final Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 15 pages including this cover. 2. Write down your Student-Id on the top of
More informationMODULE 5 - COMBINATIONAL LOGIC
Introduction to Digital Electronics Module 5: Combinational Logic 1 MODULE 5 - COMBINATIONAL LOGIC OVERVIEW: For any given combination of input binary bits or variables, the logic will have a specific
More informationSupplement to. Logic and Computer Design Fundamentals 4th Edition 1
Supplement to Logic and Computer esign Fundamentals 4th Edition MORE OPTIMIZTION Selected topics not covered in the fourth edition of Logic and Computer esign Fundamentals are provided here for optional
More informationChapter 6. Logic Design Optimization Chapter 6
Chapter 6 Logic Design Optimization Chapter 6 Optimization The second part of our design process. Optimization criteria: Performance Size Power Two-level Optimization Manipulating a function until it is
More informationBoolean Analysis of Logic Circuits
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 7 Lecture Title:
More information