Introduction to synthesis. Logic Synthesis


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1 Introduction to synthesis Lecture 5 Logic Synthesis Logic synthesis operates on boolean equations and produce optimized combinational logic
2 Logic Minimization Twolevel logic minimization Twolevel logic usually is one of the sumofproduct : f = ab+cd+ef productofsum : f = (a+b)(c+d)(e+f)... Multilevel logic minimization Find terms that can be shared In algebraic term, find common factors f = ab+ac+db+dc = a(b+c) +d(b+c) = (a+d)(b+c) Example 2 level F = abc + abd + a c d + b c d 4 NOTs, 4 3input ANDs, and 4input OR 2
3 Example multi level Decomposition X = ab, Y = c+d, F = XY + X Y Implement F with multilevel logic 2 NOTs, 3 2input ANDs, and 2 2input ORs Two level logic minimization Twolevel logic minimization can be seen as the origin of logic synthesis Theory and algorithms are well developed long time ago We will study these algorithms this month Any output combinational function can be implemented as 2level SOP In the worst case, you can get the truth table and collect minterms Simple SOP may not be the most efficient way Need to find prime implicant Multilevel logic will reduce size What if implementing multiple functions? Need to find minimal implementation (shared implicants) 3
4 2level minimal implementation Theorem (Quine): A minimal SOP implementation of a function must always consist of a sum of prime implicants Apply to 2level logic only So finding prime implicants are crucial Implicant: a product term p that is included in the function f F=xy +yz => xy and xyz are implicant Prime Implicant: an implicant that is not included in any other implicant xy is prime, but xyz is not High Level Synthesis Remember that your Verilog code is eventdriven under the simulation model blocks are executed in parallel Your hardware is done from primary inputs to primary outputs How does it convert Verilog code into hardware? Something is missing here. 4
5 Determine the order of data flow To convert a parallelstyled description into a sequential logic it needs to first determine the ORDERING in the data flow In synthesis, it constructs a socalled data flow graph to represent the overall computation Based on the data flow graph, it will decide how many latches should be used where to put them in the logic (the ordering), etc. A Simple Example  Flow Graph 5
6 Synthesis Has Limitations Synthesis is not a magic word Many behavior descriptions are not synthesizable! Results of synthesis may not satisfy the needs too big, too slow, or even contain errors custom designs are required verification is required (never trust the synthesis results completely) CommonlySupported Constructs 6
7 Unsupported Constructs Combinational Logic Elements Commonly synthesized combinational logic Multiplexer Decoder Encoder Comparator Random Logic Lookup Table Adder Subtractor ALU Multiplier PLA Structure Parity Generator 7
8 Synthesis examples A quick look Synthesis Example A B A B TWOBIT COMPARATOR A_lt_B A_gt_B A_eq_B A_lt_B = A B + A A B + A B B A_gt_B = A B + A B B + A A B A_eq_B = A A B B + A A B B + A A B B + A A B B A>B A B A B 8
9 Gate Implementation A W6 W module compare_2_str (A_lt_B, A_gt_B, A_eq_B, A, A, B, B); B A W7 W2 A_lt_B input A, A, B, B; output A_lt_B, A_gt_B, A_eq_B; wire w, w2, w3, w4, w5, w6, w7; B W3 W4 W5 A_gt_B A_eq_B or (A_lt_B, w, w2, w3); nor (A_gt_B, A_lt_B, A_eq_B); and (A_eq_B, w4, w5); and (w, w6, B); and (w2, w6, w7, B); and (w3, w7, B, B); not (w6, A); not (w7, A); xnor (w4, A, B); xnor (w5, A, B); endmodule Using IfElse Procedurestyle behavior code module compare_2_algo (A_lt_B, A_gt_B, A_eq_B, A, B); input [:] A, B; output A_lt_B, A_gt_B, A_eq_B; reg A_lt_B, A_gt_B, A_eq_B; (A or B) // Behavior and event expression begin A_lt_B = ; A_gt_B = ; A_eq_B = ; A if (A==B) A_eq_B = ; else if (A > B) A_gt_B = ; B else A_lt_B = ; BEHAVIOR end A endmodule B A_lt_B reg A_gt_B reg A_eq_B reg A_lt_B A_gt_B A_eq_B 9
10 Two Synthesized Results From behavior: A[] A_eq_B A_lt_B B[:] B[] B[] A[:] A[] A_gt_B A W6 W B A W7 W2 A_lt_B B W3 A_gt_B From gates: W4 A_eq_B W5 Synthesize decision w/ MUX Procedure CC(Rin) { if ( test(rin) ) {res = Rin + 32;} else {res = Rin 32;} end Rin 32 test select res +/ The example is just a pseudo code
11 Synthesis with library cells module or_nand_ (enable, x, x2, x3, x4, y); input enable, x, x2, x3, x4; output y; wire w, w2, w3; or (w, x, x2); or (w2, x3, x4); or (w3, x3, x4); // redundant nand(y, w, w2, w3, enable); endmodule Example bitwise operations
12 Multilevel synthesis Identify shared logic in multilevel structure Control Logic for MUX Datapath 4 channel mux with a continuous assignment 2
13 Synthesized Logic Check sel=,,2,3 Synthesis of MUX Decoded MUX 3
14 Ifthenelse 2 MUX for an if Control Logic at Select Line Control logic 4
15 Unexpected Latches When a case statement is incomplete, the synthesis may infer the need of a latch to hold result while unspecified inputs present General Synthesis Result when (sel_a, sel_b)=,, y_out keeps the old value 5
16 Priority Decode Structure low high Technology Mapping Tech Libraries contains cell implemented with certain technology (.3μ,.8 μ, or.25 μ, etc.) 6
17 Technology Mapping Library Cell Mapping 5bit adder 7
18 Enforce Shared Resource We want to use adder, instead of 2 Cont 8
19 Buses and Tristate Buffer Bidirectional Buses bidirectional 9
20 Mux Bus Driver TriState and Don t Care Don t care 2
21 Two Versions Optimized with don t care Summary Synthesis is not magic It can make mistakes Or produce unsatisfactory results Much of the synthesis intelligence comes from addhoc rules and pattern matching Writing code to influence a synthesis tool demands great experience Today, because of EDA tools, doing design has a lot to do with working around the tool(s) Synthesis happens at different levels Behavior, highlevel 2level and multi logic level Synthesis can be independent of technology mapping Physical synthesis is an entirely different process Contains placement and routing 2
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