ENEE 245 Lab 1 Report Rubrics

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1 ENEE 4 Lab 1 Report Rubrics Design Clearly state the design requirements Derive the minimum SOP Show the circuit implementation. Draw logic diagram and wiring diagram neatly Label all the diagrams/tables (Figure 1,, Table 1,, ) and 3 explain them clearly Hardware List all the equipment (complete information) List all the components (name/value and quantity) 3 Experiment Explain what is and why you use it Explain how you use Show the connection diagram of and explain how each pin is connected and why Show the outputs Qa, Qb, Qc, and Qd Explain how you select A, B, C from outputs Show your SOP circuit inputs and output: A, B, C and F 0 Label all the diagrams/figures and explain them clearly Analysis Verify your circuit performance Discuss the selection of A, B, C Comment on any problems encountered if any Conclusion Present overall conclusions related to the original purpose of learned from the experiment Total 0

2 ENEE 4 Lab 4 Report Rubrics Design 1. Design a 1-bit full adder Clearly state the design requirements. Show the design details (Sum, Carry functions). 3 Show the circuit implementation. Draw logic diagram and wiring diagram neatly.. Design a full adder with Verilog design entry List all the components (name/value and quantity) Experiment 1. Include the annotated printout of the 1-bit full adder input and output waveforms: x, y, Cin, Sum, and Carry. Clearly explain how you set up the experiment to obtain the results.. Measure the rise, fall time for the signal Sum. Measure the time delay from input x to output Sum. Show annotated printouts. Explain how each measurement is done clearly. 3. Functional simulation of your 1-bit full adder. Explain and verify. 4. Timing simulation of your 1-bit full adder. Explain and verify.. Design a 4-bit ripple carry adder. Discuss the theory that your design is based on such as block diagram, Boolean functions, etc. 6. Functional simulation of 4-bit ripple carry adder. Explain the simulation setup and verify the result. 7. Design a 4-bit carry look-ahead adder. Discuss the theory that your design is based on such as block diagram, Boolean functions etc. 8. Functional simulation of your 4-bit CLA adder. Explain the simulation setup and verify the result. 9. Explain the settings of your inputs and outputs related to the Altera DE-11 FPGA board for each Verilog design entry. Analysis Discuss the difference between the ripper adder and the CLA adder Estimate the delay for the 4-bit ripple carry adder 3 Compare functional simulation and timing simulation results of your 1-bit full adder. Comment on glitches if any. Show the RTL viewer of the 1-bit full adder, 4-bit ripple adder. Compare them with what you learned from ENEE44. Comment on any problems encountered if any Conclusion Present overall conclusions related to the original purpose of the experiment. Comment on the outcome and what was learned. Format Label all the diagrams/tables and Documentations of your Verilog code. Total 0

3 ENEE 4 Lab Report Rubrics List all the components (name/value and quantity) Design & 1. Discuss the theory of a 3 to 8 decoder. Experiment. Create a schematic design for decoder 3. Functional simulation of the schematic design of decoder. Explain the simulation setup and verify the result. 4. Verilog design for 3 to 8 decoder with explanations.. Functional simulation of the Verilog design of decoder. Explain the simulation setup and verify the result. 6. Discuss the theory of a 8 to 3 encoder and priority encoder 3 7. Verilog design for 8 to 3 encoder with explanations. 8. Verilog design for 8 to 3 priority encoder with explanations. 9. Settings of your inputs and outputs for all the circuits when tested on FPGA board Analysis Difference between encoder and priority encoder. What difference have you observed when you were testing both circuits on the FPGA board? New aspects of the Verilog language learned in this lab Any difficulties or unexpected results encountered Conclusion Present overall conclusions related to the original purpose of Format Label all the diagrams/tables (Figure 1,, Table 1,, ) and Documentations of your Verilog code. Total 0

4 ENEE 4 Lab 6 Report Rubrics List all the components (name/value and quantity) Design & 1. Show the given schematic a 4-bit synchronous counter and Experiment your Verilog design. Show the number of logic elements (LEs) used in the above design. Show the RTL viewer of your 4-bit counter designed; compare the result to the given schematic. Functional simulation of your 4-bit synchronous counter. Explain the simulation setup and verify the result. Show your augmented Verilog code. Explain your input and output settings for the DE-11 board.. Verilog design for 4-bit counter using behavioral modeling Show the number of logic elements (LEs) used in the above design. Show the RTL viewer of your 4-bit counter designed before augmentation; compare it with the circuit synthesized in previous design. 3. Verilog design for 4-bit counter using behavioral modeling With negative edge of clear added to the sensitivity list Comment on your circuit performances and the differences of the Clear operation with and without negative edge of clear added to the sensitivity list 4. Verilog design for the 4-bit counter on 1 second interval. Explain how the clock is generated. Analysis Compare the structural modeling and behavioral modeling based on your counters. Discuss the difference in the circuits synthesized. Any difficulties or unexpected results encountered Conclusion Present overall conclusions related to the original purpose of Format Label all the diagrams/tables (Figure 1,, Table 1,, ) and Documentations of your Verilog code. Total 0

5 ENEE 4 Lab 7 Report Rubrics Design Clearly state the design requirements. Show the design details (state diagram, state assignments, state table, and derive input and output equations) Show the circuit implementation. Draw logic diagram using Quartus II schematic entry. Hardware List all the equipment (complete information) List all the components (name/value and quantity) 3 Experiment 1. Discuss how you generate the input testing sequence x using 7416 shift register. Use a diagram to show and explain how each pin of 7416 is connected. Discuss how you use SPST momentary switch to control the shift/load and how you use DIP switch to set the parallel inputs of Discuss why you need to use the inverse of the clock of 7416 to drive JK flip-flops. 3. Show the circuit performance for 3 different input combinations 0 using logic analyzer. Include clock, x, output z in each printout. For each case, identify the value of bit stream x and z and verify circuit performance. 4. Design a Verilog code for the Moore sequence detector.. Perform functional simulation of the Verilog code. Explain the simulation setup and verify the result. 6. Augment the Verilog code for the DE-11 FPGA board. Explain the settings of your inputs and outputs related to the Altera DE-11 FPGA board. Analysis Comment on the glitches in the sequence detector built on 3 breadboard. Comment on the glitches in the sequence detector functional 3 simulation. Comment on any problems encountered if any Conclusion Present overall conclusions related to the original purpose of the experiment. Comment on the outcome and what was learned from the experiment. Format Label all the diagrams/tables (Figure 1,, Table 1,, ) and explain them clearly in the report Documentations of your Verilog code. 3 Total 0

6 ENEE 4 Lab 8 Report Rubrics List all the components (name/value and quantity) Design & Design a Verilog module of a BCD adder. Explain clearly what 40 Experiment BCD adder is and how you designed it. Include the block diagram. Augment your code for the FPGA board implementation Explain the input and output settings. - Error display EE if either input A or input B is great than 9. Explain your design for the error display. Analysis Any difficulties or unexpected results encountered Conclusion Present overall conclusions related to the original purpose of Format Label all the diagrams/tables (Figure 1,, Table 1,, ) and Documentations of your Verilog code. Total 0

7 ENEE 4 Lab 9 Report Rubrics List all the components (name/value and quantity) Design & Draw the block diagram implementation of the 4 bit by 4 bit Experiment multiplier using 4 bit binary adders. Create a Verilog design for the multiplier. Explain clearly how 0 you designed the circuit in your Verilog module. Functional simulation. Explain the simulation setup and verify 0 the result. Augment your code for the FPGA board implementation. - Explain the input and output settings. - A hex to 7-segment display module Analysis Comment on your Verilog design. Comment on any difficulties or unexpected results encountered. Conclusion Present overall conclusions related to the original purpose of Format Label all the diagrams/tables (Figure 1,, Table 1,, ) and Documentations of your Verilog code. Total 0

8 ENEE 4 Lab Report Rubrics List all the components (name/value and quantity) Design & Manual Calculations Experiment Verilog design of a digital calculator Functional simulation of the Verilog code. Explain the simulation setup and verify the result. Augment the Verilog file for FPGA board. Explain the design 30 requirements for each operation. - Control inputs using switches - Control four operations using pushbuttons - Display: Addition, Subtraction, Multiplication, Division Your results displayed on HEX should hold when pushbutton is released. Explain how you implemented this feature in your design. Analysis Comment on your Verilog design and structure of your Verilog implementation. Check Design Units for all the units that are used in your design. What is each unit and what does it do? Comment on any difficulties or unexpected results encountered. Conclusion Present overall conclusions related to the original purpose of Format Label all the diagrams/tables (Figure 1,, Table 1,, ) and Documentations of your Verilog code. Total 0

ENEE245 Digital Circuits and Systems Lab Manual

ENEE245 Digital Circuits and Systems Lab Manual Department of Engineering, Physical & Computer Sciences Montgomery College Version 1.1 Copyright Prof. Lan Xiang (Do not distribute without permission) 1