St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad

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1 St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad Subject: Digital Design Using Verilog Hdl Class : ECE-II Group A (Short Answer Questions) UNIT-I 1 Define verilog HDL? 2 List levels of design description in verilog HDL? 3 Describe is concurrency? 4 What is simulation and synthesis? 5 What is functional verification? 6 What are system tasks? 7 Write short notes on programming language interface (PLI). 8 What is module? 9 What is a simulation and synthesis tool? 10 What is test bench? 11 Define keywords and identifiers? 12 What are white space characters? 13 Define comments and numbers? 14 Define strings and logic values? 15 What is a data types? And what are those? 16 Define scalars and vectors? 17 Define parameters and memory operators? 18 Define system tasks? UNIT-II 1 What is gate level modeling? 2 What is AND gate primitive? 3 What is module structure? Give the example of module structure. 4 Define tri-state gate? 5 What is array of instances of primitives? 6 Define delay? 7 Define strengths and content resolution? 8 What is a net data type? 9 How many types of net data types? 10 How many tri-state gates are there in verilog? 11 What is continuous assignment structure? 12 What is assignment to vectors? 13 Define operators in verilog? UNIT-III 1 What is behavioral modeling? 2 What are operations and assignments? 3 Define functional Bifurcation 4 Define initial construct. 5 Define always construct. 6 Explain assignments with delays 7 Define wait construct 8 Explain multiple always blocks

2 9 Define blocking and non-blocking assignments 10 Explain the case statement 11 Draw a simulation flow chart 12 Explain if and if-else construct 13 Explain assign and de-assign construct. 14 Define repeat construct 15 Write the syntax for a for loop 16 Write the syntax for a while loop and forever loop 17 Explain parallel blocks 18 Explain force release construct UNIT-IV 1 Explain basic transistor switches. 2 Define basic switch primitive. 3 Explain the operation of nmos switch. 4 Explain the operation of pmos switch. 5 Define resistive switches. 6 Define cmos switch. 7 Explain Bi-Directional gates. 8 How to insatiate with strength and delays. 9 Define system task. 10 Define parameter. 11 Explain parameter declaration and assignments. 12 Define module paths. 13 Define specify block. 14 Define system function. 15 Explain $display Task. 16 Explain file based tasks and functions. 17 Explain compiler directives. 18 Define hierarchical access. UNIT-V 1 What are the types of sequential models? 2 Explain Feedback model. 3 Explain capacitive model. 4 Explain implicit model. 5 What are the basic memory components? 6 Explain functional register. 7 Define state machine coding. 8 How do you explain sequential synthesis? 9 What is test bench? 10 How to test a combinational circuit. 11 What is sequential circuit testing? 12 Explain test bench techniques. 13 Define design verification. 14 Define assertion verification.

3 Group - B (Long Answer Questions) UNIT-I 1 Write short note on Verilog as HDL 2 Discuss Level of design description 3 Explain top-down design methodology with example. Write short notes on, (a) Concurrency 4 (b) Functional verification Define the following terms relevant to Verilog HDL, (a). Simulation versus synthesis. (b). PLI 5 (c). System tasks what are the system tasks available in Verilog for making and controlling 6 simulation? Explain about, (a). Display tasks (b). Strobe tasks 7 (c). Monitor tasks with examples. Define the following terms relevant to Verilog HDL. (a). Module 8 (b). Test bench. 9 Write a syntax functions and tasks with one example. 10 Write about $readmemb with example. 11 Write value change dump file. 12 Explain the synthesis procedure in Verilog HDL. Give the surfaces for Verilog module and explain gate instantiations with 13 examples. UNIT-II 1 Explain in brief built-in primitive gates that are available in Verilog HDL. 2 Explain NAND gate primitive with Verilog module. 3 Explain NOR gate primitive with Verilog module. 4 Design a module for addition of 16 bit words. 5 Write Verilog module for addition 16 bit words. What is a three-state gate and explain each type of three-state gate with truth 6 tables? 7 Write a Verilog code for tri-state devices. Write Verilog HDL source code for a gate level description of 4 to 1 multiplexer 8 circuit. Draw the relevant logic diagram. Implement Verilog HDL source code and draw the logic diagram of a 2-to-4 9 decoder circuit. Give the gate level description. 10 Design module and a test bench for a half-adder. 11 Design module and a test bench for a 4 to 1 multiples module. 12 Explain simple latch with Verilog module. 13 Design a RS-flip with NAND gates. 14 Write a Verilog code for RS flip-flop with NAND gates. 15 Explain clocked RS flip-flop Verilog module and test bench. 16 Design a D-Flip-flop with gate primitives and write its Verilog code. 17 Design a D flip flop using NAND gates.

4 18 Write a Verilog code for D flip flop using NAND gates. 19 Classify delays and explain. 20 Explain inertial and intra-assignment delays in Verilog. 21 Design a JK flip flop using NAND gates. 22 Write a Verilog code for JK flip flop using NAND gates. Explain the design approach of a master slave flip-flop with gate primitives. (OR) 23 Design a master slave JK flip-flop using NAND gates. 24 Write a Verilog code for master slave JK flip flop using NAND gates. 25 Design a T flip flop using NAND gates. 26 Write a Verilog code for T flip flop using NAND gates. 27 Write notes on gate delays with necessary instantiations. 28 Explain delays with tristate gates. 29 Classify and explain strength and contention resolution. Design module to illustrate use if the wand-type net and test bench with 30 stimulation results. Draw the half adder circuits in terms of EX-OR and AND gates. Prepare the half 31 adder module and test bench in terms of and AND gate primitives. 32 Design a module and test bench for a full-adder. 33 Design a 4 X 4 multiplier circuit and write its Verilog HDL code. 34 Write a Verilog HDL code for ripple-carry adder using generic specification? 35 Design a 4 bit full adder using gate level primitives and write its HDL code. Design a 1to 4 demultiplexer module by using 2 to 4 decoder, and white its 36 Verilog code. 37 Explain continuous assignment structures with examples. Explain about the concurrent statements in data flow level. Give one example to 38 each one. Explain net delay with assignment delay and effects of net delay with suitable 39 example. 40 Explain combining assignment and net declarations with examples. UNIT-III Write a short note on, (a). Functional bifurcation 1 b). Intra-assignment delays. 2 Write the differences between begin-end and fork-blocks with examples. 3 Design up counter coding procedural assignment. 4 Write up counter test bench, simulation results. Write the syntax for the following constructs and give one example for each relevant to behavioral Verilog HDL modeling. (a). initial construct, (b). always construct 5 (c). wait construct. What is the difference between an intra- statement delay and an inter- 6 statement delay? explain using an example. Write short notes on the following with examples, (a). Intra-assignment delays (b). Delay assignments 7 (c). Zero delay 8 What are the advantages of multiple always blocks? Explain with example 9 Write a Verilog module for a rudimentary serial transmitter module.

5 10 Explain multiple always blocks. Write a model using the behavioral modeling style to describe the behavior of a 11 JK flip- flop using an always statement. (a). Design Verilog module to identify the highest priority interrupts. 12 (b). Write test bench simulation results of above questions with explanation (a). Design module to convert angels in radians to one in degrees. 13 (b). Write Verilog code above question with explanation. 14 Explain blocking and non-blocking statement with examples. Write a Verilog HDL code for n-bit shift register with an enable input using 15 blocking assignments. Draw the flowchart for the simulation flow. OR Explain flowchart for the 16 simulation flow. 17 Write Verilog code using case statement for any one example. Write the syntax for the following constructs and give one example for each levant to behavioral Verilog HDL modeling. (a). The case statement 18 (b). If and if-else constructs UNIT-IV 1 Design half subtractor using CMOS switches. 2 Write the Verilog code for half subtractor using CMOS switches. 3 Design code, test bench, results for CMOS switch with a single control line. 4 Design CMOS flip-flop. 5 Design Verilog module for CMOS flip-flop. Explain bi-directional gates with suitable logic diagrams and give their switch 6 level modeling 7 Design half -adder using CMOS switches. 8 Write the Verilog code for half adder using CMOS switches. 9 Write about basic switch primitives. Write notes on time delays with switch primitives relevant to switch level 10 modeling. How strength and delays are instantiated? Explain. OR Write notes on instantiations with strength and delays relevant to switch level 11 modeling. Define and explain the following terms relevant to Verilog HDL, (a) Module parameters (b) File-based tasks and functions 12 (c) Compiler directives 13 Explain parameter declaration and assignments. 14 Explain type declaration for parameters. 15 Explain automatic(recursive) function. 16 Explain about module paths. Define and explain the following terms relevant to Verilog HDL, (a) Hierarchical access 17 (b) Path delays. 18 Explain $ finish task with example. 19 Explain $ random function with example. 20 Explain asymmetric sequence generator with example.

6 UNIT-V What are the various sequential memory storage models? Explain in detail about 1 each of them. Explain cross-coupled NOR latch and ALL NAND clocked SR latch with the help of 2 neat sketches and write the Verilog cods for each of them. Draw the block diagram of master-slave flip-flop constructed using latches and 3 write the Verilog code for the same. 4 Explain about sequential UDP with the help of an example. Draw and explain the block diagram of master-slave flip-flop with two feedback 5 blocks using assign statements. Also write the Verilog code for the same. Explain behavioral modeling for D-type latch and the use of non-blocking 6 assignments in latch modeling. Also with the Verilog code for each of them. 7 Write and explain the Verilog module for positive edge trigger flip-flop. Write a Verilog module for D flip-flop with synchronous control and asynchronous 8 control. And compare the controls of both. What is function of fork-join construct? Design a Verilog module for D flip- flop 9 using this construct. 10 Write a Verilog code for D flip-flop using assign and deassign statements. 11 Define setup time. Write a Verilog code for D flip-flop setup time. 12 Define hold time. Design a Verilog module for D flip-flop with hold time. Discuss about setup hold, width and period checks used in Verilog. Write a 13 Verilog module for D flip-flop using setup hold, width and period checks. Design a Verilog module for the following, (i)8-bit transparent D-Latch 14 (ii)8-bit register with tri-state output. How the memory initialization does is carried out in Verilog? Explain with the help 15 of an example. 16 What are the rules to be followed to declare and to use the bidirectional lines? 17 Write a Verilog module for PLA. What is functional register? Write and explain the Verilog module for basic shift 18 register? 19 Design and explain the Verilog module for universal shift register. Explain about shift register that uses separates combinational and sequential 20 blocks. Also write a Verilog code for the same. 21 Write a Verilog code for 4-binary up-down counter. 22 Write short notes on gray-code counter. Also design a Verilog module for same. 23 Explain about LFSR and design its Verilog module in structural model. Explain MISR with the help of a neat sketch and also write the Verilog code for 24 the same. 25 Explain about FIFO Queue with the help of block diagram. 26 Write a Verilog code for FIFO Queue. Write a short notes on Moore 101 sequence detector. And write the Verilog code 27 for the same. 28 Explain in brief about Mealy 101 sequence detector. 29 Explain how the state machine is designed for large number of input-output line. 30 Write a Verilog code for moore detector using Huffman model. Also explain it. 31 Explain about ROM-based controller. Write the Verilog code for the same. Explain about the following with the help of neat block diagram, 32 (a)implementation of FPGA latch (b)implementation of FPGA flip-flop. Write a Verilog module for 4-bit ALU, also obtain its test bench and simulation 33 results

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