Writing Circuit Descriptions 8

Size: px
Start display at page:

Download "Writing Circuit Descriptions 8"

Transcription

1 8 Writing Circuit Descriptions 8 You can write many logically equivalent descriptions in Verilog to describe a circuit design. However, some descriptions are more efficient than others in terms of the synthesized circuit s area and speed. The way you write your Verilog source code can affect synthesis. This chapter describes how to write a Verilog description to ensure an efficient implementation. Topics include How Statements Are Mapped to Logic Don t Care Inference Propagating Constants Synthesis Issues Designing for Overall Efficiency / 8-1

2 Here are some general guidelines for writing efficient circuit descriptions: Restructure a design that makes repeated use of several large components, to minimize the number of instantiations. In a design that needs some, but not all, of its variables or signals stored during operation, minimize the number of latches or flipflops required. Consider collapsing hierarchy for more-efficient synthesis. How Statements Are Mapped to Logic Verilog descriptions are mapped to logic by the creation of blocks of combinational circuits and storage elements. A statement or an operator in a Verilog function can represent a block of combinational logic or, in some cases, a latch or register. When mapping complex operations, such as adders and subtracters, Design Compiler inserts arithmetic operators into the design as levels of hierarchy. The description fragment shown in Example 8-1 represents four logic blocks: A comparator that compares the value of b with 10 An adder that has a and b as inputs An adder that has a and 10 as inputs A multiplexer (implied by the if statement) that controls the final value of y / 8-2

3 Example 8-1 Four Logic Blocks if (b < 10) y = a + b; else y = a + 10; The logic blocks created by HDL Compiler are custom-built for their environment. That is, if a and b are 4-bit quantities, a 4-bit adder is built. If a and b are 9-bit quantities, a 9-bit adder is built. Because HDL Compiler incorporates a large set of these customized logic blocks, it can translate most Verilog statements and operators. Note: If the inputs to an adder or other operator resources are 4 bits or less, the hierarchy is automatically collapsed during the execution of the compile command. Design Structure HDL Compiler provides significant control over the preoptimization structure, or organization of components, in your design. Whether or not your design structure is preserved after optimization deps on the Design Compiler options you select. Design Compiler automatically chooses the best structure for your design. You can view the preoptimized structure in the Design Analyzer window and then correlate it back to the original HDL source code. You control structure by the way you order assignment statements and the way you use variables. Each Verilog assignment statement implies a piece of logic. The following examples illustrate two possible descriptions of an adder s carry chain. Example 8-2 results in a ripple carry implementation, as in Figure 8-1. Example 8-3 has more / 8-3

4 Example 8-2 structure (gates), because the HDL source includes temporary registers, and it results in a carry-lookahead implementation, as in Figure 8-2. Ripple Carry Chain // a is the add // b is the aug // c is the carry // cin is the carry in c0 = (a0 & b0) (a0 b0) & cin; c1 = (a1 & b1) (a1 b1) & c0; Figure 8-1 Ripple Carry Chain Implementation cin a0 b0 a1 b1 c0 c1 Example 8-3 Carry-Lookahead Chain // p s are propagate // g s are generate p0 = a0 b0; g0 = a0 & b0; p1 = a1 b1; g1 = a1 & b1; c0 = g0 p0 & cin; c1 = g1 p1 & g0 p1 & p0 & cin; / 8-4

5 Figure 8-2 Carry-Lookahead Chain Implementation cin a0 b0 a1 b1 c0 c1 Example 8-4 You can also use parentheses to control the structure of complex components in a design. HDL Compiler uses parentheses to define logic groupings. Example 8-4 and Example 8-5 illustrate two groupings of adders. The circuit diagrams show how grouping the logic affects the way the circuit is synthesized. When Example 8-4 is parsed, (a + b) is grouped together by default, then c and d are added one at a time. 4-Input Adder z = a + b + c + d; a b c d z / 8-5

6 Example Input Adder With Parentheses z = (a + b) + (c + d); a b c d z Design Compiler considers other factors, such as signal arrival times, to determine which implementation is best for your design. Note: Manual or automatic resource sharing can also affect the structure of a design. Using Design Knowledge In many circumstances, you can improve the quality of synthesized circuits by better describing your high-level knowledge of a circuit. HDL Compiler cannot always derive details of a circuit architecture. Any additional architectural information you can provide to HDL Compiler can result in a more efficient circuit. / 8-6

7 Optimizing Arithmetic Expressions Design Compiler uses the properties of arithmetic operators (such as the associative and commutative properties of addition) to rearrange an expression so that it results in an optimized implementation. You can also use arithmetic properties to control the choice of implementation for an expression. Three forms of arithmetic optimization are discussed in this section: Merging cascaded adders with a carry Arranging expression trees for minimum delay Sharing common subexpressions Merging Cascaded Adders With a Carry If your design has two cascaded adders and one has a bit input, HDL Compiler replaces the two adders with a simple adder that has a carry input. Example 8-6 shows two expressions in which cin is a bit variable connected to a carry input. Each expression results in the same implementation. To infer cascaded adders with a carry input, set the variable to true (the default is false): hdlin_use_cin = true / 8-7

8 Example 8-6 Cascaded Adders With Carry Input z <= a + b + cin; t <= a + b; z <= t + cin; a b cin cin a b z z Example 8-7 Arranging Expression Trees for Minimum Delay If your goal is to speed up your design, arithmetic optimization can minimize the delay through an expression tree by rearranging the sequence of the operations. Consider the statement in Example 8-7. Simple Arithmetic Expression Z <= A + B + C + D; The parser performs each addition in order, as though parentheses were placed as shown, and constructs the expression tree shown in Figure 8-3: Z <= ((A + B) + C) + D; / 8-8

9 Figure 8-3 A Default Expression Tree B C D Z Considering Signal Arrival Times To determine the minimum delay through an expression tree, Design Compiler considers the arrival times of each signal in the expression. If the arrival times of each signal are the same, the length of the critical path of the expression in Example 8-7 equals three adder delays. The critical path delay can be reduced to two adder delays if you add parentheses to the first statement as shown. Z <= (A + B) + (C + D); The parser evaluates the expressions in parentheses first and constructs a balanced adder tree, as shown in Figure 8-4. / 8-9

10 Figure 8-4 Balanced Adder Tree (Same Arrival Times for All Signals) A B C D Z Suppose signals B, C, and D arrive at the same time and signal A arrives last. The expression tree that produces the minimum delay is shown in Figure 8-5. Figure 8-5 B Expression Tree With Minimum Delay (Signal A Arrives Last) C D A Z Using Parentheses You can use parentheses in expressions to exercise more control over the way expression trees are constructed. Parentheses are regarded as user directives that force an expression tree to use the groupings inside the parentheses. The expression tree cannot be rearranged to violate these groupings. If you are not sure about the best expression tree for an arithmetic expression, leave the expression ungrouped. Design Compiler can reconstruct the expression for minimum delay. / 8-10

11 Example 8-8 To illustrate the effect of parentheses on the construction of an expression tree, consider Example 8-8. Parentheses in an Arithmetic Expression Q <= ((A + (B + C)) + D + E) + F; The parentheses in the expression in Example 8-8 define the following subexpressions, whose numbers correspond to those in Figure 8-6: 1 (B + C) 2 (A + (B + C)) 3 ((A + (B + C)) + D + E) These subexpressions must be preserved in the expression tree. The default expression tree for Example 8-8 is shown in Figure 8-6. / 8-11

12 Figure 8-6 Expression Tree With Subexpressions Dictated by Parentheses B C 1 2 A 3 D E F Q Design Compiler restructures the expression tree in Figure 8-6 to minimize the delay and still preserve the subexpressions dictated by the parentheses. If all signals arrive at the same time, the result is the expression tree shown in Figure 8-7. Figure 8-7 B Restructured Expression Tree With Subexpressions Preserved C A D E F Q / 8-12

13 Design Compiler automatically optimizes expression trees to produce minimum delay. If you do not want HDL Compiler to optimize the expression trees in your design, enter the following command: dc_shell> set_minimize_tree_delay false The set_minimize_tree_delay command applies to the current design. The default for the command is true. Example 8-9 Considering Overflow Characteristics When Design Compiler performs arithmetic optimization, it considers how to handle the overflow from carry bits during addition. The optimized structure of an expression tree is affected by the bit-widths you declare for storing intermediate results. For example, suppose you write an expression that adds two 4-bit numbers and stores the result in a 4-bit register. If the result of the addition overflows the 4- bit output, the most significant bits are truncated. Example 8-9 shows how HDL Compiler handles overflow characteristics. Adding Numbers of Different Bit-Widths t <= a + b; // a and b are 4-bit numbers z <= t + c; // c is a 6-bit number In Example 8-9, three variables are added (a +b+c). A temporary variable, t, holds the intermediate result of a + b. Suppose t is declared as a 4-bit variable so the overflow bits from the addition of a + bare truncated. The parser determines the default structure of the expression tree, which is shown in Figure 8-8. / 8-13

14 Figure 8-8 a[4] Default Expression Tree With 4-Bit Temporary Variable b[4] c[6] t[4] z[6] Now suppose the addition is performed without a temporary variable (z =a+b+c). HDL Compiler determines that five bits are needed to store the intermediate result of the addition, so no overflow condition exists. The results of the final addition might be different from the first case, where a 4-bit temporary variable is declared that truncates the result of the intermediate addition. Therefore, these two expression trees do not always yield the same result. The expression tree for the second case is shown in Figure 8-9. Figure 8-9 a[4] Expression Tree With 5-Bit Intermediate Result b[4] c[6] [5] z[6] Now suppose the expression tree is optimized for delay and that signal a arrives late. The tree is restructured so that b and c are added first. Because c is declared as a 6-bit number, Design Compiler / 8-14

15 determines that the intermediate result must be stored in a 6-bit variable. The expression tree for this case, where signal a arrives late, is shown in Figure Note how this tree differs from the expression tree in Figure 8-8. Figure 8-10 b[4] Expression Tree for Late-Arriving Signal c[6] a[4] [6] z[6] Example 8-10 Sharing Common Subexpressions Subexpressions consist of two or more variables in an expression. If the same subexpression appears in more than one equation, you might want to share these operations to reduce the area of your circuit. You can force common subexpressions to be shared by declaring a temporary variable to store the subexpression, then use the temporary variable wherever you want to repeat the subexpression. Example 8-10 shows a group of simple additions that use the common subexpression (a + b). Simple Additions With a Common Subexpression temp <= a + b; x <= temp; y <= temp + c; / 8-15

16 Example 8-11 Instead of manually forcing common subexpressions to be shared, you can let Design Compiler automatically determine whether sharing common subexpressions improves your circuit. You do not need to declare a temporary variable to hold the common subexpression in this case. In some cases, sharing common subexpressions results in more adders being built. Consider Example 8-11, where A+Bis a common subexpression. Sharing Common Subexpressions if cond1 Y <= A + B; else Y <= C + D; ; if cond2 Z <= E + F; else Z <= A + B; ; If the common subexpression A + B is shared, three adders are needed to implement this section of code: (A + B) (C + D) (E + F) If the common subexpression is not shared, only two adders are needed: one to implement the additions A + B and C + D and one to implement the additions E + F and A + B. / 8-16

17 Example 8-12 Design Compiler analyzes common subexpressions during the resource sharing phase of the compile command and considers area costs and timing characteristics. To turn off the sharing of common subexpressions for the current design, enter the following command: dc_shell> set_share_cse false The default is true. The HDL Compiler parser does not identify common subexpressions unless you use parentheses or write them in the same order. For example, the two equations in Example 8-12 use the common subexpression A + B. Unidentified Common Subexpressions Y = A + B + C; Z = D + A + B; The parser does not recognize A + Bas a common subexpression, because it parses the second equation as (D + A) + B. You can force the parser to recognize the common subexpression by rewriting the second assignment statement as Z <= A + B + D; or Z <= D + (A + B); Note: You do not have to rewrite the assignment statement, because Design Compiler recognizes common subexpressions automatically. / 8-17

18 Example 8-13 Using Operator Bit-Width Efficiently You can improve circuits by using operators more carefully. In Example 8-13, the adder sums the 8-bit value of a with the lower 4 bits of temp. Although temp is declared as an 8-bit value, the upper 4 bits of temp are always 0, so only the lower 4 bits of temp are needed for the addition. You can simplify the addition by changing temp to temp [3:0], as shown in Example Now, instead of using eight full adders to perform the addition, four full adders are used for the lower 4 bits and four half adders are used for the upper 4 bits. This yields a significant savings in circuit area. More Efficient Use of Operators module all (a,b,y); input [7:0] a,b; output [8:0] y; function [8:0] add_lt_10; input [7:0] a,b; reg [7:0] temp; begin if (b < 10) temp = b; else temp = 10; add_lt_10 = a + temp [3:0]; // use [3:0] for temp function assign y = add_lt_10(a,b); module / 8-18

19 Example 8-14 Using State Information When you build finite state machines, you can often specify a constant value of a signal in a particular state. You can write your Verilog description so that Design Compiler produces a more efficient circuit. Example 8-14 shows the Verilog description of a simple finite state machine. A Simple Finite State Machine module machine (x, clock, current_state, z); input x, clock; output [1:0] current_state; output z; reg [1:0] current_state; reg z; /* Redeclared as reg so they can be assigned to in always statements. By default, ports are wires and cannot be assigned to in always */ reg [1:0] next_state; reg previous_z; parameter [1:0] set0 = 0, hold0 = 1, set1 = 2; (x or current_state) begin case (current_state) //synopsys full_case /* declared full_case to avoid extraneous latches */ set0: begin z = 0 ; //set z to 0 next_state = hold0; hold0: begin / 8-19

20 z = previous_z; //hold value of z if (x == 0) next_state = hold0; else next_state = set1; set1: begin z = 1; //set z to 1 next_state = set0; case (posedge clock) begin current_state = next_state; previous_z = z; module In the state hold0, the output z retains its value from the previous state. To synthesize this circuit, a flip-flop is inserted to hold the state previous_z. However, you can make some assertions about the value of z. In the state hold0, the value of z is always 0. This can be deduced from the fact that the state hold0 is entered only from the state set0, where z is always assigned the value 0. Example 8-15 shows how the Verilog description can be changed to use this assertion, resulting in a simpler circuit (because the flip-flop for previous_z is not required). The changed line is shown in bold. / 8-20

21 Example 8-15 Better Implementation of a Finite State Machine module machine (x, clock, current_state, z); input x, clock; output [1:0]current_state; output z; reg [1:0] current_state; reg z; /* Redeclared as reg so they can be assigned to in always statements. By default, ports are wires and cannot be assigned to in always */ reg [1:0] next_state; parameter [1:0] set0 = 0, hold0 = 1, set1 = 2; (x or current_state) begin case (current_state) //synopsys full_case /* declared full_case to avoid extraneous latches */ set0: begin z = 0 ; //set z to 0 next_state = hold0; hold0: begin z = 0; //hold z at 0 if (x == 0) next_state = hold0; else next_state = set1; set1: begin z = 1; //set z to 1 next_state = set0; case / 8-21

22 (posedge clock) begin current_state = next_state; module Describing State Machines You can use an implicit state style or an explicit state style to describe a state machine. In the implicit state style, a clock edge (negedge or posedge) signals a transition in the circuit from one state to another. In the explicit state style, you use a constant declaration to assign a value to all states. Each state and its transition to the next state are defined under the case statement. Use the implicit state style to describe a single flow of control through a circuit (where each state in the state machine can be reached only from one other state). Use the explicit state style to describe operations such as synchronous resets. Example 8-16 shows a description of a circuit that sums data over three clock cycles. The circuit has a single flow of control, so the implicit style is preferable. / 8-22

23 Example 8-16 Summing Three Cycles of Data in the Implicit State Style (Preferred) module sum3 ( data, clk, total ); input [7:0] data; input clk; output [7:0] total; reg total; always (posedge clk) total = (posedge clk) total = total + (posedge clk) total = total + data; module Note: With the implicit state style, you must use the same clock phase (either posedge or negedge) for each event expression. Implicit states can be updated only if they are controlled by a single clock phase. Example 8-17 shows a description of the same circuit in the explicit state style. This circuit description requires more lines of code than Example 8-16 does, although HDL Compiler synthesizes the same circuit for both descriptions. / 8-23

24 Example 8-17 Summing Three Cycles of Data in the Explicit State Style (Not Advisable) module sum3 ( data, clk, total ); input [7:0] data; input clk; output [7:0] total; reg total; reg [1:0] state; parameter S0 = 0, S1 = 1, S2 = 2; (posedge clk) begin case (state) S0: begin total = data; state = S1; S1: begin total = total + data; state = S2; default : begin total = total + data; state = S0; case module Example 8-18 shows a description of the same circuit with a synchronous reset added. This example is coded in the explicit state style. Notice that the reset operation is addressed once before the case statement. / 8-24

25 Example 8-18 Synchronous Reset Explicit State Style (Preferred) module SUM3 ( data, clk, total, reset ); input [7:0] data; input clk, reset; output [7:0] total; reg total; reg [1:0] state; parameter S0 = 0, S1 = 1, S2 = 2; (posedge clk) begin if (reset) state = S0; else case (state) S0: begin total = data; state = S1; S1: begin total = total + data; state = S2; default : begin total = total + data; state = S0; case; module Example 8-19 shows how to describe the same function in the implicit state style. This style is not as efficient for describing synchronous resets. In this case, the reset operation has to be addressed for every statement. / 8-25

26 Example 8-19 Synchronous Reset Implicit State Style (Not Advisable) module SUM3 ( data, clk, total, reset ); input [7:0] data; input clk, reset; output [7:0] total; reg total; always begin: (posedge clk) if (reset) begin total = 8 b0; disable reset_label; else total = (posedge clk) if (reset) begin total = 8 b0; disable reset_label; else total = total + data; (posedge clk) if (reset) begin total = 8 b0; disable reset_label; else total = total + data; / 8-26

27 Example 8-20 Minimizing Registers In an always block that is triggered by a clock edge, every variable that has a value assigned has its value held in a flip-flop. Organize your Verilog description so you build only as many registers as you need. Example 8-20 shows a description where extra registers are implied. Inefficient Circuit Description With Six Implied Registers module count (clock, reset, and_bits, or_bits, xor_bits); input clock, reset; output and_bits, or_bits, xor_bits; reg and_bits, or_bits, xor_bits; reg [2:0] count; clock) begin if (reset) count = 0; else count = count + 1; and_bits = & count; or_bits = count; xor_bits = ^ count; module This description implies the use of six flip-flops: three to hold the values of count and one each to hold and_bits, or_bits, and xor_bits. However, the values of the outputs and_bits, or_bits, and xor_bits dep solely on the value of count. Because count is registered, there is no reason to register the three outputs. The synthesized circuit is shown in Figure / 8-27

28 Figure 8-11 Synthesized Circuit With Six Implied Registers To avoid implying extra registers, you can assign the outputs from within an asynchronous always block. Example 8-21 shows the same logic described with two always blocks, one synchronous and one asynchronous, which separate registered or sequential logic from combinational logic. This technique is useful for describing finite state machines. Signal assignments in the synchronous always block are registered. Signal assignments in the asynchronous always block are not. Therefore, this version of the design uses three fewer flipflops than the version in Example / 8-28

29 Example 8-21 Circuit With Three Implied Registers module count (clock, reset, and_bits, or_bits, xor_bits); input clock, reset; output and_bits, or_bits, xor_bits; reg and_bits, or_bits, xor_bits; reg [2:0] count; clock) begin//synchronous if (reset) count = 0; else count = count + 1; begin//asynchronous and_bits = & count; or_bits = count; xor_bits = ^ count; module The more efficient version of the circuit is shown in Figure Figure 8-12 Synthesized Circuit With Three Implied Registers / 8-29

30 Separating Sequential and Combinational Assignments To compute values synchronously and store them in flip-flops, set up an always block with a signal edge trigger. To let other values change asynchronously, make a separate always block with no signal edge trigger. Put the assignments you want clocked in the always block with the signal edge trigger and the other assignments in the other always block. This technique is used for creating Mealy machines, such as the one in Example Note that out changes asynchronously with in1 or in2. / 8-30

31 Example 8-22 Mealy Machine module mealy (in1, in2, clk, reset, out); input in1, in2, clk, reset; output out; reg current_state, next_state, out; clk or negedge reset) // state vector flip-flops (sequential) if (!reset) current_state = 0; else current_state = next_state; or in2 or current_state) // output and state vector decode (combinational) case (current_state) 0: begin next_state = 1; out = 1 b0; 1: if (in1) begin case next_state = 1 b0; out = in2; else begin next_state = 1 b1; out =!in2; module The schematic for this circuit is shown in Figure / 8-31

32 Figure 8-13 Mealy Machine Schematic / 8-32

33 Design Compiler Optimization After HDL Compiler translates your design description, you then use Design Compiler to optimize the HDL description and synthesize the design. Chapter 10, Design Compiler Interface, describes how to use Design Compiler to read HDL descriptions through HDL Compiler. For a complete description of the Design Compiler compile command, see the Design Compiler documentation. For the syntax of Design Compiler commands, see the Synopsys man pages. The Design Compiler commands set_flatten and set_structure set flatten and structure attributes for the compiler. Flattening reduces a design s logical structure to a set of two-level (and/or) logic equations. Structuring attempts to find common factors in the translated design s set of logic equations. Don t Care Inference You can greatly reduce circuit area by using don t care values. To use a don t care value in your design, create an enumerated type for the don t care value. Don t care values are best used as default assignments to variables. You can assign a don t care value to a variable at the beginning of a module, in the default section of a case statement, or in the else section of an if statement. To take advantage of don t care values during synthesis, use the Design Compiler command set_flatten. For information on embedding this command in your description, see Embedding Constraints and Attributes on page / 8-33

34 Limitations of Using Don t Care Values In some cases, using don t care values as default assignments can cause these problems: Don t care values create a greater potential for mismatches between simulation and synthesis. Defaults for variables can hide mistakes in the Verilog code. For example, you might assign a default don t care value to VAR. If you later assign a value to VAR, expecting VAR to be a don t care value, you might have overlooked an intervening condition under which VAR is assigned. Therefore, when you assign a value to a variable (or signal) that contains a don t care value, make sure that the variable (or signal) is really a don t care value under those conditions. Note that assignment to an x is interpreted as a don t care value. Differences Between Simulation and Synthesis Don t care values are treated differently in simulation and in synthesis, and there can be a mismatch between the two. To a simulator, a don t care is a distinct value, different from a 1 or a 0. In synthesis, however, a don t care becomes a 0 or a 1 (and hardware is built that treats the don t care value as either a 0 or a 1). Whenever a comparison is made with a variable whose value is don t care, simulation and synthesis can differ. Therefore, the safest way to use don t care values is to Assign don t care values only to output ports Make sure that the design never reads output ports / 8-34

35 These guidelines guarantee that when you simulate within the scope of the design, the only difference between simulation and synthesis occurs when the simulator indicates that an output is a don t care value. If you use don t care values internally to a design, expressions Design Compiler compares with don t care values (X) are synthesized as though values are not equal to X. For example, if A == X then... is synthesized as if FALSE then... If you use expressions comparing values with X, pre-synthesis and post-synthesis simulation results might not agree. For this reason, HDL Compiler issues the following warning: Warning: A partial don t-care value was read in routine test line 24 in file test.v This may cause simulation to disagree with synthesis. (HDL-171) Propagating Constants Constant propagation is the compile-time evaluation of expressions that contain constants. HDL Compiler uses constant propagation to reduce the amount of hardware required to implement complex operators. Therefore, when you know that a variable is a constant, / 8-35

36 specify it as a constant. For example, a + operator with a constant of 1 as one of its arguments causes an incrementer, rather than a general adder, to be built. If both arguments of an operator are constants, no hardware is constructed, because HDL Compiler can calculate the expression s value and insert it directly into the circuit. Comparators and shifters also benefit from constant propagation. When you shift a vector by a constant, the implementation requires only a reordering (rewiring) of bits, so no logic is needed. Synthesis Issues The next two sections describe feedback paths and latches that result from ambiguities in signal or variable assignments, and asynchronous behavior. Feedback Paths and Latches Sometimes your Verilog source can imply combinational feedback paths or latches in synthesized logic. This happens when a signal or a variable in a combinational logic block (an always block without a posedge or negedge clock statement) is not fully specified. A variable or signal is fully specified when it is assigned under all possible conditions. Synthesizing Asynchronous Designs In a synchronous design, all registers use the same clock signal. That clock signal must be a primary input to the design. A synchronous design has no combinational feedback paths, one-shots, or delay lines. Synchronous designs perform the same function regardless of / 8-36

37 Example 8-23 the clock rate, as long as the rate is slow enough to allow signals to propagate all the way through the combinational logic between registers. Synopsys synthesis tools offer limited support for asynchronous designs. The most common way to produce asynchronous logic in Verilog is to use gated clocks on registers. If you use asynchronous design techniques, synthesis and simulation results might not agree. Because Design Compiler does not issue warning messages for asynchronous designs, you are responsible for verifying the correctness of your circuit. The following examples show two approaches to the same counter design: Example 8-23 is synchronous, and Example 8-24 is asynchronous. Fully Synchronous Counter Design module COUNT (RESET, ENABLE, CLK, Z); input RESET, ENABLE, CLK; output [2:0] Z; reg [2:0] Z; (posedge CLK) begin if (RESET) begin Z = 1 b0; else if (ENABLE == 1 b1) begin if (Z == 3 d7) begin Z = 1 b0; else begin Z = Z + 1 b1; module / 8-37

38 Example 8-24 Asynchronous Counter Design module COUNT (RESET, ENABLE, CLK, Z); input RESET, ENABLE, CLK; output [2:0] Z; reg [2:0] Z; wire GATED_CLK = CLK & ENABLE; (posedge GATED_CLK or posedge RESET) begin if (RESET) begin Z = 1 b0; else begin if (Z == 3 d7) begin Z = 1 b0; else begin Z = Z + 1 b1; module The asynchronous version of the design uses two asynchronous design techniques. The first technique is to enable the counter by ANDing the clock with the enable line. The second technique is to use an asynchronous reset. These techniques work if the proper timing relationships exist between the asynchronous control lines (ENABLE and RESET) and the clock (CLK) and if the control lines are glitch-free. Some forms of asynchronous behavior are not supported. For example, you might expect the following circuit description of a one-shot signal generator to generate three inverters (an inverting delay line) and a NAND gate. X = A ~& (~(~(~ A))); / 8-38

39 However, this circuit description is optimized to X = A ~& (~ A); then X = 1; Designing for Overall Efficiency The efficiency of a synthesized design deps primarily on how you describe its component structure. The next two sections explain how to describe random logic and how to share complex operators. Example 8-25 Describing Random Logic You can describe random logic with many different shorthand Verilog expressions. HDL Compiler often generates the same optimized logic for equivalent expressions, so your description style for random logic does not affect the efficiency of the circuit. Example 8-25 shows four groups of statements that are equivalent. (Assume that a, b, and c are 4-bit variables.) HDL Compiler creates the same optimized logic in all four cases. c = a & b; Equivalent Statements c[3:0] = a[3:0] & b[3:0]; c[3] = a[3] & b[3]; c[2] = a[2] & b[2]; c[1] = a[1] & b[1]; c[0] = a[0] & b[0]; for (i = 0; i <= 3; i = i + 1) c[i] = a[i] & b[i]; / 8-39

40 Sharing Complex Operators You can use automatic resource sharing to share most operators. However, some complex operators can be shared only if you rewrite your source description more efficiently. These operators are Noncomputable array index Function call Shifter Example 8-26 shows a circuit description that creates more functional units than necessary when automatic resource sharing is turned off. / 8-40

41 Example 8-26 Inefficient Circuit Description With Two Array Indexes module rs(a, i, j, c, y, z); input [7:0] a; input [2:0] i,j; input c; output y, z; reg y, z; or i or j or c) begin z=0; y=0; if(c) begin z = a[i]; else begin y = a[j]; module The schematic for this code description is shown in Figure / 8-41

42 Figure 8-14 Circuit Schematic With Two Array Indexes You can rewrite the circuit description in Example 8-26 so that it contains only one array index, as shown in Example / 8-42

43 Example 8-27 Efficient Circuit Description With One Array Index module rs1(a, i, j, c, y, z); input [7:0] a; input [2:0] i,j; input c; output y, z; reg y, z; reg [3:0] index; reg temp; or i or j or c) begin if(c) begin index = i; else begin index = j; temp = a[index]; z=0; y=0; if(c) begin z = temp; else begin y = temp; module / 8-43

44 The circuit description in Example 8-27 is more efficient than the one in Example 8-26 because it uses a temporary register, temp, to store the value evaluated in the if statement. The resulting schematic is shown in Figure Figure 8-15 Circuit Schematic With One Array Index / 8-44

45 Consider resource sharing whenever you use a complex operation more than once. Complex operations include adders, multipliers, shifters (only when shifting by a variable amount), comparators, and most user-defined functions. If you use automatic resource allocation, adders, subtracters, and comparators can be shared. Chapter 7, Resource Sharing, covers these topics in detail. / 8-45

46 / 8-46

10 Writing Circuit Descriptions

10 Writing Circuit Descriptions 10 Writing Circuit Descriptions You can generally use several different, but logically equivalent, VHDL descriptions to describe a circuit. To understand the interaction between VHDL Compiler and Design

More information

Modeling Combinational Logic 3

Modeling Combinational Logic 3 3 Modeling Combinational Logic 3 There are two general classes of logic circuits: Combinational The value of the output deps only on the values of the input signals. Sequential The value of the output

More information

Why Should I Learn This Language? VLSI HDL. Verilog-2

Why Should I Learn This Language? VLSI HDL. Verilog-2 Verilog Why Should I Learn This Language? VLSI HDL Verilog-2 Different Levels of Abstraction Algorithmic the function of the system RTL the data flow the control signals the storage element and clock Gate

More information

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1

FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital

More information

Digital Design with FPGAs. By Neeraj Kulkarni

Digital Design with FPGAs. By Neeraj Kulkarni Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic

More information

Recommended Design Techniques for ECE241 Project Franjo Plavec Department of Electrical and Computer Engineering University of Toronto

Recommended Design Techniques for ECE241 Project Franjo Plavec Department of Electrical and Computer Engineering University of Toronto Recommed Design Techniques for ECE241 Project Franjo Plavec Department of Electrical and Computer Engineering University of Toronto DISCLAIMER: The information contained in this document does NOT contain

More information

Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23

Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23 98-1 Under-Graduate Project Synthesis of Combinational Logic Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23 What is synthesis? Outline Behavior Description for Synthesis Write Efficient HDL

More information

Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1

Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis. Spring 2007 Lec #8 -- HW Synthesis 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for best synthesis Spring 2007 Lec #8 -- HW Synthesis 1 Logic Synthesis Verilog and VHDL started out

More information

Synthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis

Synthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis Synthesis of Language Constructs 1 Nets Nets declared to be input or output ports are retained Internal nets may be eliminated due to logic optimization User may force a net to exist trireg, tri0, tri1

More information

EECS 270 Verilog Reference: Sequential Logic

EECS 270 Verilog Reference: Sequential Logic 1 Introduction EECS 270 Verilog Reference: Sequential Logic In the first few EECS 270 labs, your designs were based solely on combinational logic, which is logic that deps only on its current inputs. However,

More information

Verilog for Synthesis Ing. Pullini Antonio

Verilog for Synthesis Ing. Pullini Antonio Verilog for Synthesis Ing. Pullini Antonio antonio.pullini@epfl.ch Outline Introduction to Verilog HDL Describing combinational logic Inference of basic combinational blocks Describing sequential circuits

More information

Lecture 15: System Modeling and Verilog

Lecture 15: System Modeling and Verilog Lecture 15: System Modeling and Verilog Slides courtesy of Deming Chen Intro. VLSI System Design Outline Outline Modeling Digital Systems Introduction to Verilog HDL Use of Verilog HDL in Synthesis Reading

More information

CSE140L: Components and Design Techniques for Digital Systems Lab

CSE140L: Components and Design Techniques for Digital Systems Lab CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Announcements & Outline Lab 4 due; demo signup times listed on the cse140l site Check

More information

Lecture 3. Behavioral Modeling Sequential Circuits. Registers Counters Finite State Machines

Lecture 3. Behavioral Modeling Sequential Circuits. Registers Counters Finite State Machines Lecture 3 Behavioral Modeling Sequential Circuits Registers Counters Finite State Machines Behavioral Modeling Behavioral Modeling Behavioral descriptions use the keyword always, followed by optional event

More information

Verilog Tutorial. Introduction. T. A.: Hsueh-Yi Lin. 2008/3/12 VLSI Digital Signal Processing 2

Verilog Tutorial. Introduction. T. A.: Hsueh-Yi Lin. 2008/3/12 VLSI Digital Signal Processing 2 Verilog Tutorial T. A.: Hsueh-Yi Lin Introduction 2008/3/12 VLSI Digital Signal Processing 2 Verilog: A common language for industry HDL is a common way for hardware design Verilog VHDL Verilog is widely

More information

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences

MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences Introductory Digital Systems Lab (6.111) uiz - Spring 2004 Prof. Anantha Chandrakasan Student Name: Problem

More information

CSE140L: Components and Design

CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab Tajana Simunic Rosing Source: Vahid, Katz, Culler 1 Grade distribution: 70% Labs 35% Lab 4 30% Lab 3 20% Lab 2 15% Lab 1 30% Final exam

More information

EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis

EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150 - Lec05-verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State

More information

Lecture 32: SystemVerilog

Lecture 32: SystemVerilog Lecture 32: SystemVerilog Outline SystemVerilog module adder(input logic [31:0] a, input logic [31:0] b, output logic [31:0] y); assign y = a + b; Note that the inputs and outputs are 32-bit busses. 17:

More information

ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog

ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7

More information

Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University

Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register

More information

HDL Compiler Directives 7

HDL Compiler Directives 7 7 HDL Compiler Directives 7 Directives are a special case of regular comments and are ignored by the Verilog HDL simulator HDL Compiler directives begin, like all other Verilog comments, with the characters

More information

Logic Synthesis. EECS150 - Digital Design Lecture 6 - Synthesis

Logic Synthesis. EECS150 - Digital Design Lecture 6 - Synthesis Logic Synthesis Verilog and VHDL started out as simulation languages, but quickly people wrote programs to automatically convert Verilog code into low-level circuit descriptions (netlists). EECS150 - Digital

More information

Combinational Circuit Design

Combinational Circuit Design Modeling Combinational Circuits with Verilog Prof. Chien-Nan Liu TEL: 3-42275 ext:34534 Email: jimmy@ee.ncu.edu.tw 3- Combinational Circuit Design Outputs are functions of inputs inputs Combinational Circuit

More information

CSCB58 - Lab 3. Prelab /3 Part I (in-lab) /2 Part II (in-lab) /2 TOTAL /8

CSCB58 - Lab 3. Prelab /3 Part I (in-lab) /2 Part II (in-lab) /2 TOTAL /8 CSCB58 - Lab 3 Latches, Flip-flops, and Registers Learning Objectives The purpose of this exercise is to investigate the fundamental synchronous logic elements: latches, flip-flops, and registers. Prelab

More information

EEL 4783: HDL in Digital System Design

EEL 4783: HDL in Digital System Design EEL 4783: HDL in Digital System Design Lecture 15: Logic Synthesis with Verilog Prof. Mingjie Lin 1 Verilog Synthesis Synthesis vs. Compilation Descriptions mapped to hardware Verilog design patterns for

More information

In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified.

In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified. 1 In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified. I will also introduce the idea of a testbench as part of a design specification.

More information

Verilog for High Performance

Verilog for High Performance Verilog for High Performance Course Description This course provides all necessary theoretical and practical know-how to write synthesizable HDL code through Verilog standard language. The course goes

More information

ECE 551: Digital System *

ECE 551: Digital System * ECE 551: Digital System * Design & Synthesis Lecture Set 5 5.1: Verilog Behavioral Model for Finite State Machines (FSMs) 5.2: Verilog Simulation I/O and 2001 Standard (In Separate File) 3/4/2003 1 Explicit

More information

Topics. Midterm Finish Chapter 7

Topics. Midterm Finish Chapter 7 Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory

More information

Topics. Midterm Finish Chapter 7

Topics. Midterm Finish Chapter 7 Lecture 9 Topics Midterm Finish Chapter 7 Xilinx FPGAs Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice

More information

N-input EX-NOR gate. N-output inverter. N-input NOR gate

N-input EX-NOR gate. N-output inverter. N-input NOR gate Hardware Description Language HDL Introduction HDL is a hardware description language used to design and document electronic systems. HDL allows designers to design at various levels of abstraction. It

More information

CS429: Computer Organization and Architecture

CS429: Computer Organization and Architecture CS429: Computer Organization and Architecture Dr. Bill Young Department of Computer Sciences University of Texas at Austin Last updated: January 2, 2018 at 11:23 CS429 Slideset 5: 1 Topics of this Slideset

More information

VHDL for Synthesis. Course Description. Course Duration. Goals

VHDL for Synthesis. Course Description. Course Duration. Goals VHDL for Synthesis Course Description This course provides all necessary theoretical and practical know how to write an efficient synthesizable HDL code through VHDL standard language. The course goes

More information

Synthesis - Concepts and Applications

Synthesis - Concepts and Applications Synthesis - Concepts and Applications 李昆忠國立成功大學電機系 06-2757575 X 62371 kjlee@mail.ncku.edu.tw VLSI TEST LAB. NCKU-EE KJLEE Synthesis and Optimization Behavioral synthesis RTL Synthesis Logic optimization

More information

Finite-State Machine (FSM) Design

Finite-State Machine (FSM) Design 1 Finite-State Machine (FSM) Design FSMs, an important category of sequential circuits, are used frequently in designing digital systems. From the daily used electronic machines to the complex digital

More information

Verilog Sequential Logic. Verilog for Synthesis Rev C (module 3 and 4)

Verilog Sequential Logic. Verilog for Synthesis Rev C (module 3 and 4) Verilog Sequential Logic Verilog for Synthesis Rev C (module 3 and 4) Jim Duckworth, WPI 1 Sequential Logic Module 3 Latches and Flip-Flops Implemented by using signals in always statements with edge-triggered

More information

Quick Introduction to SystemVerilog: Sequental Logic

Quick Introduction to SystemVerilog: Sequental Logic ! Quick Introduction to SystemVerilog: Sequental Logic Lecture L3 8-545 Advanced Digital Design ECE Department Many elements Don Thomas, 24, used with permission with credit to G. Larson Today Quick synopsis

More information

Sequential Logic Design

Sequential Logic Design Sequential Logic Design Design of Digital Circuits 2017 Srdjan Capkun Onur Mutlu (Guest starring: Frank K. Gürkaynak and Aanjhan Ranganathan) http://www.syssec.ethz.ch/education/digitaltechnik_17 Adapted

More information

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign

a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign I hope you have completed Part 1 of the Experiment. This lecture leads you to Part 2 of the experiment and hopefully helps you with your progress to Part 2. It covers a number of topics: 1. How do we specify

More information

EE 231 Fall EE 231 Homework 8 Due October 20, 2010

EE 231 Fall EE 231 Homework 8 Due October 20, 2010 EE 231 Homework 8 Due October 20, 20 1. Consider the circuit below. It has three inputs (x and clock), and one output (z). At reset, the circuit starts with the outputs of all flip-flops at 0. x z J Q

More information

v HDL Compiler for Verilog Reference Manual Resource Sharing 7

v HDL Compiler for Verilog Reference Manual Resource Sharing 7 7 Resource Sharing 7 Resource sharing is the assignment of similar Verilog operations (for example, +) to a common netlist cell. Netlist cells are the resources they are equivalent to built hardware. Resource

More information

Chap 6 Introduction to HDL (d)

Chap 6 Introduction to HDL (d) Design with Verilog Chap 6 Introduction to HDL (d) Credit to: MD Rizal Othman Faculty of Electrical & Electronics Engineering Universiti Malaysia Pahang Ext: 6036 VERILOG HDL Basic Unit A module Module

More information

Verilog For Synthesis

Verilog For Synthesis Coding with always @(...) Coding with always @(...) always This is separate from the @(...) command. In C procedures are executed when called. In Verilog procedures are executed continuously by default.

More information

TOPIC : Verilog Synthesis examples. Module 4.3 : Verilog synthesis

TOPIC : Verilog Synthesis examples. Module 4.3 : Verilog synthesis TOPIC : Verilog Synthesis examples Module 4.3 : Verilog synthesis Example : 4-bit magnitude comptarator Discuss synthesis of a 4-bit magnitude comparator to understand each step in the synthesis flow.

More information

DIGITAL SYSTEM DESIGN

DIGITAL SYSTEM DESIGN DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1 Name: Registration No: Roll No: Semester:

More information

Verilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering

Verilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering VERILOG FUNDAMENTALS HDLs HISTORY HOW FPGA & VERILOG ARE RELATED CODING IN VERILOG HDLs HISTORY HDL HARDWARE DESCRIPTION LANGUAGE

More information

ECE 4514 Digital Design II. Spring Lecture 15: FSM-based Control

ECE 4514 Digital Design II. Spring Lecture 15: FSM-based Control ECE 4514 Digital Design II Lecture 15: FSM-based Control A Design Lecture Overview Finite State Machines Verilog Mapping: one, two, three always blocks State Encoding User-defined or tool-defined State

More information

EECS150 - Digital Design Lecture 4 - Verilog Introduction. Outline

EECS150 - Digital Design Lecture 4 - Verilog Introduction. Outline EECS150 - Digital Design Lecture 4 - Verilog Introduction Feb 3, 2009 John Wawrzynek Spring 2009 EECS150 - Lec05-Verilog Page 1 Outline Background and History of Hardware Description Brief Introduction

More information

CS6710 Tool Suite. Verilog is the Key Tool

CS6710 Tool Suite. Verilog is the Key Tool CS6710 Tool Suite Verilog-XL Behavioral Verilog Your Library Cadence SOC Encounter Synopsys Synthesis Structural Verilog Circuit Layout CSI Verilog-XL AutoRouter Cadence Virtuoso Layout LVS Layout-XL Cadence

More information

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>

Chapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1> Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building

More information

Modeling Synchronous Logic Circuits. Debdeep Mukhopadhyay IIT Madras

Modeling Synchronous Logic Circuits. Debdeep Mukhopadhyay IIT Madras Modeling Synchronous Logic Circuits Debdeep Mukhopadhyay IIT Madras Basic Sequential Circuits A combinational circuit produces output solely depending on the current input. But a sequential circuit remembers

More information

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010 Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 5- Chapter 5 :: Digital Building Blocks Digital Design and Computer Architecture David Money Harris and Sarah

More information

8 Register, Multiplexer and

8 Register, Multiplexer and 8 Register, Multiplexer and Three-State Inference HDL Compiler can infer Registers (latches and flip flops) Multiplexers Three state gates This chapter discusses methods of inferring different types of

More information

Graduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date:

Graduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date: Design of Datapath Controllers and Sequential Logic Lecturer: Date: 2009.03.18 ACCESS IC LAB Sequential Circuit Model & Timing Parameters ACCESS IC LAB Combinational Logic Review Combinational logic circuits

More information

EECS150 - Digital Design Lecture 10 Logic Synthesis

EECS150 - Digital Design Lecture 10 Logic Synthesis EECS150 - Digital Design Lecture 10 Logic Synthesis February 13, 2003 John Wawrzynek Spring 2003 EECS150 Lec8-synthesis Page 1 Logic Synthesis Verilog and VHDL started out as simulation languages, but

More information

EECS150 - Digital Design Lecture 10 Logic Synthesis

EECS150 - Digital Design Lecture 10 Logic Synthesis EECS150 - Digital Design Lecture 10 Logic Synthesis September 26, 2002 John Wawrzynek Fall 2002 EECS150 Lec10-synthesis Page 1 Logic Synthesis Verilog and VHDL stated out as simulation languages, but quickly

More information

Graduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date:

Graduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date: Synthesizable Coding of Verilog Lecturer: Date: 2009.03.18 ACCESS IC LAB Outline Basic concepts of logic synthesis Synthesizable Verilog coding subset Verilog coding practices Coding for readability Coding

More information

Digital Design with SystemVerilog

Digital Design with SystemVerilog Digital Design with SystemVerilog Prof. Stephen A. Edwards Columbia University Spring 25 Synchronous Digital Design Combinational Logic Sequential Logic Summary of Modeling Styles Testbenches Why HDLs?

More information

Nonblocking Assignments in Verilog Synthesis; Coding Styles That Kill!

Nonblocking Assignments in Verilog Synthesis; Coding Styles That Kill! Nonblocking Assignments in Verilog Synthesis; Coding Styles That Kill! by Cliff Cummings Sunburst Design, Inc. Abstract -------- One of the most misunderstood constructs in the Verilog language is the

More information

St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad

St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad St.MARTIN S ENGINEERING COLLEGE Dhulapally, Secunderabad-500 014 Subject: Digital Design Using Verilog Hdl Class : ECE-II Group A (Short Answer Questions) UNIT-I 1 Define verilog HDL? 2 List levels of

More information

Amrita Vishwa Vidyapeetham. EC429 VLSI System Design Answer Key

Amrita Vishwa Vidyapeetham. EC429 VLSI System Design Answer Key Time: Two Hours Amrita Vishwa Vidyapeetham B.Tech Second Assessment March 2013 Eighth Semester Electrical and Electronics Engineering EC429 VLSI System Design Answer Key Answer all Questions Roll No: Maximum:

More information

Chapter 5 Registers & Counters

Chapter 5 Registers & Counters University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 5 Registers & Counters Originals by: Charles R. Kime Modified for course

More information

CS6710 Tool Suite. Verilog is the Key Tool. Verilog as HDL (AHT) Verilog has a Split Personality. Quick Review. Synthesis

CS6710 Tool Suite. Verilog is the Key Tool. Verilog as HDL (AHT) Verilog has a Split Personality. Quick Review. Synthesis CS6710 Tool Suite Verilog is the Key Tool Verilog-XL Behavioral Verilog Your Library AutoRouter Cadence SOC Encounter Cadence Virtuoso Layout Synopsys Synthesis Circuit Layout CSI LVS Layout-XL Structural

More information

Topics of this Slideset. CS429: Computer Organization and Architecture. Digital Signals. Truth Tables. Logic Design

Topics of this Slideset. CS429: Computer Organization and Architecture. Digital Signals. Truth Tables. Logic Design Topics of this Slideset CS429: Computer Organization and rchitecture Dr. Bill Young Department of Computer Science University of Texas at ustin Last updated: July 5, 2018 at 11:55 To execute a program

More information

Combinational Logic II

Combinational Logic II Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic

More information

Verilog Lecture Gandhi Puvvada, USC always statements, Coding a Flip-Flop. blocking and non-blocking assignments. Copyright 2008 Gandhi Puvvada 1

Verilog Lecture Gandhi Puvvada, USC always statements, Coding a Flip-Flop. blocking and non-blocking assignments. Copyright 2008 Gandhi Puvvada 1 EE201L and EE560 Verilog Lecture by Gandhi Puvvada, USC always statements, t t Coding a Flip-Flop Counters, Basics of Data Path, blocking and non-blocking assignments Copyright 2008 Gandhi Puvvada 1 always

More information

ECE 4514 Digital Design II. Spring Lecture 13: Logic Synthesis

ECE 4514 Digital Design II. Spring Lecture 13: Logic Synthesis ECE 4514 Digital Design II A Tools/Methods Lecture Second half of Digital Design II 9 10-Mar-08 L13 (T) Logic Synthesis PJ2 13-Mar-08 L14 (D) FPGA Technology 10 18-Mar-08 No Class (Instructor on Conference)

More information

Digital Integrated Circuits

Digital Integrated Circuits Digital Integrated Circuits Lecture 4 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University BCD TO EXCESS-3 CODE CONVERTER 0100 0101 +0011 +0011 0111 1000 LSB received first Chung

More information

Working With Design Files 3

Working With Design Files 3 3 Working With Design Files 3 Designs are stored in design files, which are ASCII files containing a description of one or more designs. Design files must have unique names. Each design in a design file

More information

Course Topics - Outline

Course Topics - Outline Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 Behavioral modeling B Lecture 7

More information

Veriolog Overview. CS/EE 3710 Fall 2010

Veriolog Overview. CS/EE 3710 Fall 2010 Veriolog Overview CS/EE 3710 Fall 2010 Hardware Description Languages HDL Designed to be an alternative to schematics for describing hardware systems Two main survivors VHDL Commissioned by DOD Based on

More information

Nikhil Gupta. FPGA Challenge Takneek 2012

Nikhil Gupta. FPGA Challenge Takneek 2012 Nikhil Gupta FPGA Challenge Takneek 2012 RECAP FPGA Field Programmable Gate Array Matrix of logic gates Can be configured in any way by the user Codes for FPGA are executed in parallel Configured using

More information

Introduction to Verilog HDL. Verilog 1

Introduction to Verilog HDL. Verilog 1 Introduction to HDL Hardware Description Language (HDL) High-Level Programming Language Special constructs to model microelectronic circuits Describe the operation of a circuit at various levels of abstraction

More information

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation

A Verilog Primer. An Overview of Verilog for Digital Design and Simulation A Verilog Primer An Overview of Verilog for Digital Design and Simulation John Wright Vighnesh Iyer Department of Electrical Engineering and Computer Sciences College of Engineering, University of California,

More information

A Brief Introduction to Verilog Hardware Definition Language (HDL)

A Brief Introduction to Verilog Hardware Definition Language (HDL) www.realdigital.org A Brief Introduction to Verilog Hardware Definition Language (HDL) Forward Verilog is a Hardware Description language (HDL) that is used to define the structure and/or behavior of digital

More information

Advanced Digital Design with the Verilog HDL

Advanced Digital Design with the Verilog HDL Copyright 2001, 2003 MD Ciletti 1 Advanced Digital Design with the Verilog HDL M. D. Ciletti Department of Electrical and Computer Engineering University of Colorado Colorado Springs, Colorado ciletti@vlsic.uccs.edu

More information

ECE 353 Lab 4. Verilog Review. Professor Daniel Holcomb UMass Amherst Fall 2017

ECE 353 Lab 4. Verilog Review. Professor Daniel Holcomb UMass Amherst Fall 2017 ECE 353 Lab 4 Verilog Review Professor Daniel Holcomb UMass Amherst Fall 2017 What You Will Do In Lab 4 Design and implement a serial MIDI receiver Hardware in an Altera Complex Programmable Logic Device

More information

Federal Urdu University of Arts, Science and Technology, Islamabad VLSI SYSTEM DESIGN. Prepared By: Engr. Yousaf Hameed.

Federal Urdu University of Arts, Science and Technology, Islamabad VLSI SYSTEM DESIGN. Prepared By: Engr. Yousaf Hameed. VLSI SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING VLSI System Design 1 LAB 01 Schematic Introduction to DSCH and

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems

More information

Programming with HDLs

Programming with HDLs Programming with HDLs Paul Chow February 11, 2008 1 Introduction The purpose of this document is to encourage the proper approach or mindset for programming in a hardware description language (HDL), particularly

More information

Testbenches for Sequential Circuits... also, Components

Testbenches for Sequential Circuits... also, Components ! Testbenches for Sequential Circuits... also, Components Lecture L04 18-545 Advanced Digital Design ECE Department Many elements Don Thomas, 2014, used with permission with credit to G. Larson State Transition

More information

Synthesis of Combinational and Sequential Circuits with Verilog

Synthesis of Combinational and Sequential Circuits with Verilog Synthesis of Combinational and Sequential Circuits with Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two

More information

ECE 341 Midterm Exam

ECE 341 Midterm Exam ECE 341 Midterm Exam Time allowed: 75 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (8 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a) A

More information

FSM Components. FSM Description. HDL Coding Methods. Chapter 7: HDL Coding Techniques

FSM Components. FSM Description. HDL Coding Methods. Chapter 7: HDL Coding Techniques FSM Components XST features: Specific inference capabilities for synchronous Finite State Machine (FSM) components. Built-in FSM encoding strategies to accommodate your optimization goals. You may also

More information

ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL. Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS

ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL. Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS Note: Closed book no notes or other material allowed apart from the one

More information

Digital Design (VIMIAA01) Introduction to the Verilog HDL

Digital Design (VIMIAA01) Introduction to the Verilog HDL BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS FACULTY OF ELECTRICAL ENGINEERING AND INFORMATICS DEPARTMENT OF MEASUREMENT AND INFORMATION SYSTEMS Digital Design (VIMIAA01) Introduction to the Verilog

More information

Synthesizable Verilog

Synthesizable Verilog Synthesizable Verilog Courtesy of Dr. Edwards@Columbia, and Dr. Franzon@NCSU http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Design Methodology Structure and Function (Behavior) of a Design HDL

More information

EE178 Lecture Verilog FSM Examples. Eric Crabill SJSU / Xilinx Fall 2007

EE178 Lecture Verilog FSM Examples. Eric Crabill SJSU / Xilinx Fall 2007 EE178 Lecture Verilog FSM Examples Eric Crabill SJSU / Xilinx Fall 2007 In Real-time Object-oriented Modeling, Bran Selic and Garth Gullekson view a state machine as: A set of input events A set of output

More information

MLR Institute of Technology

MLR Institute of Technology MLR Institute of Technology Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad 500 043 Course Name Course Code Class Branch ELECTRONICS AND COMMUNICATIONS ENGINEERING QUESTION BANK : DIGITAL DESIGN

More information

HDLs and SystemVerilog. Digital Computer Design

HDLs and SystemVerilog. Digital Computer Design HDLs and SystemVerilog Digital Computer Design Logic Arrays Gates can be organized into regular arrays. If the connections are made programmable, these logic arrays can be configured to perform any function

More information

In this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and

In this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and In this lecture, we will focus on two very important digital building blocks: counters which can either count events or keep time information, and shift registers, which is most useful in conversion between

More information

Verilog 1 - Fundamentals

Verilog 1 - Fundamentals Verilog 1 - Fundamentals FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2],

More information

Parallel versus serial execution

Parallel versus serial execution Parallel versus serial execution F assign statements are implicitly parallel Ì = means continuous assignment Ì Example assign E = A & D; assign A = B & C; Ì A and E change if B changes F always blocks

More information

Techniques for Digital Systems Lab. Verilog HDL. Tajana Simunic Rosing. Source: Eric Crabill, Xilinx

Techniques for Digital Systems Lab. Verilog HDL. Tajana Simunic Rosing. Source: Eric Crabill, Xilinx CSE140L: Components and Design Techniques for Digital Systems Lab Verilog HDL Tajana Simunic Rosing Source: Eric Crabill, Xilinx 1 More complex behavioral model module life (n0, n1, n2, n3, n4, n5, n6,

More information

CSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx

CSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx CSE140L: Components and Design Techniques for Digital Systems Lab Verilog HDL Instructor: Mohsen Imani UC San Diego Source: Eric Crabill, Xilinx 1 Hardware description languages Used to describe & model

More information

L5: Simple Sequential Circuits and Verilog

L5: Simple Sequential Circuits and Verilog L5: Simple Sequential Circuits and Verilog Courtesy of Rex Min. Used with permission. 1 Key Points from L4 (Sequential Blocks) Classification: Latch: level sensitive (positive latch passes input to output

More information

Chapter 4 :: Topics. Introduction. SystemVerilog. Hardware description language (HDL): allows designer to specify logic function only.

Chapter 4 :: Topics. Introduction. SystemVerilog. Hardware description language (HDL): allows designer to specify logic function only. Chapter 4 :: Hardware Description Languages Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Chapter 4 :: Topics Introduction Combinational Logic Structural Modeling Sequential

More information

Lecture 12 VHDL Synthesis

Lecture 12 VHDL Synthesis CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?

More information