Verilog Tutorial (Structure, Test)
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1 Digital Circuit Design and Language Verilog Tutorial (Structure, Test) Chang, Ik Joon Kyunghee University
2 Hierarchical Design Top-down Design Methodology Bottom-up Design Methodology
3 Module START Example) END
4 Module (Example: Full Adder) Module becomes a template for instantiation
5 Port Declaration and Assignment Rule Input, Output and Inout declaration can be regarded as wire To store data in output, the output port should be declared as reg
6 Abstraction Modeling Levels in Verilog Behavioral or Algorithmic Level Most upper level Similar to C language Dataflow Level Showing the data flow between registers Gate Level Describing Gate-to-Gate connection Switch Level RTL Level Design = Behavioral + Dataflow
7 Abstraction Modeling Levels in Verilog Behavioral or Algorithmic Level Most upper level Similar to C language Dataflow Level Showing the data flow between registers Gate Level Describing Gate-to-Gate connection Switch Level RTL Level Design = Behavioral + Dataflow
8 Gate Level Modeling
9 Built-in Primitive Built-in Primitive Combinational logic Tri State MOS Gates CMOS Gates Bi-Directional Gates Pull Gates and nand or nor xor xnor buf not bufif0 bufif1 notif0 notif1 nmos pmos rnmos rpmos cmos rcmos tran tranif0 tranif1 rtran rtranif0 rtranif1 pullup pulldown
10 User-Defined Primitive (UDP) primitive UDP_02467 (D, A, B, C); output D; input A, B, C; // Truth table for D = f (A, B, C) =??(0, 2, 4, 6, 7); table // A B C : D : 1; : 0; : 1; : 0; : 1; : 0; : 1; : 1; endtable endprimitive Truth table UDP can be defined using a truth table
11 Example: Gate Level Modeling - butif0 #(5) a1(out, i1, i2) // rising, falling and turn-off delay = 5 - butif0 #(4, 6) a1(out, i1, i2) // rising=4, falling=6, turn-off=4 - burif0 #(3,4,5) a1(out, i1, i2) // rising=4, falling=6, turn-off=5 - and #(4:5:6) a1(out, i1, i2) // min : typical : max delay = 4 : 5 : 6 Delay operator will be removed in logic synthesis For logic simulation, min/typical/max delay should be selected
12 Gate-level Example: 4-bit RCA module half_adder (output S, C, input x, y); xor (S, x, y); and (C, x, y); endmodule module full_adder (output S, C, input x, y, z); wire S1, C1, C2; half_adder HA1 (S1, C1, x, y); half_adder HA2 (S, C2, S1, z); or G1 (C, C2, C1); endmodule module ripple_carry_4_bit_adder ( output [3: 0] Sum, output C4, input [3:0] A, B, input C0); wire C1, C2, C3; // Intermediate carries // Instantiate chain of full adders full_adder FA0 (Sum[0], C1, A[0], B[0], C0), FA1 (Sum[1], C2, A[1], B[1], C1), FA2 (Sum[2], C3, A[2], B[2], C2), FA3 (Sum[3], C4, A[3], B[3], C3); endmodule
13 Abstraction Modeling Levels in Verilog Behavioral or Algorithmic Level Most upper level Similar to C language Dataflow Level Showing the data flow between registers Gate Level Describing Gate-to-Gate connection Switch Level RTL Level Design = Behavioral + Dataflow
14 Dataflow Level Modeling Using Continuous Assignment or Operator Continuous Assignment ex. assign #10 out = in1 & in2 //delay 10 t.u. for input change
15 Example: Dataflow Level Modeling // 4:1 Multiplexer using dataflow level modeling module mux4_to_1 (out, in, sel); // I/O port declaration output out; input [3:0] in; input [1:0] sel; wire out; wire [3:0] in; wire [1:0] sel; assign out = (~sel[1] & ~sel[0] & in[0]) (~sel[1] & sel[0] & in[1]) (sel[1] & ~sel[0] & in[2]) (sel[1] & sel[0] & in[3]) endmodule
16 Abstraction Modeling Levels in Verilog Behavioral or Algorithmic Level Most upper level Similar to C language Dataflow Level Showing the data flow between registers Gate Level Describing Gate-to-Gate connection Switch Level RTL Level Design = Behavioral + Dataflow
17 Procedure What is procedure? Can be expressed in two types of statements: initial or always Every procedure is executed in parallel initial statement They execute only once always statement They execute forever until the simulation is completed Module can contain any number of procedures
18 Procedure: initial statement
19 Procedure: always statement
20 Procedural Assignment
21 Example: Blocking vs. Non-blocking Assignment (posedge clock) a = b; (posedge clock) b = a; What is the first? Race Condition (posedge clock) a <= b; (posedge clock) b <= a; (posedge clock) begin temp_a = a; temp_b = b; a = temp_b; b = temp_a; end
22 Timing Control: Delay-based (using # )
23 Example: Delay-based Timing Control In the following Verilog Code, tell the simulation time of (a), (b), (c), (d) and (e). reg x, y, p, a, b, c, d; initial begin initial end #30 c = 1 b0; // (e) x = 1 b0; #5 y = 1 b1; // (a) fork #10 p = x; //(b) begin #20 a = x; // (c) b = y; // (d) end join
24 Timing Control: Event-based ) event OR control regular event control (positive-edge) regular event control (negative-edge) What is named event control?
25 Timing Control: Level-sensitive (using wait ) always wait (count_table) #20 count = count + 1; If count_table ==1, increase count by 20 t.u. else, no action
26 Procedural Statement: If
27 Procedural Statement: Case
28 Procedural Statement: For
29 Procedural Statement: While
30 Procedural Statement: Repeat
31 Procedural Statement: Forever
32 Test Bench For Functional Verification instantiation 32 Test bench : Applying stimulus to test HDL and observe its response In the test module, no input and output reg-inputs, wire-output
33 Test Bench for Functional Verification 2-to-1 Multiplexer
34 System Task
35 Display and Monitor String Format
36 HDL Example: D-Latch & D Flip-Flop
37 HDL Example: T and J-K Flip-Flop T Flip-Flop using D Flip-Flop J-K Flip-Flop using D Flip-Flop
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