# Computer Arithmetic andveriloghdl Fundamentals

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1 Computer Arithmetic andveriloghdl Fundamentals Joseph Cavanagh Santa Clara University California, USA ( r ec) CRC Press vf J TayiorS«. Francis Group ^"*" "^ Boca Raton London New York CRC Press is an imprint of the Taylor & Francis Group, an tnforma business

2 CONTENTS Preface xv Chapter 1 Number Systems and Number Representations Number Systems Binary Number System Octal Number System Decimal Number System Number Representations Sign Magnitude Diminished-Radix Complement Radix Complement Problems 22 Chapter 2 Logic Design Fundamentals Boolean Algebra Minimization Techniques Algebraic Minimization Karnaugh Maps Quine-McCluskey Algorithm Combinational Logic Multiplexers Decoders Encoders Comparators Sequential Logic Counters Moore Machines Mealy Machines Problems 84 Chapter 3 Introduction to Verilog HDL Built-in Primitives User-Defined Primitives Dataflow Modeling Continuous Assignment Behavioral Modeling Initial Statement 129

5 x Contents 10.5 Multiplication Using Table Lookup Problems 528 Chapter 11 Decimal Division Restoring Division Version Restoring Division Version Division Using Table Lookup Problems 550 Chapter 12 Floating-Point Addition Floating-Point Format Biased Exponents Floating-Point Addition Overflow and Underflow General Floating-Point Organization Verilog HDL Implementation Problems 569 Chapter 13 Floating-Point Subtraction Numerical Examples Flowcharts Verilog HDL Implementations True Addition True Subtraction Version True Subtraction Version True Subtraction Version True Subtraction Version Problems 608 Chapter 14 Floating-Point Multiplication Double Bias Flowcharts Numerical Examples Verilog HDL Implementations Floating-Point Multiplication Version Floating-Point Multiplication Version Problems 631

6 Contents xi Chapter 15 Floating-Point Division Zero Bias Exponent Overflow/Underflow Flowcharts Numerical Examples Problems 646 Chapter 16 Additional Floating-Point Topics Rounding Methods Truncation Rounding Adder-Based Rounding Von Neumann Rounding Guard Bits Verilog HDL Implementations Adder-Based Rounding Using Memory Adder-Based Rounding Using Combinational Logic Adder-Based Rounding Using Behavioral Modeling Combined Truncation, Adder-Based, and von Neumann Rounding Problems 680 Chapter 17 Additional Topics in Computer Arithmetic Residue Checking Dataflow Modeling Structural Modeling Parity-Checked Shift Register Parity Prediction Condition Codes for Addition Logical and Algebraic Shifters Behavioral Modeling Structural Modeling Arithmetic and Logic Units Four-Function Arithmetic and Logic Unit Sixteen-Function Arithmetic and Logic Unit Count-Down Counter Shift Registers Parallel-In, Serial-Out Shift Register Serial-In, Serial-Out Shift Register 778

7 xii Contents Parallel-In, Serial-In, Serial-Out Shift Register Serial-In, Parallel-Out Shift Register Problems 795 Appendix A Verilog HDL Designs for Select Logic Functions 8 l A.l AND Gate 801 A.2 NAND Gate 806 A.3 OR Gate 809 A.4 NOR Gate 811 A.5 Exclusive-OR Function 814 A.6 Exclusive-NOR Function 818 A.7 Multiplexers 822 A.8 Decoders 825 A.9 Encoders 829 A.10 Priority Encoder 833 A.ll Binary-to-Gray Code Converter 836 A.12 Adder/Subtractor 843 Appendix В Event Queue 849 B.l Event Handling for Dataflow Assignments 849 B.2 Event Handling for Blocking Assignments 854 B.3 Event Handling for Nonblocking Assignments 857 B.4 Event Handling for Mixed Blocking and Nonblocking Assignments 861 Appendix С Verilog HDL Project Procedure 865 Appendix D Answers to Select Problems 867 Chapter 1 Number Systems and Number Representations 867 Chapter 2 Logic Design Fundamentals 869 Chapter 3 Introduction to Verilog HDL 873 Chapter 4 Fixed-Point Addition 883 Chapter 5 Fixed-Point Subtraction 887 Chapter 6 Fixed-Point Multiplication 891 Chapter 7 Fixed-Point Division 897 Chapter 8 Decimal Addition 903 Chapter 9 Decimal Subtraction 907

8 Contents xiii Chapter 10 Decimal Multiplication 908 Chapter 11 Decimal Division 912 Chapter 12 Floating-Point Addition 913 Chapter 13 Floating-Point Subtraction 915 Chapter 14 Floating-Point Multiplication 918 Chapter 15 Floating-Point Division 924 Chapter 16 Additional Floating-Point Topics 926 Chapter 17 Additional Topics in Computer Arithmetic 932 Index 943

### Digital Design. Verilo. and. Fundamentals. fit HDL. Joseph Cavanagh. CRC Press Taylor & Francis Group Boca Raton London New York

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COMPUTER ARITHMETIC 1. Addition and Subtraction of Unsigned Numbers The direct method of subtraction taught in elementary schools uses the borrowconcept. In this method we borrow a 1 from a higher significant

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ENEE 350 c C. B. Silio, Jan., 2010 FLOATING POINT REPRESENTATIONS It is assumed that the student is familiar with the discussion in Appendix B of the text by A. Tanenbaum, Structured Computer Organization,