Computer Arithmetic andveriloghdl Fundamentals


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1 Computer Arithmetic andveriloghdl Fundamentals Joseph Cavanagh Santa Clara University California, USA ( r ec) CRC Press vf J TayiorS«. Francis Group ^"*" "^ Boca Raton London New York CRC Press is an imprint of the Taylor & Francis Group, an tnforma business
2 CONTENTS Preface xv Chapter 1 Number Systems and Number Representations Number Systems Binary Number System Octal Number System Decimal Number System Number Representations Sign Magnitude DiminishedRadix Complement Radix Complement Problems 22 Chapter 2 Logic Design Fundamentals Boolean Algebra Minimization Techniques Algebraic Minimization Karnaugh Maps QuineMcCluskey Algorithm Combinational Logic Multiplexers Decoders Encoders Comparators Sequential Logic Counters Moore Machines Mealy Machines Problems 84 Chapter 3 Introduction to Verilog HDL Builtin Primitives UserDefined Primitives Dataflow Modeling Continuous Assignment Behavioral Modeling Initial Statement 129
3 viii Contents Always Statement Intrastatement Delay Interstatement Delay Blocking Assignments Nonblocking Assignments Conditional Statements Case Statement Loop Statements Structural Modeling Module Instantiation Design Examples Problems 179 Chapter 4 FixedPoint Addition RippleCarry Addition Carry Lookahead Addition CarrySave Addition MultipleBit Addition MultipleOperand Addition MemoryBased Addition CarrySelect Addition Serial Addition Problems 234 Chapter 5 FixedPoint Subtraction Twos Complement Subtraction RippleCarry Subtraction Carry Lookahead Addition/Subtraction Behavioral Addition/Subtraction Problems 271 Chapter 6 FixedPoint Multiplication Sequential AddShift Multiplication Sequential AddShift Multiplication Hardware Algorithm Sequential AddShift Multiplication Version Sequential AddShift Multiplication Version Booth Algorithm Multiplication BitPair Recoding Multiplication 304
4 Contents Chapter 7 Array Multiplication Table Lookup Multiplication MemoryBased Multiplication MultipleOperand Multiplication Problems FixedPoint Division Chapter 8 Sequential ShiftAdd/Subtract Restoring Division Restoring Division Version Restoring Division Version 2 Sequential ShiftAdd/Subtract Nonrestormg Division SRT Division SRT Division Using Table Lookup SRT Division Using the Case Statement Multiplicative Division Array Division Problems Decimal Addition Chapter 9 Addition with Sum Correction Addition Using Multiplexers Addition with MemoryBased Correction Addition with Biased Augend Problems Decimal Subtraction Chapter ix Subtraction Examples 464 TwoDecade Addition/Subtraction Unit for A+B and AB TwoDecade Addition/Subtraction Unit for A+B, AB, andba 481 Problems 491 Decimal Multiplication BinarytoBCD Conversion Multiplication Using Behavioral Modeling Multiplication Using Structural Modeling Multiplication Using Memory
5 x Contents 10.5 Multiplication Using Table Lookup Problems 528 Chapter 11 Decimal Division Restoring Division Version Restoring Division Version Division Using Table Lookup Problems 550 Chapter 12 FloatingPoint Addition FloatingPoint Format Biased Exponents FloatingPoint Addition Overflow and Underflow General FloatingPoint Organization Verilog HDL Implementation Problems 569 Chapter 13 FloatingPoint Subtraction Numerical Examples Flowcharts Verilog HDL Implementations True Addition True Subtraction Version True Subtraction Version True Subtraction Version True Subtraction Version Problems 608 Chapter 14 FloatingPoint Multiplication Double Bias Flowcharts Numerical Examples Verilog HDL Implementations FloatingPoint Multiplication Version FloatingPoint Multiplication Version Problems 631
6 Contents xi Chapter 15 FloatingPoint Division Zero Bias Exponent Overflow/Underflow Flowcharts Numerical Examples Problems 646 Chapter 16 Additional FloatingPoint Topics Rounding Methods Truncation Rounding AdderBased Rounding Von Neumann Rounding Guard Bits Verilog HDL Implementations AdderBased Rounding Using Memory AdderBased Rounding Using Combinational Logic AdderBased Rounding Using Behavioral Modeling Combined Truncation, AdderBased, and von Neumann Rounding Problems 680 Chapter 17 Additional Topics in Computer Arithmetic Residue Checking Dataflow Modeling Structural Modeling ParityChecked Shift Register Parity Prediction Condition Codes for Addition Logical and Algebraic Shifters Behavioral Modeling Structural Modeling Arithmetic and Logic Units FourFunction Arithmetic and Logic Unit SixteenFunction Arithmetic and Logic Unit CountDown Counter Shift Registers ParallelIn, SerialOut Shift Register SerialIn, SerialOut Shift Register 778
7 xii Contents ParallelIn, SerialIn, SerialOut Shift Register SerialIn, ParallelOut Shift Register Problems 795 Appendix A Verilog HDL Designs for Select Logic Functions 8 l A.l AND Gate 801 A.2 NAND Gate 806 A.3 OR Gate 809 A.4 NOR Gate 811 A.5 ExclusiveOR Function 814 A.6 ExclusiveNOR Function 818 A.7 Multiplexers 822 A.8 Decoders 825 A.9 Encoders 829 A.10 Priority Encoder 833 A.ll BinarytoGray Code Converter 836 A.12 Adder/Subtractor 843 Appendix В Event Queue 849 B.l Event Handling for Dataflow Assignments 849 B.2 Event Handling for Blocking Assignments 854 B.3 Event Handling for Nonblocking Assignments 857 B.4 Event Handling for Mixed Blocking and Nonblocking Assignments 861 Appendix С Verilog HDL Project Procedure 865 Appendix D Answers to Select Problems 867 Chapter 1 Number Systems and Number Representations 867 Chapter 2 Logic Design Fundamentals 869 Chapter 3 Introduction to Verilog HDL 873 Chapter 4 FixedPoint Addition 883 Chapter 5 FixedPoint Subtraction 887 Chapter 6 FixedPoint Multiplication 891 Chapter 7 FixedPoint Division 897 Chapter 8 Decimal Addition 903 Chapter 9 Decimal Subtraction 907
8 Contents xiii Chapter 10 Decimal Multiplication 908 Chapter 11 Decimal Division 912 Chapter 12 FloatingPoint Addition 913 Chapter 13 FloatingPoint Subtraction 915 Chapter 14 FloatingPoint Multiplication 918 Chapter 15 FloatingPoint Division 924 Chapter 16 Additional FloatingPoint Topics 926 Chapter 17 Additional Topics in Computer Arithmetic 932 Index 943
Digital Design. Verilo. and. Fundamentals. fit HDL. Joseph Cavanagh. CRC Press Taylor & Francis Group Boca Raton London New York
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