Digital Design. Verilo. and. Fundamentals. fit HDL. Joseph Cavanagh. CRC Press Taylor & Francis Group Boca Raton London New York


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1 Digital Design and Verilo fit HDL Fundamentals Joseph Cavanagh Santa Clara University California, USA CRC Press Taylor & Francis Group Boca Raton London New York CRC Press is an imprint of the Taylor & Francis Croup, an informa business
2 CONTENTS Chapter Number Systems, Number Representations, and Codes 1 Number Systems Binary Number System Octal Number System Decimal Number System Hexadecimal Number System Arithmetic Operations Conversion Between Radices 22 Number Representations Sign Magnitude 29 DiminishedRadix Complement 31 Radix Complement 34 Arithmetic Operations 38 Binary Codes Binary Weighted and Nonweighted Codes 59 BinarytoBCD Conversion 63 BCDtoBinary Conversion 64 Gray Code 65 Error Detection and Correction Codes Parity 68 Hamming Code 70 Cyclic Redundancy Check Code 72 Checksum 73 TwoOutOfFive Code 75 Horizontal and Vertical Parity Check 75 Serial Data Transmission 77 Problems 78 Chapter 2 Minimization of Switching Functions Boolean Algebra Algebraic Minimization Karnaugh Maps MapEntered Variables QuineMcCluskey Algorithm Petrick Algorithm Problems 128
3 Chapter 3 Combinational Logic Logic Primitive Gates WiredAND and WiredOR Operations ThreeState Logic Functionally Complete Gates Logic Macro Functions Multiplexers Decoders Encoders Comparators Analysis of Combinational Logic Synthesis of Combinational Logic Problems 223 Chapter 4 Combinational Logic Design UsingVerilogHDL BuiltIn Primitives UserDefined Primitives Defming a UserDefined Primitive Combinational UserDefined Primitives Dataflow Modeling Continuous Assignment Reduction Operators Conditional Operator Relational Operators Logical Operators Bitwise Operators Shift Operators Behavioral Modeling Initial Statement Always Statement Intrastatement Delay Interstatement Delay Blocking Assignments Nonblocking Assignments Conditional Statement Case Statement Loop Statements Tasks Functions Structural Modeling Module Instantiation Ports 379
4 Design Examples 383 Problems 412 Chapter 5 Computer Arithmetic FixedPoint Addition RippleCarry Addition Carry Lookahead Addition FixedPoint Subtraction FixedPoint Multiplication Sequential AddShift Booth Algorithm BitPair Recoding Array Multiplier FixedPoint Division Restoring Division Nonrestoring Division Decimal Addition Addition With Sum Correction Addition Using Multiplexers for Sum Correction Decimal Subtraction Decimal Multiplication Multiplication Using ReadOnly Memory Decimal Division Division Using Table Lookup FloatingPoint Arithmetic FloatingPoint Addition/Subtraction FloatingPoint Multiplication FloatingPoint Division Rounding Methods Problems 497 Chapter 6 Computer Arithmetic Design Using Verilog HDL FixedPoint Addition HighSpeed Füll Adder FourBit Ripple Adder Carry Lookahead Adder FixedPoint Subtraction FixedPoint Multiplication Booth Algorithm Array Multiplier 532
5 6.4 Decimal Addition BCD Addition With Sum Correction BCD Addition Using Multiplexers for Sum Correction Decimal Subtraction Problems 560 Chapter 7 Sequential Logic Analysis of Synchronous Sequential Machines Machine Alphabets Storage Elements Classes of Sequential Machines Methods of Analysis Analysis Examples Synthesis of Synchronous Sequential Machines Synthesis Procedure Synchronous Registers Synchronous Counters Moore Machines Mealy Machines Output Glitches Analysis of Asynchronous Sequential Machines FundamentalMode Model Methods of Analysis Hazards Oscillations Races Synthesis of Asynchronous Sequential Machines Synthesis Procedure Synthesis Examples Analysis of PulseMode Asynchronous Sequential Machines Analysis Procedure Synthesis of PulseMode Asynchronous Sequential Machines Synthesis Procedure Problems 722 Chapter 8 Sequential Logic Design Using Verilog HDL Synchronous Sequential Machines Asynchronous Sequential Machines PulseMode Asynchronous Sequential Machines Problems 808
6 Chapter 9 Programmable Logic Devices Programmable ReadOnly Memory Combinational Logic Sequential Logic Programmable Array Logic Combinational Logic Sequential Logic Programmable Logic Arrays Combinational Logic Sequential Logic FieldProgrammable Gate Arrays Problems 862 Chapter 10 Digital and Analog Conversion Operational Amplifier DigitaltoAnalog Conversion BinaryWeighted Resistor Network DigitaltoAnalog Converter R  2R Resistor Network DigitaltoAnalog Converter AnalogtoDigital Conversion Comparators Counter AnalogtoDigital Converter Successive Approximation AnalogtoDigital Converter Simultaneous Analogto Digital Converter Problems 894 Chapter 11 Magnetic Recording Fundamentals Return to Zero Nonreturn to Zero Nonreturn to Zero Inverted Frequency Modulation Phase Encoding Modified Frequency Modulation RunLength Limited GroupCoded Recording Peak Shift Write Precompensation Verti cal Recording Problems 915
7 Chapter 12 Additional Topics in Digital Design Functional Decomposition 922 Iterative Networks 941 Hamming Code 953 Cyclic Redundancy Check Code 967 Residue Checking 973 Parity Prediction 980 Condition Codes for Addition 984 Arithmetic and Logic Unit 987 Memory 1000 Problems 1006 Append ix A A.l A.2 A.3 A.4 Event Queue 1013 Event Handling for Dataflow Assignments 1013 Event Handling for Blocking Assignments 1018 Event Handling for Nonblocking Assignments 1021 Event Handling for Mixed Blocking and Nonblocking Assignments 1025 Appendix B Verilog Project Procedure 1029 Appendix C Answers to Select Problems 1031 Chapter 1 Number Systems, Number Representations, and Codes 1031 Chapter 2 Minimization of Switching Functions 1034 Chapter 3 Combinational Logic 1038 Chapter 4 Combinational Logic Design Using Verilog HDL 1043 Chapter 5 Computer Arithmetic 1065 Chapter 6 Computer Arithmetic Design Using Verilog HDL 1069 Chapter 7 Sequential Logic 1076 Chapter 8 Sequential Logic Design Using Verilog HDL 1086 Chapter 9 Programmable Logic Devices 1117 Chapter 10 Digital and Analog Conversion 1123 Chapter 11 Magnetic Recording Fundamentals 1125 Chapter 12 Additional Topics in Digital Design 1127 Index 1135
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