Lecture 3: Modeling in VHDL. EE 3610 Digital Systems
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1 EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL
2 VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware Other languages: Verilog, Verilog-AMS (Analog and Mixed Signal)
3 VHDL: Overview 3 Benefits Public Standard Technology and Process Independent Include technology via libraries Supports a variety of design methodologies Behavioral modeling Dataflow or RTL (Register Transfer Language) Modeling: We won t use it Structural or gate level modeling
4 VHDL: Overview 4 Model Mathematical Description of a physical device Simulation Analysis (automated) of a model given a set of inputs Digital Circuit Models Structural: defines sub-models and how they are interconnected (FFs, Gates, etc) Behavioral: defines the behavior of the circuit (no actual components)
5 HDL: Then 5 Originally designed for simulation only Start with behavioural models and slowly replace them with structural models Reduce these to FFs and Gates Try and Test
6 HDL: Now 6 Build behavioral models and Simulate Synthesize to net-list (generic) Fit to a device Simulate the new (wholly structural) model Try and test
7 Levels of Abstraction: Behavioral, Structural, Physical 7 S <=AB S Behavioral (Algorithms, Dataflow) Structural (Components, interconnections) Physical
8 Combinational Circuits 8 C<=A and B after 5 ns; E<=C or D after 5 ns; explicit declaration of delay to update the change 1) Suppose initial Values: A=1, B=C=D=E=0 2) At t=0 ns: B=1 3) At t=5 ns: C=1 4) At t=10 ns: E=1 5) If delay is not specified, then a minimum is assumed
9 Combinational Circuits 9 Concurrent Statements C<=A and B after 5 ns; E<=C or D after 5 ns; Order is not important E<=C or D after 5 ns; C<=A and B after 5 ns;
10 Combinational Circuits This statement causes a simulation error 10 CLK <= not CLK;
11 Combinational Circuits Repetition of Concurrent Statements CLK <= not CLK after 10 ns; 11 1) Implicit Loop 2) Toggles between 1 and 0 after updating the signal at every 10 ns 3) Will continue indefinitely
12 Combinational Circuits Concurrent Statements 12 1) Statements are executed simultaneously 2) D, E, F are updated at different times 3) Can specify different gate delays within cocurrent statements
13 VHDL: Elements Entity:-Description of interface consisting of the port list -The primary hardware abstraction in VHDL, -Analogous to a symbol in a block diagram. Architecture: Description of the function of the corresponding module. Process: Allows for a sequential execution of the assignments Configuration: Used for simulation purposes. Package: Hold the definition of commonly used data types, constants and subprograms. Library: -The logical name of a collection of compiled VHDL units (object code) -Mapped by the simulation or synthesis tools 13
14 VHDL: Example Code Write the code for the following circuit: 14
15 VHDL: Example Code 15 entity example is port (x1,x2,x3: in std_logic; f: out std_logic); end example; ARCHITECTURE logicfunc of example is begin -- Architecture statement region f <= (x1 AND x2) NOR (NOT x2 AND x3); end logicfunc; name defined by the user
16 Code Flow 16
17 Six Phases (1) Compilation: Code Flow Checks the code to see that the syntax and semantic rules are met, references to libraries are correct Outputs intermediate code to be used by Simulator (2) Elaboration: A driver is created for each signal Each driver holds the current value of signal and a queue of future signal values Ports are created for each component, memory storage is allocated, interconnection between port signals specified 17
18 Code Flow Six Phases (continued ) (3) Simulation: Simulator takes simulation commands Passage of time is simulated in discrete steps VHDL statements are executed and actions are scheduled Whenever a component input changes, the output is scheduled to change after specified delay or some delay After all inputs are processed, simulated time is advanced and counter is reset 18
19 Code Flow Six Phases (continued ) (4) Synthesis: Translate VHDL code to a circuit description Compilation and Elaboration: same as Simulation Usually Synthesis comes after Simulation List of required components and interconnections is produced (5) Implementation: Output of Synthesizer is used to implement the digital system using specific hardware, e.g. CPLD, FPGA, ASIC ASIC: masks may be generated CPLD/FPGA: generates bit-map 19
20 Code Flow (5) Implementation (continued ): TRANSLATE: converts the netlist generated from the synthesis process, into a form specific to the target device (e.g. Xilinx FPGA). MAP: translates the standard building blocks into the specific resources available in the target hardware PLACE & ROUTE: picks up where the MAP process leaves off by allocating specific resources (placing) and interconnecting (routing) the placed design, places and routes the design to the timing constraints Can perform a post-place and route simulation (6) Hardware: Binary programming file is generated (bitstream) and downloaded to the FPGA 20
21 Inside of a Bit File: Lab 0 Hexadecimal Format 21
22 SIDE NOTES: INSIDE THE FPGA 22
23 SIDE NOTES: INSIDE THE FPGA 23 CLB=Configurable Logic Block=4 Slices Slice=> two Look Up Table (LUT)s and two Flip Flops
![SIDE NOTES: LUT Implementation [1/2] LUT is implemented with small RAM Four input bits act as an address bus: select output bit based on four input bits addressing one of 16 stored](/docs-images/77/74980371/images/24-0.jpg "bits 24 Io I1 I2 I3 Out 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1")
24 SIDE NOTES: LUT Implementation [1/2] LUT is implemented with small RAM Four input bits act as an address bus: select output bit based on four input bits addressing one of 16 stored bits 24 Io I1 I2 I3 Out
25 16:1 MUX SIDE NOTES: LUT Implementation [2/2] 25 16:1 Addressable Shift Register
26 Example 1: Pin Assignments (Lab 0) NET "SW0" LOC = "L13"; NET "SW1" LOC = "L14"; 26 Set this signal (which is a port in the top level module) to pin L13 on the FPGA entity top is Port ( SW0 : in STD_LOGIC; SW1 : in STD_LOGIC; LED0 : out STD_LOGIC); end top; NET "LED0" LOC = "F12" IOSTANDARD = LVTTL SLEW = SLOW DRIVE = 8 ; Set input output standard to transistor-transistor logic, slew rate (rate of transition for each output), and current level to 8 ma
27 Example 2: 1-bit Full Adder Co = A B + A Ci + B Ci; S=A + B + Ci 27 entity FullAdder is port (A,B,Ci: in bit Co,S: out bit end FullAdder; architecture Eq of FullAdder is begin S <= A xor B xor Ci; Co <= (A and b) or (A and Ci) or (B and Ci); end Eq; Use ( )to specify order of precedence
28 Predefined Operators There are seven groups of predefined VHDL operators: Binary logical operators: and or nand nor xor xnor 2. Relational operators: = /= < <= > >= 3. Shifts operators: sll srl sla sra rol ror 4. Adding operators: + - &(concatenation) 5. Unary sign operators: Multiplying operators: * / mod rem 7. Miscellaneous operators: not abs **
29 Predefined Operators: Order of Precedence [1/2] Highest precedence first, left to right within same precedence group, use parenthesis to control order. Unary operators take an operand on the right. "result same" means the result is the same as the right operand. Binary operators take an operand on the left and right. "result same" means the result is the same as the left operand. 29 ** exponentiation, numeric ** integer, result numeric abs absolute value, abs numeric, result numeric not complement, not logic or boolean, result same * multiplication, numeric * numeric, result numeric / division, numeric / numeric, result numeric mod modulo, integer mod integer, result integer rem remainder, integer rem integer, result integer + unary plus, + numeric, result numeric - unary minus, - numeric, result numeric + addition, numeric + numeric, result numeric - subtraction, numeric - numeric, result numeric & concatenation, array or element & array or element, result array Reserved Words:
30 Predefined Operators: Order of Precedence [2/2] sll shift left logical, logical array sll integer, result same srl shift right logical, logical array srl integer, result same sla shift left arithmetic, logical array sla integer, result same sra shift right arithmetic, logical array sra integer, result same rol rotate left, logical array rol integer, result same ror rotate right, logical array ror integer, result same 30 = test for equality, result is boolean /= test for inequality, result is boolean < test for less than, result is boolean <= test for less than or equal, result is boolean > test for greater than, result is boolean >= test for greater than or equal, result is boolean and logical and, logical array or boolean, result is same or logical or, logical array or boolean, result is same nand logical complement of and, logical array or boolean, result is same nor logical complement of or, logical array or boolean, result is same xor logical exclusive or, logical array or boolean, result is same xnor logical complement of exclusive or,logical array or boolean, result is same Reserved Words:
31 Example 3: Priority of Operators Let A= 110, B= 111, C= , and D= (A & not B or C ror 2 and D)= Order: not, &, ror, or, and, = 1) not B = bit-by-bit complement 2) A & not B = concatenation 3) C ror 2 = rotate right 2 places 4) (A & not B) or (C ror 2) = bit-by-bit or 5) (A & not B or C ror 2) and D = bit-by-bit and 6) [(A & not B or C ror 2 and D) = ]=TRUE=1 --with parentheses the equality test is done last 31
32 Example 4: Concurrent Statement (4-bit mux) entity mux4 is port (I0, I1, I2, I3: in std_logic; Select: in std_logic_vector (1 downto 0); Y: out bit); end mux4; architecture dude of mux4 is begin Y <= I0 when select = 00 ; else I1 when select = 01 ; else I2 when select = 10 ; else I3; end dude; 32
33 4 bit Ripple Carry Adder
34 4 bit Ripple Carry Adder 4 bit Ripple Carry Adder with Hierarchical Design entity Adder4 is port (A,B: in bit_vector(3 downto 0); Ci: in bit --inputs S: out bit_vector(3 downto 0); Co: out bit--outputs end Adder4; architecture Structure of Adder4 is component FullAdder is port (X,Y,Cin: in bit --inputs Cout,Sum: out bit --outputs end component; Can create component declarations in a libary file signal C: bit_vector (3_downto 1); --C is internal signal begin ---create 4 copies of FullAdder FA0: FullAdder port map (A(0),B(0),Cin,C(1),S(0)); FA1: FullAdder port map (A(1),B(1),C(1),C(2),S(1)); FA2: FullAdder port map (A(2),B(2),C(2),C(3),S(2)); FA3: FullAdder port map (A(3),B(3),C(3),Co,S(3)); end Structure
35 4 bit Ripple Carry Adder entity Adder4 is port (A,B: in bit_vector(3 downto 0); Ci: in bit --inputs S: out bit_vector(3 downto 0); Co: out bit--outputs end Adder4; architecture Structure of Adder4 is component FullAdder is port (X,Y,Cin: in bit --inputs Cout,Sum: out bit --outputs end component; signal C: bit_vector (3_downto 1); --C is internal signal begin ---create 4 copies of FullAdder FA0: FullAdder port map (Y=>B(0), X=>A(0),Sum=>S(0), Cin=>Ci);. end Structure.. With named association order doesn't matter
36 VHDL: Common Mistakes Avoid Common Mistakes: [1] [2] VHDL Guides: [1] 36
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