# Mid-Term Exam Solutions

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1 CS/EE 26 Digital Computers: Organization and Logical Design Mid-Term Eam Solutions Jon Turner 3/3/3. (6 points) List all the minterms for the epression (B + A)C + AC + BC. Epanding the epression gives B C + AC + AC + BC = A B C + AB C + ABC + AB C + ABC + A BC All the minterms appear at right. Numerically, they are, 3, 4, 5, 6 and 7. List the materms for the epression. The missing minterms are and 2. These correspond to the two materms of the epression (A +B + C) and (A +B + C) 2. (5 points) Show that the following Boolean equation is true using algebraic simplification (not Karnaugh maps). Show your work. AB + BC + CD = (B + C)(B + D)(A + C + D) Epanding the right side gives (B + C)(B + D)(A + C + D) = (B + BC + BD+ CD)(A + C + D) = (B + CD)(A + C + D) = AB + BC + BD + (ACD + CD) = AB + BC + BD + CD = AB + BC + (BC D + BCD) + CD = AB + (BC + BC D) + (BCD + CD) = AB + BC + CD - -

2 3. (8 points) The attached simulation output is from an eecution of the simple processor introduced in section of the lecture notes. The instruction set for the processor appears below. Answer the following questions using the simulation output. What does the instruction stored at location C do? This instruction is A. It adds the content of memory location to the accumulator. What is the value of memory location at time 6 µs? 2 What is the value of the program counter at time 445 ns? f What is the value of memory location at time 7 µs? halt eecution negate the value in the ACC change the value of the ACC to 2 load the contents of memory location into the ACC 3 load the ACC from the memory location whose address is stored in memory location 4 store the value in the ACC in memory location 5 store the value in the ACC in the memory location whose address is stored in memory location 6 change the value of the PC to 7 change the value of the PC to if ACC = 8 change the value of the PC to if ACC > 9 change the value of the PC to if ACC < a add the value in memory location to the ACC - 2 -

3 /testbench/reset /testbench/mem_en /testbench/mem_rw /testbench/abus E /testbench/dbus A 2 7F 3 2 /testbench/clk /testbench/pc E D F /testbench/ireg A 7F 3 /testbench/iar 2 2 /testbench/acc 2 3 FFD FFF /testbench/alu FFD FFF 2 4 us 42 ns 44 ns 46 ns 48 ns 5 us 52 ns 54 ns 56 ns Entity:testbench Architecture:testbench_arch Date: Sun Mar 2 5:29: Central Standard Time 23 Row: Page:

4 /testbench/reset /testbench/mem_en /testbench/mem_rw /testbench/abus 2 9 A B C D E /testbench/dbus A 4 A /testbench/clk /testbench/pc 9 A B C D E /testbench/ireg 3 A 4 A 4 /testbench/iar 2 /testbench/acc FFF 22 /testbench/alu ns 6 us 62 ns 64 ns 66 ns 68 ns 7 us 72 ns 74 ns Entity:testbench Architecture:testbench_arch Date: Sun Mar 2 5:29: Central Standard Time 23 Row: 2 Page: 2

5 4. ( points) Draw a logic circuit using the smallest possible number of simple gates (AND, OR and inverters, only) for the logic epression UX + X(V + Z ) + (V + U)X Z. XZ UV UX + VX + V Z U X V Z How many transistors are required by a CMOS version of this circuit? Show how to improve it by using NAND and NOR gates. How many transistors does this version require? The circuit above requires 36 transistors if implemented directly in CMOS. The circuit shown below uses just 24 transistors. U X V Z 5. (8 points) Use a Karnaugh map to find the simplest sum-of-products epression for F(X,Y,Z) = Σm(,2,4), d(x,y,z) = Σm(3,6) X YZ X Y + X Z+ XZ Use a Karnaugh map to find the simplest product-of-sums epression for F(A,B,C,D) = Σm(,2,6,7,8,9,5), d(a,b,c,d) = Σm(3,4,5,) AB CD F = A C D + BC + ACD F = (A + C + D)(B +C)(A + C + D) - 3 -

6 6. (5 points) Show how to implement the function F(A,B,C,D) = Σm(,2,5,7,8,9,), d(a,b,c,d) = Σm(3,4,6,5) using an 8 input multipleor. ABCD F D D D ABC - 4 -

7 7. ( points) The circuit below shows a combinational circuit that implements a 5 bit version of the parallel pulse-parity function from design problem 2. What is the worst-case propagation delay for a 64 bit version of this circuit, using only simple gates with a delay of ns? (The worst-case propagation delay is the maimum time from when an input changes until all outputs reach their final value.) a a a 2 a 3 a 4 all in pp int all out all in pp int all out all in pp int all out all in pp int all out all in pp int all out 2 a i a i 3 4 all in all out pp in The worst-case delay is 63+4=67 ns. The circuit outlined below is a lookahead version of the same circuit. The boes represent a repeated sub-circuit. In the rightmost bo, fill in this circuit. What is the worst-case delay for a 64 bit version of this circuit, implemented using simple gates? a 4 a a2 3 a a The 64 bit version would have a delay of 6+3+6=5 ns

8 8. (5 points) The circuit shown below implements a ternary (base 3) half-adder. The pair of input bits (A_i,B_i) represents a single ternary digit (the bit pair represent the ternary digit, the bit pair represents the ternary digit and the bit pair represents the ternary digit 2). Similarly for the outputs (X_i,Y_i). We can build a ternary increment circuit by combining these ternary half-adder circuits together, in the same way as with a binary ripple-carry increment circuit. Suppose that the input presented to a ternary increment circuit with four ternary digits corresponds to the ternary value 22. What are the values of the nine output bits? Fill in your answer below the output signals listed below. Cout, (X_3, Y_3), (X_2, Y_2), (X_, Y_), (X_, Y_) C in A X B Y C A X B Y C A 2 X 2 B 2 Y 2 C 2 A 3 X 3 B 3 Y 3 C 3 =C out - 6 -

9 The partial VHDL module below implements a ternary increment circuit with 8 ternary digits. Complete the missing parts. Your VHDL should be complete and syntactically correct. library IEEE; use IEEE.STD_LOGIC_64.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ternaryinc is Port ( A, B : in std_logic_vector(7 downto ); Cin : in std_logic; X, Y : out std_logic_vector(7 downto ); Cout : out std_logic ); end ternaryinc; architecture arch of ternaryinc is signal C: std_logic_vector(7 downto ); begin process(a, B, Cin, C) begin X() <= (A() and (not Cin)) or (B() and Cin); Y() <= (B() and (not Cin)) or ((not A()) and (not B()) and Cin); C() <= A() and Cin; for i in to 7 loop X(i) <= (A(i) and (not C(i-))) or (B(i) and C(i-)); Y(i) <= (B(i) and (not C(i-))) or ((not A(i)) and (not B(i)) and C(i-)); C(i) <= A(i) and C(i-); end loop; Cout <= C(7); end process; end arch; - 7 -

10 9. ( points) The figure shown below is a state diagram for a sequential circuit with one input A and two outputs X and Y. Is this a Moore model circuit or a Mealy model circuit? Fill in the values in the net state table. It s a Moore model circuit. / / / S S A XY D D What are the net state equations for the circuit? D S S A D S S A D = S + S A + S A D = S A + S A - 8 -

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