Chap.3 3. Chap reduces the complexity required to represent the schematic diagram of a circuit Library


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1 3.1 Combinational Circuits 2 Chap 3. logic circuits for digital systems: combinational vs sequential Combinational Logic Design Combinational Circuit (Chap 3) outputs are determined by the present applied inputs performs an operation, which can be specified logically by a set of Boolean expressions Spring 2003 Sequential Circuit (Chap 4) logic gates + storage elements (called flipflops) outputs are a function of the inputs & bit values in the storage elements (state of storage elements is a function of previous inputs) output depends on the present values of inputs & past inputs 3.1 Combinational Circuits Design Topics 4 Combinational Circuit (Fig 3.1) Design Hierarchy consist of input/output variables, logic gates, & interconnections n inputs: 2 n possible combinations m outputs: circuit can be described by m Boolean expressions logic gate transforms binary information from input to outputs a circuit may be specified by a symbol showing inputs, outputs, & a description defining exactly how it operates ninputs moutputs a circuit is composed of logic gates that are interconnected (in terms of implementation) Combinational Circuit a single VLSI processor contains several million gates approach divide & conquer the circuit is broken up into pieces (blocks) Schematic: logic diagram Design Topics 6 primitive blocks: NAND gates predefined blocks leaves lower level of design hierarchy reusable blocks Instance Use of blocks Focus reusable blocks Hierarchical Design fundamental blocks predefined collection of interconnected gates 1. reduces the complexity required to represent the schematic diagram of a circuit Library 2. ends at a set of "leaves" (consisting of AND gates) elementary digital components 3. reuse of blocks
2 3.2 Design Topics 7 8 Functional Blocks predefined, reusable blocks that typically lie in the lower levels of logic design hierarchies provide functions that are broadly useful in digital design available for decades in MSI circuits TopDown Design functional blocks: Ch 5, Ch 6 (cf) bottom up ComputerAided Design Schematic Capture, Library HDL (hardware description language) Verification logic simulator Logic Synthesizer Physical area, delay HDL (hardware description languages) Deacribes hardware structure and behavior VHDL (Very High Speed Integrated Circuits Hardware Description Language) Verilog : Cadence Design Systems, Inc. Feature Programming Language Parallel operation contrary to conventional serial operation Structural description Alternative to schematic: lowlevel description Behavioral description highlevel description Logic Synthesis: RTL(Register transfer level) 9 Logic Synthesis 10 Sequence of Process Analysis Elaboration simulation initialization Testbench: describes H/W and S/W that applies input to the DUT(device under test) and analyzes the outputs for correctness. Logic Synthesis Translation Optimization technology mapping FPGA( field programmable gate array ) 3.3 Analysis Procedure for Combinational Circuit Determining the function that the circuit implements 1) make sure that the circuit is combinational, not sequential 11 no feedback or storage elements 2) obtain the output Boolean functions or the truth table & interpret the operation of the circuit Derivation of Boolean Functions to obtain the output Boolean functions from a logic diagram 1) label all gate outputs that are a function only of input variables or their complements & determine the Boolean functions for each gate 2) label the gates that are a function of input variables and previously labeled gates & find Boolean functions for each gate 3) repeat (2) until the outputs of the circuits are obtained Ex) 3.3 Analysis Procedure 4 inputs, A, B, C, D; 2 outputs, F 1, F 2 T 1 = B' C; T 2 = A' B T 3 = A + T 1 = A + B' C T 4 = T 2 D = (A' B) D = A'BD' +AD +B'D T 5 = T 2 + D = A'B + D So, F 2 = T 5 = T 2 + D = A'B + D F 1 = T 3 + T 4 = A + B'C + A'BD' +AD + B'D = A(1+D) + B'C + A BD' + B'D = A+A BD +B C+B D=A+BD +B C+B D 12
3 3.3 Analysis Procedure Analysis Procedure 14 Derivation of the Truth Table from the Logic Diagram Ex) binary adder a straightforward process 1) Determine no of input variables in the circuit For n inputs, list 2 n (0(2 n 1)) binary numbers 2) Label the outputs of selected gates 3) Obtain the truth table for the outputs of those gates 4) Proceed to obtain the truth table for the outputs of gates 3 inputs, X, Y, Z; 2 outputs C, S (00 ~ 11) C is 1 if XY, XZ, or YZ = 11; C is 0 otherwise 3.3 Analysis Procedure Design Procedure 16 Logic Simulation  ViewDraw & ViewTrace Procedure to design combinational circuits 1) Determine required number of inputs & outputs & assign a letter symbol to each 2) Derive the truth table 3) Obtain simplified Boolean functions for each output 4) Draw the logic diagram 5) Verify the correctness of the design Truth Table n input variables: 2 n binary numbers output functions give the exact definition of comb circuit. Output functions are simplified by method, such as algebraic manipulation, map method, computer programs 3.4 Design Procedure Design Procedure 18 Ex 3.1) Design a combinational circuit with 3 inputs and 1 output Output is 1 when input is less than 3(011), otherwise 0. Code Converter a circuit that translates info from one binary code to another Ex 3.2) BCD to Excess3 Code Converter Excess3 code: decimal digit + 3 desirable to implementing decimal subtraction (Don't care conditions!!)
4 3.4 Design Procedure Design Procedure 20 twolevel ANDOR logic diagram W = A + BC + BD = A + B(C + D) X = B'C + B'D + BC'D' = B'(C + D) + BC'D' Y = CD + C'D' = (C D)' Z = D' Logic Diagram 3.4 Design Procedure Decoders 22 Ex3.3) BCD to SevenSegment Decoder LED (light emitting diodes), or LCD (liquid crystal display) accept a decimal digit in BCD & generate the appropriate outputs Decoders a binary code of n bits represents 2 n distinct elements convert binary info of n coded inputs to 2 n (max) unique outputs outputs (a, b, c, d, e, f, g) 7 fourvariable maps ntomline decoders (m < 2 n ) generate 2 n (or fewer) minterms of n input variables 3to8line decoder (3 inputs & 8 outputs) 3.5 Decoders Decoders 24 Ex) binarytooctal conversion 2to4line decoder with enable input constructed with NAND instead of AND gates operates with comp outputs and comp enable E
5 3.5 Decoders Decoders 26 Decoder Expansion combine two or more small decoder w/ enable inputs form a larger decoder 3to8line decoder with two 2to4line decoders Combinational Circuit Implementation a decoder provides 2 n minterms of n input variables since Boolean functions are expressed as a sum of minterms, one can use a decoder(minterms) and OR(sum) gates ninputs, moutputs combi. logic : nx2 n decoder + mor gates Ex 3.4) a binary adder S(X,Y,Z) = Σ m(1,2,4,7); C(X,Y,Z) = Σ m(3,5,6,7) if A 2 =0, upper is enabled; if A 2 =1, lower is enabled. 3.6 Encoders Encoders 28 perform the inverse operation of a decoder 2 n (or less) input lines and n output lines Octaltobinary encoder implemented with 3 4input OR gates only one input can be active at any given time more than 2 inputs are active undefined! priority for inputs Priority Encoder 2 or more inputs are equal to 1 at the same time, an input with the highest priority will take precedence valid A 0 = D 1 + D 3 + D 5 + D 7 ; A 1 = D 2 + D 3 + D 6 + D 7 ; A 2 = D 4 + D 5 + D 6 + D 7 ; 3.6 Encoders Multiplexers(MUX) 30 selects binary information from one of many input lines, and directs it to a single output line Normally, 2 n input lines and n selection variables 4to1line multiplexer A 1 = D 2 + D 3 V = D 0 + D 1 + D 2 + D 3 A 0 = D 3 + D 1 D 2 ' selection inputs called data selector or MUX 2 n to1line multiplexer is constructed from nto2 n decoder by adding 2 n input lines
6 Multiplexers 32 Quadruple 2to1 Line Multiplexer common selection & enable lines to select multibits 3.7 Multiplexers Multiplexers 34 Combinational Circuit Implementation a decoder can be used to implement Boolean Functions by employing external OR gates the minterms of a function are generated in a multiplexer by the circuit associated with the selection inputs n variables with a multiplexer with n1 selection inputs Ex) F(X,Y,Z) = m(1,2,6,7)  implemented with a 4to1line multiplexer first (n1) variables > selection inputs remaining 1 variable > data inputs  any Boolean function of n variables can be implemented with a multiplexer with n1 selection inputs and 2 n1 data inputs 3.7 Multiplexers Multiplexers 36 Ex) F(A,B,C,D) = Σ m(1,3,4,11,12,13,14,15) Demultiplexer perform the inverse operation of a multiplexer receives information from a single line and transmits it to one of 2 n possible output lines 1to4line demultiplexer the input E has a path to all 4 outputs, selected by two selection lines S1 and S0 a decoder with enable input is referred to as decoder /demultiplexer identical to a 2to4 line decoder with enable input
7 3.8 Binary Adders Binary Adders 38 Arithmetic Circuit Addition of 3 binary inputs, 'Full Adder' a combinational circuit for arithmetic operations such as addition, subtraction, multiplication, and division with binary numbers or decimal numbers in a binary code Addition of 2 binary inputs, 'Half Adder 0+0=0, 0+1=1, 1+0=1, 1+1 = 10 S = X'Y + XY' = X Y; C = XY Logic Diagram of Full Adder Binary Ripple Carry Adder 3.8 Binary Adders sum of two nbit binary numbers in parallel 39 c s i s i s HA c x i HA y c c i + 1 i 40 4bit parallel adder A = 1011, B = 0011 (a) Block diagram c i s i x i y i c i + 1 (b) Detailed diagram A decomposed implementation of the fulladder circuit 3.8 Binary Adders 41 x 1 y 1 x 0 y 0 42 Carry Lookahead Adder The ripple carry adder has a long circuit delay the longest delay: (2n + 2) gate delay Carry Lookahead Adder reduced delay at the price of complex hardware c 2 g 1 p 1 c 1 g 0 p 0 c 0 a new logic hierarchy PFA : partial full adder P i : propagate function P i = A i B i G i : generate function Stage 1 Stage 0 G i = A i B i s 1 s 0 A ripplecarry adder with generate/propagate signals
8 Gate Delay of 4bits 4 Ripple Carry Adder 43 x 1 y 1 x 0 y 0 44 x 0 y 0 g 1 p 1 g 0 p 0 c 0 c 2 c 1 C1 : 3 gate delay S0 : 2 C2 : 5 S1 : 4 C3 : 7 S2 : 6 C4 : 9 S3 : 8 In general, for n, Cn : 2n+1 Sn1 : 2n s 1 Figure 5.16 The first two stages of a carrylookahead adder s Binary Adders Development of Carry Lookahead Adder C 2 =G 1 +P1(G0+P0C0) C 3 =G2+P2(G1+P1(G0+P0C0)) =G2+P2G1+P2P1G0+P2P1P0C0 Group propagation ftn P 03 =P3P2P1P0 Group generate ftn G 03 =G3+P3G2+P3P2G1+P3P2P1G x y x 15 8 y 15 8 x 7 0 y 7 0 c 32 Block c 24 c Block c 8 Block 0 c 0 s s 15 8 s 7 0 A hierarchical carrylookahead adder with ripplecarry between blocks
9 x y x 15 8 y 15 8 x 7 0 y Binary Subtraction 50 P 3 G 3 Block 3 s c 24 P 1 G 1 Block 1 s 15 8 P 0 G 0 Block 0 s 7 0 c 0 Subtraction MN= M=Minuend N=Subtrahend 1 c 32 c 16 Secondlevel lookahead A hierarchical carrylookahead adder c 8 a borrow occurs into the most significant position(end borrow occurs) M  N ==> M  N + 2 n ==> 2 n (MN + 2 n ) = N  M 1) Subtract the subtrahend N from the minuend M 2) If no end borrow occurs, then M > N 3) If an end borrow occurs, then NM is subtracted from 2 n & minus sign is appended to the result Subtraction of a binary number from 2 n "2's complement form" 3.9 Binary Subtraction Binary Subtraction 52 Ex 3.5) Complements 2 types: radix complement: r's complement diminished radix complement: (r1)'s complement 2's & 1's for binary numbers 10's & 9's for decimal numbers 1's complement of N (binary number): (2 n 1) N 1's comp of ==> 's comp of ==> Binary Subtraction Binary Subtraction 54 2's complement of N: 2 n  N for N!= 0, 0 for N = 0 add 1 to the 1's complement 2's comp of ==> ==> leaving all least significant 0's and the first unchanged then replacing 1's with 0's, 0's with 1's in all other higher significant bits 2's comp of ==> 's complement of N is 2 n N & the complement of the complement is 2 n (2 n N) = N Subtraction with Complements (M  N) 1) add 2's comp of the subtrahend N to the minuend M M + (2 n N) = M  N + 2 n 2) if M > N, the end carry is discarded 3) if M < N, the result is 2 n (N M) no end carry take the 2's complement of the sum & place a minus sign, i.e. ( 2 n (2 n (NM))) avoid overflow problem to accomodate the sum
10 3.10 Binary AdderSubtractors Binary AdderSubtractors 56 Signed Binary Numbers sign bit(=msb, most significant bit) 0 for positive numbers 1 for negative numbers 9 (=1001) using 8 bits signedmagnitude representation: signed 1's complement representation: signed 2's complement representation: A  B = A + (B) in 2's complement form with exclusiveor gate (B 0=B; B 1=B') adder if S = 0; subtractor if S = 1 4bit signed binary number (positive numbers are identical) signedmagnitude 7 ~ 1, 0, 0, 1 ~ 7 (2 zeros) signed 1's comp 7 ~ 1, 0, 0, 1 ~ 7 (2 zeros) signed 2's comp 8 ~ 1, 0, 1 ~ 7 signed 1's comp : useful as a logical operation signed 2's comp : popular in use 3.10 Binary AdderSubtractors Binary AdderSubtractors 58 8bits Signed Binary Addition using 2 s complement 8bits Signed Binary subtraction using 2 s complement + Signed Binary Number 3.10 Binary AdderSubtractors 59 Overflow Detection Logic 60 Overflow
11 3.11 Binary Multipliers Binary Multipliers 62 a 2Bit by 2Bit Binary Multiplier a 4Bit by 3Bit Binary Multiplier B 3 B 2 B 1 B 0 x A 2 A 1 A A 0 B 3 A 0 B 2 A 0 B 1 A 0 B 0 A 1 B 3 A 1 B 2 A 1 B 1 A 1 B 0 A 2 B 3 A 2 B 2 A 2 B 1 A 2 B Decimal Arithmetic (BCD Adder) Decimal Arithmetic 64 0~9 ( 0000 ~ 1001), 1010, 1011, 1100, 1101, 1110, Ex) = B 16 error!!!! = 11 BCD ok C Sum BCD Adder binary numbers 1010 ~ 1111 need to correct 1010, 1011, 1100, 1101, 1110, 1111 if C = K + Z 1 Z 3 + Z 2 Z 3, add 0110 to the binary sum to add two n decimal digits needs n BCD adders 3.12 Decimal Arithmetic Use of Complements in Decimal 9's complement if is = 's complement if is = 's complement if is Structural Desc of 2to2 to4 4 Line Decoder 66 no end carry (10 s complement of 30718) =
12 Structural Desc of 4to4 to1 1 Line MUX 67 Dataflow Desc of 2to2 to4 4 Line Decoder 68 Dataflow Desc of 4to4 to1 1 Line MUX 69 Dataflow Desc of 4to4 to1 1 MUX 70 Structural/Dataflow Desc of 4bits 4 Full Adder 71 Structural/Dataflow Desc of 4bits 4 Full Adder 72
13 Structural/Dataflow Desc of 4bits 4 Full Adder 73 Behavioral Desc of 4bit 4 Full Adder 74
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