ARM Cortex-M4 Architecture and Instruction Set 1: Architecture Overview

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1 ARM Cortex-M4 Architecture and Instruction Set 1: Architecture Overview M J Brockway January 25, 2016

2 UM10562 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Block diagram NXP Semiconductors UM10562 Chapter 1: Introductory information 1.5 Simplified block diagram JTAG interface Ethernet PHY LCD USB bus or interface panel tranceiver Xtalin Xtalout RST General Purpose I/O ports Ethernet registers USB registers SPI Flash Interface LCD registers CRC engine TEST/DEBUG INTERFACE ARM Cortex-M4 with FPU I-code bus D-code bus System bus General Purpose DMA controller Ethernet 10/100 MAC Multilayer AHB Matrix LCD panel interface USB OTG/ Host/ Device clocks and controls EEPROM Up to 4 kb Flash Accelerator SRAM Up to 96 kb Boot ROM 8 kb Static / Dynamic Memory Controller clock generation, power control, and other system functions Flash Up to 512 kb 26-bit addr 32-bit data APB slave group 0 UARTs 0 & 1 SSP1 CAN 1 & 2 I 2 C 0 & 1 Capture/Match timer 0 & 1 PWM0 & 1 12-bit ADC Pin connect block GPIO interrupt control Analog comparators APB slave group 1 UARTs 2, 3, & 4 SSP0 & 2 I 2 S I 2 C 2 Capture/Match timer 2 & 3 SD card interface DAC Motor control PWM Quadrature Encoder i/f External interrupts Watchdog oscillator Event Inputs ALARM Vbat 32 khz oscillator ultra-low power regulator Windowed Watchdog Event Monitor/ Recorder Real Time Clock Backup registers (20 bytes) System control Note: - Orange shaded peripheral blocks support General Purpose DMA. - Yellow shaded peripheral blocks include a dedicated DMA controller. RTC Power Domain Fig 1. LPC408x/407x simplified block diagram User manual Rev March of 947

3 Block diagram This block diagram is reproduced from the LPC408x/407x User Manual, published by NXP Semiconductors, the makers of the LPC4088 microcontroller (CPU) used in our kit. There are a few TLAs (three-letter acronyms) - FPU floating-point unit DMA direct memory access Controller AHB advanced high-performance bus APB advanced peripheral bus SSP synchoronous serial port SPI serial peripheral interface - another serial bus I 2 C inter-integrated circuit - yet another serial bus PWM pulse-width modulation I 2 S inter-ic sound ADC, DAC, CAN...

4 Block diagram EEPROM electronically erasible, programmable read-only memory. Flash is a type of EEPROM. SRAM static random-access memory: fast; retains contents as long as powered-up; but expensive. Uses for key high performance purposes: cache, stack,... DRAM dynamic random-access memory: slower, and capacitor-based: needs regular charge top-up; but cheaper. Used for the bulk of RAM.

5 Programmer s model Ref: Generic User Guide section 2.1 Processor modes main stack - running application software. Limited access to some instructions, system timer. System is in this mode immediately after reset. handler mode - handling as exception. Returns to thread mode after all exceptions handled. Stacks full descending: Stack pointer is decremented when an item is pushed on; the stack grows downwards Two stacks: main and process; a special register controls which. Programmer s model: next slide (ref GUG 2.1.)

7 Programmer s model Registers... R0-R12 32-bit general-purpose registers for data operations. Avoid using higher regsiters for applicaton programming! R13 the stack pointer: main or process stack depending on setting in CONTROL register. R14 is the link register(lr): stores the return information for subroutines, function calls, and exceptions. R15 is the program counter: stores the address of the next instruction to be fetched. PSR The program status register contains information about status of last operationn. Bits are the condition codes; the ones we shall be most concerned with are N : the last operation produced an arithmetically negative result Z : the last operation produced a zero result C : the last operation produced a carry (or borrow) V : the last operation produced an arithmetic overflow

8 Programmer s model Registers (ctd) CONTROL manages privilege level of the current instruction, and which of the two stacks to use. Exceptions and interrupts NVIC The processor and the nested vectored interrupt controller manage prioritized handling. Data types 32-bit words, 16-bit halfwords, 8-bit bytes. Can be big- or little-endian; instruction memory and private peripheral but (PPB) accesses are always little-endian.

9 Memory model Ref: Generic User Guide sec 2.2; With 32-bit addressing, the memory space is 4 Gb.

10 Memory model code FFFFFFF is where executible code goes. On-chip FLASH. Data can go here, but not recommended. SRAM FFFFFFF is primarily for application data, but code can go here. peripherals FFFFFFF - on-chip peripherals external RAM FFFFFFF - eg DDR, FLASH, LCD external device A DFFFFFFF - external peripherals private peripher bus E E00FFFFF vendor-specific E FFFFFFFF

11 Memory model - bit-band aliasing A bit-band operation allows a single load/store operation to access a single bit in the memory; Normal method: load register with a 32-bit value from RAM address; OR or XOR it with a mask, or AND with MASK store register value to RAM address. Bit-band method - provided for some addresses: Each bit of the address is mapped from a bit-band alias address; Writing a 0 or 1 to the alias address changes just that bit of the real address. Fast only two operations rather than three; Atomic

12 Memory model - bit-band aliasing Example - set bit 3 at address 0x : LDR R1, =0x LDR R0,[R1] ORR.W R0,#0x8 STR R0,[R1] The bit-band alias for bit 3 of address 0x is 0x C so all we have to do is LDR R1, =0x C LDR R0, #1 STR R0, [R1]

13 Memory model - bit-band aliasing Only some addresses have bit-band aliases Addresses in the 32 Mb range FFFFF are aliases for the bits of the 1 Mb of data FFFFF. SRAM region Addresses in the 32 Mb range FFFFF are aliases for the bits of the 1 Mb of data FFFFF Peripherals region These addresses are normally used for memory-mapped I/O, where we need to read and set each bit as efficiently as possible. The very first blinky example you saw last semester used bit-band aliased addresses. See the Generic User Guide, subsection

14 Cortex-M4 Image of a Program From low to high memory, Interrupt vector table - addresses of interrupt and exception handlers 2. C startup routine 3. Application code and data 4. C library code On reset, the CPU 1. Reads initial stack pointer address 2. Reads interrupt vector for reset 3. The reset handler branches to start of application program 4. The program executes...

15 Introducing Cortex-M4 Machine Instructions The size of most instructions is 32 bits (4 bytes) or 16 bits (2 bytes), comprising a THUMB-2 operation code and sometimes and additional operand. The program as loaded into RAM is thus and array of 32-bit words. The address of the n th instruction (counting from 0) is therefore the base address of the loaded program + 32n. Shall use ARM assembly language as a human-readable version of these instructions. The following is a simple program: simpler than Hello world, as it does not do any I/O. It simply uses registers R0, R1 to compute , leaving the result in register R1.

16 Cortex-M4 Machine Instructions - simple example PRESERVE8 ; Indicate the code here preserve ; 8 byte stack alignment THUMB ; Indicate THUMB code is used AREA.text, CODE, READONLY ; Start of CODE area EXPORT main ENTRY main FUNCTION ; initialize registers MOV r0, #10 ; Starting loop counter value MOV r1, #0 ; starting result ; Calculating loop ADD r1, r0 ; R1 = R1 + R0 SUBS r0, #1 ; Decrement R0, update flag ( S suffix) BNE loop ; If result not zero jump to loop ; Result is now in R1 deadloop B deadloop ; Infinite loop ENDFUNC END ; End of file

17 Simple example: pseudocode main function: Put value 10 in register 0 Put value 0 in register 1 Repeat: Add contents of R0 to R1, leaving result in R1; Subtract 1 from contents of R0, updating condition codes according to the result; Check condition codes: if Z not set, repeat, else drop out of loop Forever run on the spot (branch to self)

18 Simple example with machine code and relative addresses PRESERVE ; 8 byte stack alignment THUMB AREA EXPORT main ENTRY main FUNCTION ; initialize registers F04F 000A MOV r0, # F04F 0100 MOV r1, # ; Calculating loop ADD r1, r A 3801 SUBS r0, # C D1FC BNE loop E ; Result is now in R E deadloop E E7FE B deadloop ENDFUNC END

19 References UM10562.pdf: The LPC408x/407x User Manual DUI0553A cortex m4 dgug.pdf: The Cortex M4 Generic User Guide Both these documents are linked to the home page of the module, in the group Resources for the LPC4088. The Generic User Guide is well worth reading in conjunction with these lecture slides and in general provides a fairly readable technical but not-too-technical introduction. The user manual is a good reference document.

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