Digital VLSI Design with Verilog

Transcription

1 John Williams Digital VLSI Design with Verilog A Textbook from Silicon Valley Technical Institute Foreword by Don Thomas Sprin ger

2 Contents Introduction xix 1 Course Description xix 2 Using this Book xx 2.1 Contents of the CD-ROM xx 2.2 Performing the Lab Exercises xx 2.3 Proprietary Information and Licensing Limitations xxi References xxi 1 Week 1 Class Introductory Lab Lab 1 Postmortem Verilog Vectors Operator Lab Lab Postmortem First-Day Wrapup VCD File Dump The Importance of Synthesis SDFFileDump Additional Study 19 2 Week 1 Class More Language Constructs Parameter and Conversion Lab Lab Postmortem Procedural Control Procedural Control in Verilog Combinational and Sequential Logic Verilog Strings and Messages Shift Registers Reconvergence Design Note Nonblocking Control Lab Lab Postmortem Additional Study 42 xi

3 xii Contents 3 Week 2 Class Net Types, Simulation, and Scan Variables and Constants Identifiers Concurrent vs. Procedural Blocks Miscellaneous Other Verilog Features Backus-Naur Format Verilog Semantics Modelling Sequential Logic Design for Test (DFT): Scan Lab Introduction Simple Scan Lab Lab Postmortem Additional Study 59 4 Week 2 Class PLLs and the SerDes Project Phase-Locked Loops A 1 x Digital PLL Introduction to SerDes and PCI Express The SerDes of this Course A 32 x Digital PLL PLL Clock Lab Lab Postmortem Additional Study 82 5 Week 3 Class Data Storage and Verilog Arrays Memory: Hardware and Software Description Verilog Arrays A Simple RAM Model Verilog Concatenation Memory Data Integrity Error Checking and Correcting (ECC) Parity for SerDes Frame Boundaries Memory Lab Lab Postmortem Additional Study 99 6 Week 3 Class Counter Types and Structures Introduction to Counters Terminology: Behavioral, Procedural, RTL, Structural Adder Expression vs. Counter Statement Counter Structures 105

4 Contents xiii 6.2 Counter Lab Lab Postmortem Ill Additional Study Ill 7 Week 4 Class Contention and Operator Precedence Verilog Net Types and Strengths Race Conditions, Again Unknowns in Relational Expressions Verilog Operators and Precedence Digital Basics: Three-State Buffer and Decoder Strength and Contention Lab Strength Lab postmortem Back to the PLL and the SerDes Named Blocks The PLL in a SerDes The SerDes Packet Format Revisited Behavioral PLL Synchronization (language digression) Synthesis of Behavioral Code Synthesizable, Pattern-Based PLL Synchronization PLL Behavioral Lock-In Lab Lock-in Lab Postmortem Additional Study Week 4 Class State Machine and FIFO design Verilog Tasks and Functions A Function for Synthesizable PLL Synchronization Concurrency by fork-join Verilog State Machines FIFO Functionality FIFO Operational Details A Verilog FIFO FIFO Lab Lab Postmortem Additional Study Week 5 Class Rise-Fall Delays and Event Scheduling Types of Delay Expression Verilog Simulation Event Queue Simple Stratified Queue Example Event Controls Event Queue Summary 178

5 xiv Contents 9.2 Scheduling Lab Lab Postmortem Additional Study Week 5 Class Built-in Gates and Net Types Verflog Built-in Gates Implied Wire Names Net Types and their Default Structural Use of Wire vs. Reg Port and Parameter Syntax Note A D Flip-flop from SR Latches Netlist Lab Lab Postmortem Additional Study Week 6 Class Procedural Control and Concurrency Verflog Procedural Control Statements Verflog case Variants Procedural Concurrency Verilog Name Space Concurrency Lab Lab Postmortem Additional Study Week 6 Class Hierarchical Names and generate Blocks Hierarchical Name Access Verilog Arrayed Instances generate Statements Conditional Macroes and Conditional generates Looping Generate Statements generate Blocks and Instance Names A Decoding Tree with Generate Scope of the generate Loop Generate Lab Lab Postmortem Additional Study Week 7 Class Serial-Parallel Conversion Simple Serial-Parallel Converter Deserialization by Function and Task Lab Preface: The Deserialization Decoder Some Deserializer Redesign - An Early ECO A Partitioning Question 237

6 Contents xv 13.3 Serial-Parallel Lab Lab Postmortem Additional Study Week 7 Class UDPs, Timing Triplets, and Switch-level Models User-Defined Primitives (UDPs) Delay Pessimism Gate-Level Timing Triplets Switch-Level Components Switch-Level Net: The Trireg Component Lab Lab Postmortem Additional Study Week 8 Class Parameter Types and Module Connection Summary of Parameter Characteristics ANSI Header Declaration Format Traditional Header Declaration Format Instantiation Formats ANSI Port and Parameter Options Traditional Module Header Format and Options Defparam Connection Lab Connection Lab Postmortem Hierarchical Names and Design Partitions Hierarchical Name References Scope of Declarations Design Partitioning Synchronization Across Clock Domains Hierarchy Lab Lab Postmortem Additional Study Week 8 Class Verilog Configurations Libraries Verilog Configuration Timing Arcs and specify Delays Arcs and Paths Distributed and Lumped Delays specify Blocks specparams Parallel vs. Full Path Delays Conditional and Edge-Dependent Delays 288

7 xvi Contents Conflicts of specify with Other Delays Conflicts Among specify Delays Timing Lab Lab Postmortem Additional Study Week 9 Class Timing Checks and Pulse Controls Timing Checks and Assertions Timing Check Rationale The Twelve Verilog Timing Checks Negative Time Limits Timing Check Conditioned Events Timing Check Notifiers Pulse Filtering Improved Pessimism Miscellaneous time-related Types Timing Check Lab Additional Study Week 9 Class The Sequential Deserializer PLL Redesign Improved VFO Clock Sampler Synthesizable Variable-Frequency Oscillator Synthesizable Frequency Comparator Modifications for a 400 MHz 1 x PLL Wrapper Modules for Portability Sequential Deserializer I Lab Lab Postmortem Additional Study Week 10 Class The Concurrent Deserializer Dual-porting the Memory Dual-clocking the FIFO State Machine Upgrading the FIFO for Synthesis Upgrading the Deserialization Decoder for Synthesis Concurrent Deserializer II Lab Lab Postmortem Additional Study Week 10 Class The Serializer and The SerDes The SerEncoder Module 362

8 Contents xvii The SerialTx Module The SerDes SerDes Lab Lab Postmortem Additional Study Week 11 Class Design for Test (DFT) Design for Test Introduction Assertions and Constraints Observability Coverage Corner-Case vs. Exhaustive Testing Boundary Scan Internal Scan BIST Scan and BIST Lab Lab postmortem DFT for a Full-Duplex SerDes Full-Duplex SerDes Adding Test Logic Tested SerDes Lab Lab Postmortem Additional Study Week 11 Class SDF Back-Annotation Back-Annotation SDF Files in Verilog Design Flow Verilog Simulation Back-Annotation SDF Lab Lab Postmortem Additional Study Week 12 Class Wrap-up: The Verilog Language Verilog-1995 vs (or 2005) Differences Verilog Synthesizable Subset Review Constructs Not Exercised in this Course List of all Verilog System Tasks and Functions List of all Verilog Compiler Directives Verilog PLI Continued Lab Work (Lab 23 or later) Additional Study 418

9 xviii Contents 24 Week 12 Class Deep-Submicron Problems and Verification Deep Submicron Design Problems The Bigger Problem Modern Verification Formal Verification Nonlogical Factors on the Chip System Verflog Continued Lab Work (Lab 23 or later) Additional Study 428 Index 429