60-265: Winter ANSWERS Exercise 4 Combinational Circuit Design

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1 60-265: Winter 2010 Computer Architecture I: Digital Design ANSWERS Exercise 4 Combinational Circuit Design Question 1. One-bit Comparator [ 1 mark ] Consider two 1-bit inputs, A and B. If we assume that the values A and B are treated as integer values (0 or 1) then it is meaningful to define the operation of comparison. If A and B are equivalent (ie. A==B in C language syntax) then we could indicate this using an output E set to 1. If A > B (ie. 1 > 0) then we could indicate this using an output G set to 1, but E=0. Finally, if A < B (ie. 0 < 1) then we could indicate this using an output L set to 1, but E=G=0. Note that all the output values for E, G and L are mutually exclusive (ie. only one of the outputs can be 1 at a time, while the other two are 0.) Write a complete truth table for this circuit, then derive simplified expressions for the circuit, and, finally, draw the logic diagram for the circuit. Comparing two 1-bit values is simple: E=1 iff AB + A'B' G=1 iff AB' L=1 iff A'B Question 2. Half-Subtracter Circuit [ 1 mark ] Design a Half-Subtracter circuit in a similar fashion to the Half-Adder Circuit. The Half- Subtracter accepts two 1-bit inputs, X and Y, and produces two 1-bit outputs, D and B, where D is the 1-bit difference of X-Y and B is the 1-bit "borrow" that would be required to complete the subtraction (eg. if X=0 and Y=1, then B=1 is the amount of borrow necessary to determine that D would be equal to 2-0-1=1). Develop the truth table, simplified expressions and draw the logic diagram.

2 Review the lecture notes on the subject of subtractive "borrowing" if you are unsure of how to proceed. A Half-Subtracter circuit has 2 inputs (X and Y) and 2 outputs (D and B) to determine the difference, D=X-Y and a "borrow", B (if required). To put this into proper perspective, compare with the Half-Adder, where a Carry-Out is needed (for the case of 1+1); this Carry-Out may participate in summing the digits in the column to the left. However, in the case of the Half-Subtracter, a Borrow-From may be needed "from" the column on the left (for the case of 0-1). The Borrow, B, may participate in finding the difference of digits in the column to the left. This leads to the cases and expressions: XY = 00 : D = 0, B = 0 XY = 11 : D = 0, B = 0 XY = 10 : D = 1, B = 0 XY = 01 : D = 1, B = 1 (since X < Y, a "borrow" is needed) Thus, D = XY' + X'Y and B = X'Y Note that the Half-Subtracter would normally be used only for the low-order digits in a multi-bit subtracter circuit, since for the low-order bit difference there cannot be any a priori borrowing (from the right). Question 3. Integer Overflow Detection [ 2 marks ] In the case of multi-bit signed-binary (ie. using 2's complement representation) addition, it is possible for the operation X+Y to result in a numeric overflow, for X and Y represented as multibit signed binary integer inputs. Overflow is defined, in general terms, as the obtaining of a result that is non-sensical. An example of this is shown by considering 7+1 (in base-10). In signed binary (base-2) this has the 4-bit signed binary representation: = 1000, or (decimal) -8! Clearly, this makes no sense and it indicates the conditions of an overflow operation. Determine the conditions for overflow for addition for a 4-bit adder circuit (ie. both X and Y are 4-bits each) that produces output S (4-bit signed binary sum) and a Carry-Out bit. Use a block diagram for the 4-bit adder (eg. the one derived in the lecture notes) as your starting point.

3 Extend this diagram to determine how to obtain the output V (for overflow bit) based on the various inputs (and outputs) from the 4-bit adder. Overflow for addition, X+Y, can only happen if two signed binary numbers X and Y have the same sign (ie. either positive, with high-order bit 0, or negative, with high-order bit 1). After the addition logic is performed, the resulting sum S reflects a value which has the opposite sign, hence the high-order bit of S is different than that of X and Y. Thus, the overflow bit can be defined by the logic: V = X 3 Y 3 S 3 ' + X 3 'Y 3 'S 3. Alternatively, it should be noted that whenever overflow does occur, the highorder bit of S differs from the Carry-Out bit C. This leads to the expression: V = CS 3 ' + C'S 3. Question 4. Designing a Combinational Circuit [ 3 marks] Design a combinational circuit with three inputs (X, Y, Z) and three outputs (A, B, C). When the triple (X,Y,Z) is taken as the 3-bit representation of a binary number, then (0,0,0) corresponds to 0, (0,0,1) to 1, (0,1,1) to 3, (1,0,1) to 5 and so on. Hence, X is the most significant bit while Z is the least significant bit. Similarly for the triple (A,B,C). When the binary input (X,Y,Z) is 0, 1, 2 or 3, the binary output is one greater than the input. When the binary input is 4, 5, 6 or 7, the binary output is one less than the input. Write the Truth Table for the inputs and outputs. Simplify the resulting expressions for A, B and C outputs (use algebra or maps). Draw the logic diagram for the complete circuit, labelling all inputs and outputs. X Y Z A B C

4 Simplified expressions for outputs are provided as: A = YZ + XZ + XY B = X Y Z + X YZ + XY Z + XYZ = (XY + X Y )Z + (XY + X Y)Z = X xor Y xor Z C = Z The logic diagram is straightforward and is left as an exercise to You may use any gates, including inverters, AND, OR and XOR gates. Question 5. Enabled Inc/Decrement Circuits [ 3 marks ] An L-bit unsigned binary Incrementer circuit is a circuit that accepts an L-bit input X that is an unsigned binary representation (ie. values range from the smallest, 0, to the largest, 2^L-1), plus a 1-bit input E (for "Enable"). The purpose of the circuit is to output the L-bit value Y = X+1, but only if E=1. If E=0, then the output Y=X and no change occurs. In other words, the value of X is incremented by 1 if the circuit is enabled. In the case where X=2^L-1 (ie. a string of 1's), then by adding 1, the output Y should be reset to zero (ie. string of 0's). Repeat the previous part of this question, but develop the circuit for an L-bit unsigned binary Decrementer circuit. In this case the output Y = X-1 when E=1, and Y=X when E=0. For the case of X=0, the output Y should be 2^L-1 when E=1. In both parts of this question, consider the possible role(s) that Half-Adder, Full-Adder, or other simple SSI circuits might play in designing your approach. You may also start from first principles with truth tables, expression simplification and so on. The choice is yours. There are many ways of approaching this question, but a simple way involves the use of a standard L-bit adder (as defined in the lecture notes). Recall that an L-bit adder applies two inputs A K and B K to the K'th Adder SSI circuit (either a Half-Adder for K=0, or a Full- Adder for K>0). We shall apply the X K inputs to the A K inputs for the K'th Adder SSI circuit. Decrementing by 1 is the same as adding -1, and -1 is always represented by a string of 1's in signed binary notation. Thus, we must deal with two cases. For E=0, Y=X. We apply E to the B K input. For E=1, Y=X-1. We apply E to the B K input.

5 Since the connections for the E input are the same in both cases, the circuit for the Decrementer is straightforward. Note that simpler circuits, with minimal gate logic, are possible. Students are encouraged to explore other alternative approaches. Copyright 2010 by Robert D. Kent. All rights reserved.

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