EKT 422/4 COMPUTER ARCHITECTURE. MINI PROJECT : Design of an Arithmetic Logic Unit

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1 EKT 422/4 COMPUTER ARCHITECTURE MINI PROJECT : Design of an Arithmetic Logic Unit Objective Students will design and build a customized Arithmetic Logic Unit (ALU). It will perform 16 different operations on two 4-bit inputs, producing a single 4-bit output and an overflow indicator. The design must work in simulation level. Figure 1: Overview of the experimental setup Preparation In this project, you will design an ALU that includes both an arithmetic circuit and a logic & shifting circuit, as shown in Figure 1. The unit will have two 4-bit inputs, A and B, and one 4-bit output C, as well as an overflow indicator for the arithmetic circuit. Table 1 shows the 16 microoperations that the ALU will be capable of performing. The control signal S3 will be used to switch the output between the arithmetic and logic circuits. Three other control signals S2, S1, and S0 will be used to direct the operations of the individual circuits. All inputs and outputs will pass through registers (D flip-flops that switch on the same clock edge). This is a sound design practice, because it ensures that both the inputs and outputs will be held steady for the entire clock period.

2 Table 1: Arithmetic and logic microoperations Circuit S3 S2 S1 S0 ALU output Description C A + B Add Add with carry Transfer A Arithmetic circuit Increment A Subtract A B with borrow (taking the 1 s complement of B). This will give an answer 1 lower than conventional subtraction Subtract A B (taking the 2 s complement of B) NOT A (1 s complement of A) C A s complement of A Clear Set Logic & shifting circuit A AND B A OR B A XOR B Selective clear A Left shift A (multiply by 2) Right shift A (divide by 2) Hierarchical design Since the ALU s input and output signals are all 4 bits wide, the most efficient way to implement the ALU will be a hierarchical design. The bottom-level design files will be a 1-bit full adder circuit and a 1-bit logic circuit. The intermediate files will be a 4-bit register, a 4-bit arithmetic circuit and a 4-bit logic circuit. Last, the top level file will encompass the complete design, suitable for download onto the UP2 board. The relationship between these files is shown in Figure 2. The designs shaded in yellow are specified later in this document. In preparation for the lab, it is necessary to design the circuits shaded in green: the 1-bit logic circuit, the 4- bit logic circuit, and the 4-bit arithmetic circuit.

3 Figure 2: Hierarchy of design files 1-bit logic & shifting design file At its lowest level, the logic and shifting circuit operates on a bit-by-bit basis (say, on bits A2 and B2). Design a circuit that implements all of the logic and shifting functions shown in the bottom half of Table 1. The circuit should have three control inputs (S2, S1 and S0), two logic inputs (A and ), two additional inputs for left i BBi and right shifting (A and A ), and one output (C ). For inspiration, see Figure 3a below for an example of a i-1 i+1 i 1-bit logic circuit, and Figure 3b for an example of how to implement a shifter using a multiplexer. S1 S0 Output Operation 0 0 E = A B AND 0 1 E = A B OR 1 0 E = A B X-OR 1 1 E = A Complement Figure 3a: One stage logic circuit Figure 3b: One stage of arithmetic logic shift unit For this project, assume that A3 and B3 are the most significant bits, and A0 and B0 are the least significant bits. A suitable multiplexer to use in this design is the 74151, which has the symbol and truth table shown below. Note that the A, B and C shown in the truth table are the multiplexer s select lines, and do not correspond to the A, B and C in our ALU design.

4 Figure 3c: Schematic symbol for the multiplexer Table 2: Truth table for the multiplexer Inputs Output Select Enable C B A GN Y X X X D D D D D D D D7 4-bit logic & shifting design file Determine how to connect four of your 1-bit logic circuits to implement a 4-bit circuit. At the ends of the shifters, shift a zero into the delay chain. The final design should have three control inputs (S2 S0), eight data inputs (A3 A0 and B3 B0), and four data outputs (C3 C0). 4-bit arithmetic circuit design file The 4-bit arithmetic circuit will make use of the full-adder circuit. Determine how to connect four of these adders to implement the arithmetic functions shown in Table 1. Your final design should have three control inputs (S2 S0), eight data inputs (A3 A0 and B3 B0), four data outputs (C3 C0) and a one-bit output to indicate overflow. Here are a few hints to simplify this task! Use control bit S0 as the carry-in bit. Note that the ALU s truth table will not allow you to input the A3 A0 bits directly to the full adders, so some extra logic will be required. Start your design by analyzing what inputs must appear at the full adder inputs for each combination of S2 and S1. The symbol and truth table of the dual 4-line to 1-line multiplexer are shown below. Note that both multiplexers share the same select lines A and B (once again, not related to the ALU inputs of the same name!).

5 Figure 4: Schematic symbol for the dual multiplexer Table 3: Truth table for the dual multiplexer Inputs Output Select Enable B A GN Y X X C C C C3 The quad 2-line to 1-line multiplexer has the following symbol and truth table: Figure 5: Schematic symbol for the quad multiplexer Table 4: Truth table for the quad multiplexer Inputs Output Select Enable SEL GN Y X 1 Z (high impedance) 0 0 A 1 0 B Overflow detection is discussed on pages of the textbook.

6 If you wish, you may implement a carry look-ahead adder. However, a ripple adder will be fully satisfactory. Procedure 1. Use Max+Plus II to enter the following graphical design file, which implements a 4-bit register. Use D flip-flops (symbol dff ). Save the file as register4bits.gdf (adopting a standard name will help the TA debug your design, should problems arise). Figure 6: Schematic of a 4-bit register 2. Set the project to the current file, set the device to an EPM7128SLC84-7, and make sure that the file compiles properly (there is no need to assign pin numbers at this stage). Check the file register4bits.rpt to see what percentage of the chip s resources have been used. Create a default symbol that can be used later. 3. Enter your 1-bit logic & shifting circuit design in a file called logiccircuit1bit.gdf. To enter the multiplexer s symbol in the schematic, simply right-click, select Enter symbol, and type in the Symbol Name box. If the multiplexer does not display the way you want it to, you can right-click it and flip it in either the horizontal or vertical directions. Set the project to the current file, assign the device, compile the file to check for errors, and create a default symbol.

7 4. Enter your 4-bit logic & shifting circuit design in a file called logiccircuit4bits.gdf. Set the project to the current file, assign the device, compile the file and create a default symbol. What percentage of the chip s resources does this design require? 5. Enter the following full adder design into a file called fulladder1bit.gdf. Assign the device, compile it to ensure there are no errors, and create a default symbol. Figure 7: Schematic of full adder 6. Enter your 4-bit arithmetic circuit design in a file called arithcircuit4bits.gdf. Set the project to the current file, assign the device, compile the file and create a default symbol. What percentage of the chip s resources does this design require? Is the arithmetic circuit more or less complicated than the logic & shifting circuit? 7. Combine your registers, arithmetic and logic circuits with a multiplexer in a top-level file similar to that shown in Figure 8 (shown on the last page of this document). Your diagram may differ slightly, based on the naming conventions you adopted in your design, and on the default symbols that were created. 8. Set the project to the current file and assign the device to an EPM7128SLC84-7. Assign pin 83 to the clock and pin 1 to CLRN, but leave all other signals unassigned. Compile the design (the place & route engine will automatically assign the other pins appropriately). 9. Create a waveform (.scf) file. a. Select Options Grid Size and enter 50ns. Note that this circuit should operate satisfactorily using a 20ns grid size and 40 ns clock period if designed well. This value is a conservative number that should give even the most inefficient designs enough time to stabilize between clock edges! b. Select File End Time and type in 2.0us. c. Right-click the screen and select Enter nodes from SNF to import all of your input and output signals into the.scf file. d. Set up the clk and CLRN signals as appropriate (note that CLRN is active low, so the ALU will not come out of reset unless CLRN is high). e. Set up the remaining input signals to implement the series of RTL instructions contained in Table 5. It is highly recommended that you group your signals to simplify data entry and enhance readability. To group A3 A0, assuming that A3 is the MSB and A0 is the LSB, make sure that the signals are ordered from A3 at the top to A0 at the bottom. Select A3, then depress the shift key and select A0. Right-click and select Enter group. Choose the binary display format, and select OK. To overwrite the group value, use the mouse to select a signal over the desired time range, then click the G icon on the left-hand side of the screen. A small box will pop up and prompt you for a new value.

8 Table 5: Sequence of microoperations for simulation Clock cycle RTL microoperations 10. Run the simulation and check that all components of your ALU work as they should. Note that results will be delayed at the output because of the input and output registers! If elements of your design do not function properly, troubleshoot your work until the problems have been resolved. Capture a screen shot of the simulation for your lab report. Submission This project is due in two weeks. The following items should be included in the lab report: 1. schematic diagrams of the circuits you designed; 2. a brief discussion explaining how you arrived at your final design; and 3. an image of your simulation (.scf) file. You may break this into multiple images if necessary.

9 Figure 8: Schematic of the complete ALU

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