EKT 422/4 COMPUTER ARCHITECTURE. MINI PROJECT : Design of an Arithmetic Logic Unit
|
|
- Christiana Neal
- 6 years ago
- Views:
Transcription
1 EKT 422/4 COMPUTER ARCHITECTURE MINI PROJECT : Design of an Arithmetic Logic Unit Objective Students will design and build a customized Arithmetic Logic Unit (ALU). It will perform 16 different operations on two 4-bit inputs, producing a single 4-bit output and an overflow indicator. The design must work in simulation level. Figure 1: Overview of the experimental setup Preparation In this project, you will design an ALU that includes both an arithmetic circuit and a logic & shifting circuit, as shown in Figure 1. The unit will have two 4-bit inputs, A and B, and one 4-bit output C, as well as an overflow indicator for the arithmetic circuit. Table 1 shows the 16 microoperations that the ALU will be capable of performing. The control signal S3 will be used to switch the output between the arithmetic and logic circuits. Three other control signals S2, S1, and S0 will be used to direct the operations of the individual circuits. All inputs and outputs will pass through registers (D flip-flops that switch on the same clock edge). This is a sound design practice, because it ensures that both the inputs and outputs will be held steady for the entire clock period.
2 Table 1: Arithmetic and logic microoperations Circuit S3 S2 S1 S0 ALU output Description C A + B Add Add with carry Transfer A Arithmetic circuit Increment A Subtract A B with borrow (taking the 1 s complement of B). This will give an answer 1 lower than conventional subtraction Subtract A B (taking the 2 s complement of B) NOT A (1 s complement of A) C A s complement of A Clear Set Logic & shifting circuit A AND B A OR B A XOR B Selective clear A Left shift A (multiply by 2) Right shift A (divide by 2) Hierarchical design Since the ALU s input and output signals are all 4 bits wide, the most efficient way to implement the ALU will be a hierarchical design. The bottom-level design files will be a 1-bit full adder circuit and a 1-bit logic circuit. The intermediate files will be a 4-bit register, a 4-bit arithmetic circuit and a 4-bit logic circuit. Last, the top level file will encompass the complete design, suitable for download onto the UP2 board. The relationship between these files is shown in Figure 2. The designs shaded in yellow are specified later in this document. In preparation for the lab, it is necessary to design the circuits shaded in green: the 1-bit logic circuit, the 4- bit logic circuit, and the 4-bit arithmetic circuit.
3 Figure 2: Hierarchy of design files 1-bit logic & shifting design file At its lowest level, the logic and shifting circuit operates on a bit-by-bit basis (say, on bits A2 and B2). Design a circuit that implements all of the logic and shifting functions shown in the bottom half of Table 1. The circuit should have three control inputs (S2, S1 and S0), two logic inputs (A and ), two additional inputs for left i BBi and right shifting (A and A ), and one output (C ). For inspiration, see Figure 3a below for an example of a i-1 i+1 i 1-bit logic circuit, and Figure 3b for an example of how to implement a shifter using a multiplexer. S1 S0 Output Operation 0 0 E = A B AND 0 1 E = A B OR 1 0 E = A B X-OR 1 1 E = A Complement Figure 3a: One stage logic circuit Figure 3b: One stage of arithmetic logic shift unit For this project, assume that A3 and B3 are the most significant bits, and A0 and B0 are the least significant bits. A suitable multiplexer to use in this design is the 74151, which has the symbol and truth table shown below. Note that the A, B and C shown in the truth table are the multiplexer s select lines, and do not correspond to the A, B and C in our ALU design.
4 Figure 3c: Schematic symbol for the multiplexer Table 2: Truth table for the multiplexer Inputs Output Select Enable C B A GN Y X X X D D D D D D D D7 4-bit logic & shifting design file Determine how to connect four of your 1-bit logic circuits to implement a 4-bit circuit. At the ends of the shifters, shift a zero into the delay chain. The final design should have three control inputs (S2 S0), eight data inputs (A3 A0 and B3 B0), and four data outputs (C3 C0). 4-bit arithmetic circuit design file The 4-bit arithmetic circuit will make use of the full-adder circuit. Determine how to connect four of these adders to implement the arithmetic functions shown in Table 1. Your final design should have three control inputs (S2 S0), eight data inputs (A3 A0 and B3 B0), four data outputs (C3 C0) and a one-bit output to indicate overflow. Here are a few hints to simplify this task! Use control bit S0 as the carry-in bit. Note that the ALU s truth table will not allow you to input the A3 A0 bits directly to the full adders, so some extra logic will be required. Start your design by analyzing what inputs must appear at the full adder inputs for each combination of S2 and S1. The symbol and truth table of the dual 4-line to 1-line multiplexer are shown below. Note that both multiplexers share the same select lines A and B (once again, not related to the ALU inputs of the same name!).
5 Figure 4: Schematic symbol for the dual multiplexer Table 3: Truth table for the dual multiplexer Inputs Output Select Enable B A GN Y X X C C C C3 The quad 2-line to 1-line multiplexer has the following symbol and truth table: Figure 5: Schematic symbol for the quad multiplexer Table 4: Truth table for the quad multiplexer Inputs Output Select Enable SEL GN Y X 1 Z (high impedance) 0 0 A 1 0 B Overflow detection is discussed on pages of the textbook.
6 If you wish, you may implement a carry look-ahead adder. However, a ripple adder will be fully satisfactory. Procedure 1. Use Max+Plus II to enter the following graphical design file, which implements a 4-bit register. Use D flip-flops (symbol dff ). Save the file as register4bits.gdf (adopting a standard name will help the TA debug your design, should problems arise). Figure 6: Schematic of a 4-bit register 2. Set the project to the current file, set the device to an EPM7128SLC84-7, and make sure that the file compiles properly (there is no need to assign pin numbers at this stage). Check the file register4bits.rpt to see what percentage of the chip s resources have been used. Create a default symbol that can be used later. 3. Enter your 1-bit logic & shifting circuit design in a file called logiccircuit1bit.gdf. To enter the multiplexer s symbol in the schematic, simply right-click, select Enter symbol, and type in the Symbol Name box. If the multiplexer does not display the way you want it to, you can right-click it and flip it in either the horizontal or vertical directions. Set the project to the current file, assign the device, compile the file to check for errors, and create a default symbol.
7 4. Enter your 4-bit logic & shifting circuit design in a file called logiccircuit4bits.gdf. Set the project to the current file, assign the device, compile the file and create a default symbol. What percentage of the chip s resources does this design require? 5. Enter the following full adder design into a file called fulladder1bit.gdf. Assign the device, compile it to ensure there are no errors, and create a default symbol. Figure 7: Schematic of full adder 6. Enter your 4-bit arithmetic circuit design in a file called arithcircuit4bits.gdf. Set the project to the current file, assign the device, compile the file and create a default symbol. What percentage of the chip s resources does this design require? Is the arithmetic circuit more or less complicated than the logic & shifting circuit? 7. Combine your registers, arithmetic and logic circuits with a multiplexer in a top-level file similar to that shown in Figure 8 (shown on the last page of this document). Your diagram may differ slightly, based on the naming conventions you adopted in your design, and on the default symbols that were created. 8. Set the project to the current file and assign the device to an EPM7128SLC84-7. Assign pin 83 to the clock and pin 1 to CLRN, but leave all other signals unassigned. Compile the design (the place & route engine will automatically assign the other pins appropriately). 9. Create a waveform (.scf) file. a. Select Options Grid Size and enter 50ns. Note that this circuit should operate satisfactorily using a 20ns grid size and 40 ns clock period if designed well. This value is a conservative number that should give even the most inefficient designs enough time to stabilize between clock edges! b. Select File End Time and type in 2.0us. c. Right-click the screen and select Enter nodes from SNF to import all of your input and output signals into the.scf file. d. Set up the clk and CLRN signals as appropriate (note that CLRN is active low, so the ALU will not come out of reset unless CLRN is high). e. Set up the remaining input signals to implement the series of RTL instructions contained in Table 5. It is highly recommended that you group your signals to simplify data entry and enhance readability. To group A3 A0, assuming that A3 is the MSB and A0 is the LSB, make sure that the signals are ordered from A3 at the top to A0 at the bottom. Select A3, then depress the shift key and select A0. Right-click and select Enter group. Choose the binary display format, and select OK. To overwrite the group value, use the mouse to select a signal over the desired time range, then click the G icon on the left-hand side of the screen. A small box will pop up and prompt you for a new value.
8 Table 5: Sequence of microoperations for simulation Clock cycle RTL microoperations 10. Run the simulation and check that all components of your ALU work as they should. Note that results will be delayed at the output because of the input and output registers! If elements of your design do not function properly, troubleshoot your work until the problems have been resolved. Capture a screen shot of the simulation for your lab report. Submission This project is due in two weeks. The following items should be included in the lab report: 1. schematic diagrams of the circuits you designed; 2. a brief discussion explaining how you arrived at your final design; and 3. an image of your simulation (.scf) file. You may break this into multiple images if necessary.
9 Figure 8: Schematic of the complete ALU
REGISTER TRANSFER LANGUAGE
REGISTER TRANSFER LANGUAGE The operations executed on the data stored in the registers are called micro operations. Classifications of micro operations Register transfer micro operations Arithmetic micro
More informationUNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT
UNIT-III 1 KNREDDY UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT Register Transfer: Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Micro operations Logic
More informationBUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book
BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book Decoder Tri-state device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write
More informationCSE 141L Computer Architecture Lab Fall Lecture 3
CSE 141L Computer Architecture Lab Fall 2005 Lecture 3 Pramod V. Argade November 1, 2005 Fall 2005 CSE 141L Course Schedule Lecture # Date Day Lecture Topic Lab Due 1 9/27 Tuesday No Class 2 10/4 Tuesday
More informationLab 1 Modular Design and Testbench Simulation ENGIN 341 Advanced Digital Design University of Massachusetts Boston
Lab 1 Modular Design and Testbench Simulation ENGIN 341 Advanced Digital Design University of Massachusetts Boston Introduction This lab introduces the concept of modular design by guiding you through
More informationEXPERIMENT NUMBER 11 REGISTERED ALU DESIGN
11-1 EXPERIMENT NUMBER 11 REGISTERED ALU DESIGN Purpose Extend the design of the basic four bit adder to include other arithmetic and logic functions. References Wakerly: Section 5.1 Materials Required
More informationEXPERIMENT #8: BINARY ARITHMETIC OPERATIONS
EE 2 Lab Manual, EE Department, KFUPM EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS OBJECTIVES: Design and implement a circuit that performs basic binary arithmetic operations such as addition, subtraction,
More informationComputer Architecture and Organization: L04: Micro-operations
Computer Architecture and Organization: L4: Micro-operations By: A. H. Abdul Hafez Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com, hafez@research.iiit.ac.in 1 Outlines 1. Arithmetic microoperation 2.
More informationArithmetic Logic Unit. Digital Computer Design
Arithmetic Logic Unit Digital Computer Design Arithmetic Circuits Arithmetic circuits are the central building blocks of computers. Computers and digital logic perform many arithmetic functions: addition,
More informationRegister Transfer Language and Microoperations (Part 2)
Register Transfer Language and Microoperations (Part 2) Adapted by Dr. Adel Ammar Computer Organization 1 MICROOPERATIONS Computer system microoperations are of four types: Register transfer microoperations
More informationCOMPUTER ARCHITECTURE AND ORGANIZATION Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital
Register Transfer and Micro-operations 1. Introduction A digital system is an interconnection of digital hardware modules that accomplish a specific information-processing task. Digital systems vary in
More informationCSCB58 - Lab 3. Prelab /3 Part I (in-lab) /2 Part II (in-lab) /2 TOTAL /8
CSCB58 - Lab 3 Latches, Flip-flops, and Registers Learning Objectives The purpose of this exercise is to investigate the fundamental synchronous logic elements: latches, flip-flops, and registers. Prelab
More informationDigital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University
Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register
More informationECE 341 Midterm Exam
ECE 341 Midterm Exam Time allowed: 75 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (8 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a) A
More informationECE 341 Midterm Exam
ECE 341 Midterm Exam Time allowed: 90 minutes Total Points: 75 Points Scored: Name: Problem No. 1 (10 points) For each of the following statements, indicate whether the statement is TRUE or FALSE: (a)
More informationMicrocomputers. Outline. Number Systems and Digital Logic Review
Microcomputers Number Systems and Digital Logic Review Lecture 1-1 Outline Number systems and formats Common number systems Base Conversion Integer representation Signed integer representation Binary coded
More informationTwo-Level CLA for 4-bit Adder. Two-Level CLA for 4-bit Adder. Two-Level CLA for 16-bit Adder. A Closer Look at CLA Delay
Two-Level CLA for 4-bit Adder Individual carry equations C 1 = g 0 +p 0, C 2 = g 1 +p 1 C 1,C 3 = g 2 +p 2 C 2, = g 3 +p 3 C 3 Fully expanded (infinite hardware) CLA equations C 1 = g 0 +p 0 C 2 = g 1
More informationTailoring the 32-Bit ALU to MIPS
Tailoring the 32-Bit ALU to MIPS MIPS ALU extensions Overflow detection: Carry into MSB XOR Carry out of MSB Branch instructions Shift instructions Slt instruction Immediate instructions ALU performance
More informationENEE245 Digital Circuits and Systems Lab Manual
ENEE245 Digital Circuits and Systems Lab Manual Department of Engineering, Physical & Computer Sciences Montgomery College Version 1.1 Copyright Prof. Lan Xiang (Do not distribute without permission) 1
More informationLecture Topics. Announcements. Today: Integer Arithmetic (P&H ) Next: continued. Consulting hours. Introduction to Sim. Milestone #1 (due 1/26)
Lecture Topics Today: Integer Arithmetic (P&H 3.1-3.4) Next: continued 1 Announcements Consulting hours Introduction to Sim Milestone #1 (due 1/26) 2 1 Overview: Integer Operations Internal representation
More informationENEE245 Digital Circuits and Systems Lab Manual
ENEE245 Digital Circuits and Systems Lab Manual Department of Engineering, Physical & Computer Sciences Montgomery College Modified Fall 2017 Copyright Prof. Lan Xiang (Do not distribute without permission)
More informationFor Example: P: LOAD 5 R0. The command given here is used to load a data 5 to the register R0.
Register Transfer Language Computers are the electronic devices which have several sets of digital hardware which are inter connected to exchange data. Digital hardware comprises of VLSI Chips which are
More informationREGISTER TRANSFER AND MICROOPERATIONS
1 REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift
More informationCOMP 303 Computer Architecture Lecture 6
COMP 303 Computer Architecture Lecture 6 MULTIPLY (unsigned) Paper and pencil example (unsigned): Multiplicand 1000 = 8 Multiplier x 1001 = 9 1000 0000 0000 1000 Product 01001000 = 72 n bits x n bits =
More informationChapter 5. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 5 <1>
Chapter 5 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 Chapter 5 :: Topics Introduction Arithmetic Circuits umber Systems Sequential Building
More informationChapter 3: part 3 Binary Subtraction
Chapter 3: part 3 Binary Subtraction Iterative combinational circuits Binary adders Half and full adders Ripple carry and carry lookahead adders Binary subtraction Binary adder-subtractors Signed binary
More informationCOSC 243. Computer Architecture 1. COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1
COSC 243 Computer Architecture 1 COSC 243 (Computer Architecture) Lecture 6 - Computer Architecture 1 1 Overview Last Lecture Flip flops This Lecture Computers Next Lecture Instruction sets and addressing
More informationComputer Architecture Programming the Basic Computer
4. The Execution of the EXCHANGE Instruction The EXCHANGE routine reads the operand from the effective address and places it in DR. The contents of DR and AC are interchanged in the third microinstruction.
More informationEE577A FINAL PROJECT REPORT Design of a General Purpose CPU
EE577A FINAL PROJECT REPORT Design of a General Purpose CPU Submitted By Youngseok Lee - 4930239194 Narayana Reddy Lekkala - 9623274062 Chirag Ahuja - 5920609598 Phase 2 Part 1 A. Introduction The core
More informationWriting Circuit Descriptions 8
8 Writing Circuit Descriptions 8 You can write many logically equivalent descriptions in Verilog to describe a circuit design. However, some descriptions are more efficient than others in terms of the
More informationCS 151 Midterm. (Last Name) (First Name)
CS 151 Midterm Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 13 pages including this cover. 2. Write down your Student-Id on the top
More informationDate Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS
Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 09 MULTIPLEXERS OBJECTIVES: To experimentally verify the proper operation of a multiplexer.
More information4DM4 Lab. #1 A: Introduction to VHDL and FPGAs B: An Unbuffered Crossbar Switch (posted Thursday, Sept 19, 2013)
1 4DM4 Lab. #1 A: Introduction to VHDL and FPGAs B: An Unbuffered Crossbar Switch (posted Thursday, Sept 19, 2013) Lab #1: ITB Room 157, Thurs. and Fridays, 2:30-5:20, EOW Demos to TA: Thurs, Fri, Sept.
More informationArithmetic Operations
Arithmetic Operations Arithmetic Operations addition subtraction multiplication division Each of these operations on the integer representations: unsigned two's complement 1 Addition One bit of binary
More informationR10. II B. Tech I Semester, Supplementary Examinations, May
SET - 1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) -48 and +31
More informationArithmetic Circuits. Nurul Hazlina Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit
Nurul Hazlina 1 1. Adder 2. Multiplier 3. Arithmetic Logic Unit (ALU) 4. HDL for Arithmetic Circuit Nurul Hazlina 2 Introduction 1. Digital circuits are frequently used for arithmetic operations 2. Fundamental
More informationParallel logic circuits
Computer Mathematics Week 9 Parallel logic circuits College of Information cience and Engineering Ritsumeikan University last week the mathematics of logic circuits the foundation of all digital design
More informationREGISTER TRANSFER AND MICROOPERATIONS
REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift
More informationCHAPTER 4: Register Transfer Language and Microoperations
CS 224: Computer Organization S.KHABET CHAPTER 4: Register Transfer Language and Microoperations Outline Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations
More informationUNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180B DIGITAL SYSTEMS II Fall 1999
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180B DIGITAL SYSTEMS II Fall 1999 Lab 7-10: Micro-processor Design: Minimal Instruction Set Processor (MISP) Objective:
More information5 Arithmetic Logic Unit
Arithmetic Logic Unit, Muxes 5 Arithmetic Logic Unit I Overview An Arithmetic Logic Unit (ALU) allows many pre-defined functions to be implemented on two binary inputs. We will look at a simple ALU that
More informationComputer Organization (Autonomous)
Computer Organization (Autonomous) UNIT I Sections - A & D Prepared by Anil Kumar Prathipati, Asst. Prof., Dept. of CSE. SYLLABUS Introduction: Types of Computers, Functional units of Basic Computer (Block
More informationLet s put together a Manual Processor
Lecture 14 Let s put together a Manual Processor Hardware Lecture 14 Slide 1 The processor Inside every computer there is at least one processor which can take an instruction, some operands and produce
More informationTo design a 4-bit ALU To experimentally check the operation of the ALU
1 Experiment # 11 Design and Implementation of a 4 - bit ALU Objectives: The objectives of this lab are: To design a 4-bit ALU To experimentally check the operation of the ALU Overview An Arithmetic Logic
More informationECSE-323 Digital System Design. Lab #1 Using the Altera Quartus II Software Fall 2008
1 ECSE-323 Digital System Design Lab #1 Using the Altera Quartus II Software Fall 2008 2 Introduction. In this lab you will learn the basics of the Altera Quartus II FPGA design software through following
More informationFinite State Machine Lab
Finite State Machine Module: Lab Procedures Goal: The goal of this experiment is to reinforce state machine concepts by having students design and implement a state machine using simple chips and a protoboard.
More information1 MALP ( ) Unit-1. (1) Draw and explain the internal architecture of 8085.
(1) Draw and explain the internal architecture of 8085. The architecture of 8085 Microprocessor is shown in figure given below. The internal architecture of 8085 includes following section ALU-Arithmetic
More informationInternational Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
An Efficient Implementation of Double Precision Floating Point Multiplier Using Booth Algorithm Pallavi Ramteke 1, Dr. N. N. Mhala 2, Prof. P. R. Lakhe M.Tech [IV Sem], Dept. of Comm. Engg., S.D.C.E, [Selukate],
More informationDigital Logic & Computer Design CS Professor Dan Moldovan Spring 2010
Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 5- Chapter 5 :: Digital Building Blocks Digital Design and Computer Architecture David Money Harris and Sarah
More informationMidterm Project Design of 4 Bit ALU Fall 2001
Midterm Project Design of 4 Bit ALU Fall 2001 By K.Narayanan George Washington University E.C.E Department K.Narayanan Fall 2001 1 Midterm Project... 1 Design of 4 Bit ALU... 1 Abstract... 3 1.2 Specification:...
More informationReal Digital Problem Set #6
Real igital Problem et #6. (2 points) ketch a block diagram for a magnitude comparator bit-slice circuit. Create K-maps to define the bit-slice circuit, and use them to find optimal logic equations. ketch
More informationInstitute of Engineering & Management
Course:CS493- Computer Architecture Lab PROGRAMME: COMPUTERSCIENCE&ENGINEERING DEGREE:B. TECH COURSE: Computer Architecture Lab SEMESTER: 4 CREDITS: 2 COURSECODE: CS493 COURSE TYPE: Practical COURSE AREA/DOMAIN:
More informationDESIGN PROJECT TOY RPN CALCULATOR
April 8, 1998 DESIGN PROJECT TOY RPN CALCULATOR ECE/Comp Sci 352 Digital System Fundamentals Semester II 1997-98 Due Tuesday, April 28, 1998; 10% of course grade. This project is to be submitted and will
More informationExperiment 7 Arithmetic Circuits Design and Implementation
Experiment 7 Arithmetic Circuits Design and Implementation Introduction: Addition is just what you would expect in computers. Digits are added bit by bit from right to left, with carries passed to the
More informationPrachi Sharma 1, Rama Laxmi 2, Arun Kumar Mishra 3 1 Student, 2,3 Assistant Professor, EC Department, Bhabha College of Engineering
A Review: Design of 16 bit Arithmetic and Logical unit using Vivado 14.7 and Implementation on Basys 3 FPGA Board Prachi Sharma 1, Rama Laxmi 2, Arun Kumar Mishra 3 1 Student, 2,3 Assistant Professor,
More informationFPGA Implementation of Multiplier for Floating- Point Numbers Based on IEEE Standard
FPGA Implementation of Multiplier for Floating- Point Numbers Based on IEEE 754-2008 Standard M. Shyamsi, M. I. Ibrahimy, S. M. A. Motakabber and M. R. Ahsan Dept. of Electrical and Computer Engineering
More informationBinary Arithmetic. Daniel Sanchez Computer Science & Artificial Intelligence Lab M.I.T.
Binary Arithmetic Daniel Sanchez Computer Science & Artificial Intelligence Lab M.I.T. MIT 6.004 Fall 2018 Reminder: Encoding Positive Integers Bit i in a binary representation (in right-to-left order)
More informationDIGITAL ARITHMETIC: OPERATIONS AND CIRCUITS
C H A P T E R 6 DIGITAL ARITHMETIC: OPERATIONS AND CIRCUITS OUTLINE 6- Binary Addition 6-2 Representing Signed Numbers 6-3 Addition in the 2 s- Complement System 6-4 Subtraction in the 2 s- Complement
More informationFinal Exam Solution Sunday, December 15, 10:05-12:05 PM
Last (family) name: First (given) name: Student I.D. #: Circle section: Kim Hu Department of Electrical and Computer Engineering University of Wisconsin - Madison ECE/CS 352 Digital System Fundamentals
More informationChapter 4 Arithmetic Functions
Logic and Computer Design Fundamentals Chapter 4 Arithmetic Functions Charles Kime & Thomas Kaminski 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Overview Iterative combinational
More informationDigital Circuit Design Using Xilinx ISE Tools
Digital Circuit Design Using Xilinx ISE Tools Poras T. Balsara and Prashant Vallur Table of Contents 1. Introduction 2. Programmable logic devices: FPGA and CPLD 3. Creating a new project in Xilinx Foundation
More informationLearning Outcomes. Spiral 2 2. Digital System Design DATAPATH COMPONENTS
2-2. 2-2.2 Learning Outcomes piral 2 2 Arithmetic Components and Their Efficient Implementations I know how to combine overflow and subtraction results to determine comparison results of both signed and
More informationCombinational and sequential circuits (learned in Chapters 1 and 2) can be used to create simple digital systems.
REGISTER TRANSFER AND MICROOPERATIONS Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Microoperations Logic Microoperations Shift Microoperations Arithmetic Logic Shift
More informationVerilog Lab. Two s Complement Add/Sub Unit. TA: Xin-Yu Shi
Verilog Lab. Two s Complement Add/Sub Unit TA: Xin-Yu Shi genius@access.ee.ntu.edu.tw Introduction In previous lecture, what you have learned : Complete representation for binary negative number Arithmetic
More informationSCHEMATIC DESIGN IN QUARTUS
SCHEMATIC DESIGN IN QUARTUS Consider the design of a three-bit prime number detector. Figure 1 shows the block diagram and truth table. The inputs are binary signals A, B, and C while the output is binary
More informationLearning Outcomes. Spiral 2-2. Digital System Design DATAPATH COMPONENTS
2-2. 2-2.2 Learning Outcomes piral 2-2 Arithmetic Components and Their Efficient Implementations I understand the control inputs to counters I can design logic to control the inputs of counters to create
More informationIA Digital Electronics - Supervision I
IA Digital Electronics - Supervision I Nandor Licker Due noon two days before the supervision 1 Overview The goal of this exercise is to design an 8-digit calculator capable of adding
More informationComputer Organization
Register Transfer Logic Department of Computer Science Missouri University of Science & Technology hurson@mst.edu 1 Note, this unit will be covered in three lectures. In case you finish it earlier, then
More informationRegister Transfer and Micro-operations
Register Transfer Language Register Transfer Bus Memory Transfer Micro-operations Some Application of Logic Micro Operations Register Transfer and Micro-operations Learning Objectives After reading this
More informationCHAPTER 5 : Introduction to Intel 8085 Microprocessor Hardware BENG 2223 MICROPROCESSOR TECHNOLOGY
CHAPTER 5 : Introduction to Intel 8085 Hardware BENG 2223 MICROPROCESSOR TECHNOLOGY The 8085A(commonly known as the 8085) : Was first introduced in March 1976 is an 8-bit microprocessor with 16-bit address
More informationEGCP 1010 Digital Logic Design (DLD) Laboratory #6
EGCP 11 Digital Logic Design (DLD) Laboratory #6 Four by Four (4 x 4) Sorting Stack Prepared By: Alex Laird on October 1st, 2 Lab Partner: Ryan Morehart Objective: The goal of this laboratory is to expose
More informationDigital Fundamentals. Lab 6 2 s Complement / Digital Calculator
Richland College Engineering Technology Rev. 0. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. radbury Digital Fundamentals CETT 1425 Lab 6 2 s Complement / Digital Calculator Name: Date: Objectives:
More informationInternal architecture of 8086
Case Study: Intel Processors Internal architecture of 8086 Slide 1 Case Study: Intel Processors FEATURES OF 8086 It is a 16-bit μp. 8086 has a 20 bit address bus can access up to 220 memory locations (1
More informationDigital Systems. John SUM Institute of Technology Management National Chung Hsing University Taichung, ROC. December 6, 2012
Digital Systems John SUM Institute of Technology Management National Chung Hsing University Taichung, ROC December 6, 2012 Contents 1 Logic Gates 3 1.1 Logic Gate............................. 3 1.2 Truth
More informationMicrocomputer Architecture and Programming
IUST-EE (Chapter 1) Microcomputer Architecture and Programming 1 Outline Basic Blocks of Microcomputer Typical Microcomputer Architecture The Single-Chip Microprocessor Microprocessor vs. Microcontroller
More informationBinary Addition. Add the binary numbers and and show the equivalent decimal addition.
Binary Addition The rules for binary addition are 0 + 0 = 0 Sum = 0, carry = 0 0 + 1 = 0 Sum = 1, carry = 0 1 + 0 = 0 Sum = 1, carry = 0 1 + 1 = 10 Sum = 0, carry = 1 When an input carry = 1 due to a previous
More informationBinary Adders. Ripple-Carry Adder
Ripple-Carry Adder Binary Adders x n y n x y x y c n FA c n - c 2 FA c FA c s n MSB position Longest delay (Critical-path delay): d c(n) = n d carry = 2n gate delays d s(n-) = (n-) d carry +d sum = 2n
More informationDIGITAL SYSTEM DESIGN
DIGITAL SYSTEM DESIGN Prepared By: Engr. Yousaf Hameed Lab Engineer BASIC ELECTRICAL & DIGITAL SYSTEMS LAB DEPARTMENT OF ELECTRICAL ENGINEERING Digital System Design 1 Name: Registration No: Roll No: Semester:
More informationECE468 Computer Organization & Architecture. The Design Process & ALU Design
ECE6 Computer Organization & Architecture The Design Process & Design The Design Process "To Design Is To Represent" Design activity yields description/representation of an object -- Traditional craftsman
More informationLearning Outcomes. Spiral 2 2. Digital System Design DATAPATH COMPONENTS
2-2. 2-2.2 Learning Outcomes piral 2 2 Arithmetic Components and Their Efficient Implementations I know how to combine overflow and subtraction results to determine comparison results of both signed and
More informationNumber Systems. Readings: , Problem: Implement simple pocket calculator Need: Display, adders & subtractors, inputs
Number Systems Readings: 3-3.3.3, 3.3.5 Problem: Implement simple pocket calculator Need: Display, adders & subtractors, inputs Display: Seven segment displays Inputs: Switches Missing: Way to implement
More informationThe UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL Comp 541 Digital Logic and Computer Design Spring 2015 Lab #3: Designing an ALU Issued Wed 1/21/15; Due Wed 1/28/15 (11:59pm) This lab assignment consists
More informationMICROPROGRAMMED CONTROL
MICROPROGRAMMED CONTROL Hardwired Control Unit: When the control signals are generated by hardware using conventional logic design techniques, the control unit is said to be hardwired. Micro programmed
More informationChapter 10 Binary Arithmetics
27..27 Chapter Binary Arithmetics Dr.-Ing. Stefan Werner Table of content Chapter : Switching Algebra Chapter 2: Logical Levels, Timing & Delays Chapter 3: Karnaugh-Veitch-Maps Chapter 4: Combinational
More informationMemory Supplement for Section 3.6 of the textbook
The most basic -bit memory is the SR-latch with consists of two cross-coupled NOR gates. R Recall the NOR gate truth table: A S B (A + B) The S stands for Set to remember, and the R for Reset to remember.
More informationAddition and multiplication
Addition and multiplication Arithmetic is the most basic thing you can do with a computer, but it s not as easy as you might expect! These next few lectures focus on addition, subtraction, multiplication
More informationLab 7: RPN Calculator
University of Pennsylvania Department of Electrical and Systems Engineering ESE171 - Digital Design Laboratory Lab 7: RPN Calculator The purpose of this lab is: Purpose 1. To get familiar with the use
More informationALU Design. 1-bit Full Adder 4-bit Arithmetic circuits. Arithmetic and Logic Unit Flags. Add/Subtract/Increament/Decrement Circuit
LU Design -bit Full dder 4-bit rithmetic circuits dd/subtract/increament/decrement Circuit rithmetic and Logic Unit Flags Carry-Out, Sign, Zero, Overflow Shift and Rotate t Operations COE2 (Fall27) LU
More informationUniversity of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science. EECS 150 Spring 2000
University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Spring 2000 Lab 1 Introduction to Xilinx Design Software 1 Objectives In this
More informationEE 109 Unit 6 Binary Arithmetic
EE 109 Unit 6 Binary Arithmetic 1 2 Semester Transition Point At this point we are going to start to transition in our class to look more at the hardware organization and the low-level software that is
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationCS 261 Fall Mike Lam, Professor. Combinational Circuits
CS 261 Fall 2017 Mike Lam, Professor Combinational Circuits The final frontier Java programs running on Java VM C programs compiled on Linux Assembly / machine code on CPU + memory??? Switches and electric
More informationArithmetic Logic Unit (ALU)
Arithmetic Logic Unit (ALU) Introduction to Computer Yung-Yu Chuang with slides by Sedgewick & Wayne (introcs.cs.princeton.edu), Nisan & Schocken (www.nand2tetris.org) and Harris & Harris (DDCA) Let's
More informationCS 151 Midterm. Instructions: Student ID. (Last Name) (First Name) Signature
CS 151 Midterm Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 11 pages including this cover. 2. Write down your Student-Id on the top
More informationA True Single Cycle RISC Processor without Pipelining
1 A True Single Cycle RISC Processor without Pipelining Robert S. Plachno, VP of Audio Abstract This paper details the design of a embedded RISC controller used for mixed signal audio integrated circuits.
More information1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4]
HW 3 Answer Key 1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] You can build a NAND gate from tri-state buffers and inverters and thus you
More informationLecture #21 March 31, 2004 Introduction to Gates and Circuits
Lecture #21 March 31, 2004 Introduction to Gates and Circuits To this point we have looked at computers strictly from the perspective of assembly language programming. While it is possible to go a great
More informationOne and a half hours. Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE
One and a half hours Section A is COMPULSORY UNIVERSITY OF MANCHESTER SCHOOL OF COMPUTER SCIENCE Fundamentals of Computer Engineering Date: Thursday 21st January 2016 Time: 14:00-15:30 Answer BOTH Questions
More informationArithmetic Circuits. Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak.
Arithmetic Circuits Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak http://www.syssec.ethz.ch/education/digitaltechnik_14 Adapted from Digital Design and Computer Architecture, David Money
More informationThe UNIVERSITY of NORTH CAROLINA at CHAPEL HILL
The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL Comp 541 Digital Logic and Computer Design Fall 2014 Lab #3: Designing an ALU Issued Thu 9/4/14; Due Wed 9/10/14 (11:59pm) This lab assignment consists of
More information