Lecture 1: VHDL Quick Start. Digital Systems Design. Fall 10, Dec 17 Lecture 1 1

Transcription

1 Lecture 1: VHDL Quick Start Digital Systems Design Fall 10, Dec 17 Lecture 1 1

2 Objective Quick introduction to VHDL basic language concepts basic design methodology Use The Student s Guide to VHDL or The Designer s Guide to VHDL self-learning for more depth reference for project work Fall 10, Dec 17 Lecture 1 2

3 Introduction Hardware description languages (HDL) Language to describe hardware Two popular languages VHDL: Very High Speed Integrated Circuits Hardware Description Language Developed by DOD from 1983 IEEE Standard /1993/200x Based on the ADA and Pascal language Verilog IEEE Standard /2001/2005 Based on the C language Fall 10, Dec 17 Lecture 1 3

4 Why use an HDL? Question: How do we know that we have not made a mistake when we manually draw a schematic and connect components to implement a function? Answer: By describing the design in a high-level (=easy to understand) language, we can simulate our design before we manufacture it. This allows us to catch design errors, i.e., that the design does not work as we thought it would. Simulation guarantees that the design behaves as it should. Fall 10, Dec 17 Lecture 1 4

5 Applications of HDL Model and document digital systems Different levels of abstraction Behavioral, structural, etc. Verify design Synthesize circuits Convert from higher abstraction levels to lower abstraction levels Fall 10, Dec 17 Lecture 1 5

6 VHDL Design Styles (Architecture) VHDL Design Styles BEHAVIORAL DATAFLOW STRUCTURAL SYTHESIZABLE NON- SYNTHESIZABLE concurrent statements Gates Simple Comb. Logic components and interconnects sequential statements State machines Registers Complex Comb. Logic Test Benches Modeling IP

7 Describing Combinational Logic Using Dataflow VHDL

8 Dataflow VHDL Major instructions Concurrent statements concurrent signal assignment ( ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)

9 Dataflow VHDL Major instructions Concurrent statements concurrent signal assignment ( ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate)

10 Input-Output specification of circuit X Y Halfadder S Cout Example: Halfadder Inputs: X, Y Outputs: S, Cout VHDL description: entity Halfadder is port ( X : in bit; Y : in bit; S : out bit; Cout: out bit); end Halfadder; Fall 10, Dec 17 Lecture 1 10

11 VHDL entity entity Halfadder is port ( X : in bit; Y : in bit; S : out bit; Cout : out bit ); end Halfadder; Port names or Signal names Datatypes: Name In-built of the circuit User-defined User-defined Filename same as circuit name recommended XExample. Example: S Circuit Halfadder name: Halfadder my_ckt Y Filename: Halfadder.vhd my_ckt.vhd Cout Direction of port 3 main types: in: Input Note the out: absence Output of semicolon ; at inout: the end Bidirectional of the last signal and the presence at the end of the closing bracket Fall 10, Dec 17 Lecture 1 11

12 Built-in Datatypes Scalar (single valued) signal types: bit boolean integer Examples: A: in bit; G: out boolean; K: out integer range -2**4 to 2**4-1; Aggregate (collection) signal types: bit_vector: array of bits representing binary numbers signed: array of bits representing signed binary numbers Examples: D: in bit_vector(0 to 7); E: in bit_vector(7 downto 0); M: in signed (4 downto 0); --signed 5 bit_vector binary number Fall 10, Dec 17 Lecture 1 12

13 Dataflow VHDL: Half Adder X Y Cout S

14 Dataflow VHDL: Half Adder A Method is to use Logic Equations to Develop a Data Flow Description ARCHITECTURE half_adder_c OF Halfadder IS BEGIN Cout <= X AND Y; S <= X XOR Y; END half_adder_c;

15 Dataflow VHDL: Full Adder c i x i y i c i x i y i (a) Truth table c i s i s i = x i y i c i x i y i c i c i + 1 = x i y i + x i c i + y i c i (b) Karnaugh maps x i y i s i c i c i + 1 (c) Circuit

16 Full Adder Example ENTITY fulladd IS PORT ( x : IN bit; y : IN bit; cin : IN bit; s : OUT bit; cout : OUT bit) ; END fulladd ; ARCHITECTURE fulladd_dataflow OF fulladd IS BEGIN s <= x XOR y XOR cin ; cout <= (x AND y) OR (cin AND x)or(cin AND y); END fulladd_dataflow ;

17 Logic Operators Logic operators and or nand nor xor not xnor Logic operators precedence only in VHDL-93 and later Highest Lowest not and or nand nor xor xnor

18 No Implied Precedence Wanted: y = ab + cd Incorrect y <= a and b or c and d ; equivalent to y <= ((a and b) or c) and d ; equivalent to y = (ab + c)d Correct y <= (a and b) or (c and d) ;

19 VHDL features Case insensitive inputa, INPUTA and InputA are refer to same variable Comments -- until end of line If you want to comment multiple lines, -- need to be put at the beginning of every single line Statements are terminated by ; Signal assignment: <= User defined names: letters, numbers, underscores ( _ ) start with a letter Fall 10, Dec 17 Lecture 1 19

20 VHDL structure Library Definitions, constants Entity Interface Architecture Implementation, function Fall 10, Dec 17 Lecture 1 20

21 VHDL - Library Include library library IEEE; Define the library package used use IEEE.STD_LOGIC_1164.all; Define the library file used For example, STD_LOGIC_1164 defines 1 as logic high and 0 as logic low output <= 1 ; --Assign logic high to output Fall 10, Dec 17 Lecture 1 21

22 Data Types bit values: '0', '1' Boolean values: TRUE, FALSE integer values: -(2^31) to +(2^31-1) Std_logic values: 'U','X','1','0','Z','W','H','L','-' 'U' = uninitialized 'X' = unknown 'W' = weak 'X 'Z' = floating 'H'/'L' = weak '1'/'0 '-' = don't care Std_logic_vector (n downto 0); Std_logic_vector (0 upto n); Fall 10, Dec 17 Lecture 1 22

23 Signal All internal variables Signal X,Y : std_logic; Fall 10, Dec 17 Lecture 1 23

24 Final code LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY TEST IS PORT (A,B,C,D : IN STD_LOGIC; E : OUT STD_LOGIC); END TEST; ARCHITECTURE BEHAVIOR OF TEST IS SIGNAL X,Y : STD_LOGIC; BEGIN X <= (not A) AND B; Y <= C AND D; E <= X OR Y; END BEHAVIOR; Fall 10, Dec 17 Lecture 1 24

25 Concatenation SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0); a <= "0000"; b <= "1111"; c <= a & b; -- c = " " d <= '0' & " "; -- d <= " " e <= '0' & '0' & '0' & '0' & '1' & '1' & '1' & '1'; -- e <= " "

26 Rotations in VHDL a(3) a(2) a(1) a(0) a(2) a(1) a(0) a(3) a_rotl <= a(2 downto 0) & a(3);

27 Shifts in VHDL (zero-stuff) a(3) a(2) a(1) a(0) 0 a(2) a(1) a(0) a(3) a_shiftl <= a(2 downto 0) & 0 ; Be careful if doing sign-extension

28 Dataflow VHDL Major instructions Concurrent statements concurrent signal assignment conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) ( )

29 Conditional concurrent signal assignment When - Else target_signal <= value1 when condition1 else value2 when condition2 else... valuen-1 when conditionn-1 else valuen; Value N Value N Condition N-1. Value Value Target Signal Condition 2 Condition 1

30 Operators Relational operators = /= < <= > >= Logic and relational operators precedence Highest Lowest not = /= < <= > >= and or nand nor xor xnor

31 Priority of Logic and Relational Operators Incorrect compare a = bc when a = b and c else equivalent to when (a = b) and c else Correct when a = (b and c) else

32 Tri-state Buffer example LIBRARY ieee; USE ieee.std_logic_1164.all; input ena output ENTITY tri_state IS PORT ( ena: IN STD_LOGIC; input: IN STD_LOGIC_VECTOR(7 downto 0); output: OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END tri_state; ARCHITECTURE tri_state_dataflow OF tri_state IS BEGIN output <= input WHEN (ena = '0') ELSE (OTHERS => 'Z'); END tri_state_dataflow; OTHERS means all bits not directly specified, in this case all the bits.

33 Dataflow VHDL Major instructions Concurrent statements concurrent signal assignment conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) ( )

34 Selected concurrent signal assignment With Select-When with choice_expression select target_signal <= expression1 when choices_1, expression2 when choices_2,... expressionn when choices_n; expression1 expression2 choices_1 choices_2 target_signal expressionn choices_n choice expression

35 Allowed formats of choice_k - example WITH sel SELECT y <= a WHEN "000", b WHEN "011" to "110", c WHEN "001" "111", d WHEN OTHERS;

36 MLU Example

37 MLU: Block Diagram A A1 MUX_0 NEG_A MUX_1 MUX_2 IN0 IN1 IN2 IN3 OUTPUT Y1 Y SEL1 SEL0 B B1 MUX_4_1 NEG_Y MUX_3 NEG_B L1L0

38 MLU: Entity Declaration LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mlu IS PORT( NEG_A : IN STD_LOGIC; NEG_B : IN STD_LOGIC; NEG_Y : IN STD_LOGIC; A : IN STD_LOGIC; B : IN STD_LOGIC; L1 : IN STD_LOGIC; L0 : IN STD_LOGIC; Y : OUT STD_LOGIC ); END mlu;

39 MLU: Architecture Declarative Section ARCHITECTURE mlu_dataflow OF mlu IS SIGNAL A1 : STD_LOGIC; SIGNAL B1 : STD_LOGIC; SIGNAL Y1 : STD_LOGIC; SIGNAL MUX_0 : STD_LOGIC; SIGNAL MUX_1 : STD_LOGIC; SIGNAL MUX_2 : STD_LOGIC; SIGNAL MUX_3 : STD_LOGIC; SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);

40 MLU - Architecture Body BEGIN A1<= NOT A WHEN (NEG_A='1') ELSE A; B1<= NOT B WHEN (NEG_B='1') ELSE B; Y <= NOT Y1 WHEN (NEG_Y='1') ELSE Y1; MUX_0 <= A1 AND B1; MUX_1 <= A1 OR B1; MUX_2 <= A1 XOR B1; MUX_3 <= A1 XNOR B1; L <= L1 & L0; with (L) select Y1 <= MUX_0 WHEN "00", MUX_1 WHEN "01", MUX_2 WHEN "10", MUX_3 WHEN OTHERS; END mlu_dataflow;

41 Dataflow VHDL Major instructions Concurrent statements concurrent signal assignment conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) ( )

42 For Generate Statement For - Generate label: FOR identifier IN range GENERATE label: FOR identifier IN range GENERATE BEGIN {Concurrent Statements} END GENERATE [label];

43 PARITY Example

44 PARITY: Block Diagram

45 PARITY: Entity Declaration LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC ); END parity;

46 PARITY: Block Diagram xor_out(0) xor_out(1) xor_out(2) xor_out(3) xor_out(4) xor_out(5) xor_out(6) xor_out(7)

47 PARITY: Architecture ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0); BEGIN xor_out(0) <= parity_in(0); xor_out(1) <= xor_out(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); xor_out(7) <= xor_out(6) XOR parity_in(7); parity_out <= xor_out(7); END parity_dataflow;

48 PARITY: Architecture (2) ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN xor_out(0) <= parity_in(0); G2: FOR i IN 1 TO 7 GENERATE xor_out(i) <= xor_out(i-1) XOR parity_in(i); END GENERATE; parity_out <= xor_out(7); END parity_dataflow;

49 Combinational Logic Synthesis for Beginners

50 Simple Rules For combinational logic, use only concurrent statements concurrent signal assignment conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) ( )

51 Simple Rules For circuits composed of: simple logic operations (logic gates) simple arithmetic operations (addition, subtraction, multiplication) shifts/rotations by a constant Use concurrent signal assignment

52 Simple Rules For circuits composed of multiplexers decoders, encoders tri-state buffers Use: conditional concurrent signal assignment (when-else ) selected concurrent signal assignment (with-select-when)

53 Left versus Right Side Left side <= Right side <= when-else Expressions including: Internal signals (defined in a given architecture) Ports of the mode - out - inout with-select <= Expressions including: Internal signals (defined in a given architecture) Ports of the mode - in - inout

54 Signed and Unsigned Arithmetic

55 Arithmetic operations Synthesizable arithmetic operations: Addition: + Subtraction: - Comparisons: >, >=, <, <= Multiplication: * Division by a power of 2: /2**6 (equivalent to right shift) Shifts by a constant: SHL, SHR

56 Arithmetic operations The result of synthesis of an arithmetic operation is a - combinational circuit - without pipelining

57 IEEE Packages for Arithmetic std_logic_1164 Official IEEE standard Defines std_logic and std_logic_vector These are for logic operations (AND, OR) not for arithmetic operations (+, *) std_logic_arith Not official IEEE standard (created by Synopsys) Defines unsigned and signed data types, example: unsigned(7 downto 0) These are for arithmetic (+,*) not for logic (AND, OR) std_logic_unsigned Not official IEEE standard (created by Synopsys) Including this library tells compiler to treat std_logic_vector like unsigned type in certain cases For example, can perform addition on std_logic_vector Used as a helper to avoid explicit conversion functions std_logic_signed Not official IEEE standard (created by Synopsys) Same functionality as std_logic_unsigned except tells compiler to treat std_logic_vector like signed type in certain cases Do not use both std_logic_unsigned and std_logic_signed at the same time! If need to do both signed and unsigned arithmetic in same entity, do not use std_logic_unsigned or std_logic_signed packages do all conversions explicitly

58 Library inclusion When dealing with unsigned arithmetic use: LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; needed for using unsigned data type USE ieee.std_logic_unsigned.all; When dealing with signed arithmetic use: LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; need for using signed data type USE ieee.std_logic_signed.all; When dealing with both unsigned and signed arithmetic use: LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; Then do all type conversions explicitly

59 Unsigned and Signed Numbers N-bit unsigned number: unsigned(n-1 downto 0) Has a decimal range of 0 to 2 N -1 Example: unsigned(7 downto 0) has a decimal range 0 to 255 N-bit signed number (two s complement) number: signed(n-1 downto 0) Has a decimal range of -2 N-1 to 2 N-1-1 Asymmetric range due to non-redundant representation of 0 Example: signed(7 downto 0) has a decimal range -128 to 127 MSB indicates sign 0 in MSB means non-negative (0 or positive) 1 in MSB means negative To negate a two s complement number: invert all bits, add 1 to LSB 010 = 2 to get -2, invert then add 1 : = 110 Sign extension does not affect value Example: 010 and both represent decimal 2 Example: 110 and both represent decimal -2

60 Unsigned versus Signed Binary Unsigned value (decimal) Signed value (decimal) (zero) 0 (zero) (largest positive value) (largest negative value) (largest positive value) -1 (smallest negative value)

61 Addition of Unsigned Numbers A (2 bits) B (2 bits) SUM = A + B DECIMAL SUM BINARY = = = = = = = = = = = = = = = = SUM and CARRYOUT BINARY

62 Unsigned Addition: No Carryout library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity adder_unsigned is port( a : in STD_LOGIC_VECTOR(1 downto 0); b : in STD_LOGIC_VECTOR(1 downto 0); sum : out STD_LOGIC_VECTOR(1 downto 0)); end adder_unsigned; architecture dataflow of adder_unsigned is begin sum <= a + b; end dataflow;

63 Unsigned Addition: With Carryout library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity adder_unsigned_carryout is port( a : in STD_LOGIC_VECTOR(1 downto 0); b : in STD_LOGIC_VECTOR(1 downto 0); sum : out STD_LOGIC_VECTOR(1 downto 0); cout : out STD_LOGIC ); end adder_unsigned_carryout; architecture dataflow of adder_unsigned_carryout is signal tempsum : std_logic_vector(2 downto 0); begin tempsum <= ('0' & a) + ('0' & b); -- pad with 0 before addition sum <= tempsum(1 downto 0); cout <= tempsum(2); end dataflow;

64 Addition of Signed Numbers A (2 bits) B (2 bits) SUM = A + B DECIMAL SUM BINARY = = = = = = = = = = = = = = = = SUM and CARRYOUT BINARY

65 Signed Addition: No Carryout library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_SIGNED.all; entity adder_signed is port( a : in STD_LOGIC_VECTOR(1 downto 0); b : in STD_LOGIC_VECTOR(1 downto 0); sum : out STD_LOGIC_VECTOR(1 downto 0)); end adder_signed; architecture dataflow of adder_signed is begin sum <= a + b; end dataflow;

66 Signed Addition: With Carryout library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_SIGNED.all; entity adder_signed_carryout is port( a : in STD_LOGIC_VECTOR(1 downto 0); b : in STD_LOGIC_VECTOR(1 downto 0); sum : out STD_LOGIC_VECTOR(1 downto 0); cout : out STD_LOGIC ); end adder_signed_carryout; architecture dataflow of adder_signed_carryout is signal tempsum : std_logic_vector(2 downto 0); begin tempsum <= (a(1) & a) + (b(1) & b); -- sign extend BEFORE addition, very important sum <= tempsum(1 downto 0); cout <= tempsum(2); end dataflow;

67 Multiplication N-bit unsigned number x M-bit unsigned number results in N+M bit unsigned number Example: 3 bits x 4 bits = 7 bits 111 (7) x 1111 (15) = (105) most positive x most positive needs 7 bits N-bit signed number x M-bit signed number results in N+M bit unsigned number Example: 3 bits x 4 bits 100 (-4) x 1000 (-8) = (+32) most negative x most negative needs 7 bits (this is the only scenario which requires the full output range) 100 (-4) x 0111 (7) = [1] (-28) most negative x most positive needs 6 bits, [ ] indicates not necessary 011 (3) x 0111 (7) = [0] (21) most positive x most positive needs 6 bits 011 (3) x 1000 (-8) = [1] (-24) most positive x most negative needs 6 bits

68 Multiplication of signed and unsigned numbers (1) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; Since using both signed and unsigned data types, don t use std_logic_unsigned/signed. Do all conversions by hand. entity multiply is port( a : in STD_LOGIC_VECTOR(15 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); cu : out STD_LOGIC_VECTOR(23 downto 0); cs : out STD_LOGIC_VECTOR(23 downto 0) ); end multiply; architecture dataflow of multiply is SIGNAL sa: SIGNED(15 downto 0); SIGNAL sb: SIGNED(7 downto 0); SIGNAL sres: SIGNED(23 downto 0); SIGNAL ua: UNSIGNED(15 downto 0); SIGNAL ub: UNSIGNED(7 downto 0); SIGNAL ures: UNSIGNED(23 downto 0);

69 Multiplication of signed and unsigned numbers (2) begin -- signed multiplication sa <= SIGNED(a); sb <= SIGNED(b); sres <= sa * sb; cs <= STD_LOGIC_VECTOR(sres); -- unsigned multiplication ua <= UNSIGNED(a); ub <= UNSIGNED(b); ures <= ua * ub; cu <= STD_LOGIC_VECTOR(ures); end dataflow;

70 VHDL Design Styles (Architecture) VHDL Design Styles BEHAVIORAL DATAFLOW STRUCTURAL SYTHESIZABLE NON- SYNTHESIZABLE concurrent statements Gates Simple Comb. Logic components and interconnects sequential statements State machines Registers Complex Comb. Logic Test Benches Modeling IP

71 HalfAdder with std_logic Fall 10, Dec 17 Lecture 1 71

72 Full Adder using two Half Adders Fall 10, Dec 17 Lecture 1 72

73 Component statement Fall 10, Dec 17 Lecture 1 73

74 Generic statement The generic statement allows components to be parameterized, mostly with certain timing values like delays and size values like the size of an adder (8-bit, 16-bit, 32- bit, etc.) being designed. The generic statement is part of the entity description of a module/component. Fall 10, Dec 17 Lecture 1 74

75 Generic example Fall 10, Dec 17 Lecture 1 75

76 How to use a parameterized block? Fall 10, Dec 17 Lecture 1 76