Lecture 7. Summary of two-level combinational-logic. Ways of specifying circuits. Solving combinational design problems. Verilog versus VHDL

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1 Lecture 7 Summary of two-level combinational-logic Logistics Homework due today Homework out today due next Wednesday First midterm a week Friday: Friday Jan 0 Will cover up to the of Multiplexers/DeMultiplexers Last lecture K-Maps Today Verilog Structural constructs Describing combinational circuits Logic functions and truth tables ND, OR, uf,, NND, NOR, OR, NOR Minimal set xioms and theorems of oolean algebra Proofs by re-writing Proofs by truth table Gate logic Networks of oolean functions NND/NOR conversion and de Morgan s theorem anonical forms Two-level forms Incompletely specified functions (don t cares) Simplification Two-level simplification (K-maps) Solving combinational design problems Ways of specifying circuits Step : Understand the problem Identify the inputs and outputs Draw a truth table Step : Simplify the logic Draw a K-map Write a simplified oolean expression SOP or POS Use don t cares Step : Implement the design Logic gates and/or Verilog Schematics Structural description Describe circuit as interconnected elements uild complex circuits using hierarchy Large circuits are unreadable HDLs Hardware description languages Not programming languages Parallel languages tailored to digital design Synthesize code to produce a circuit 4 Hardware description languages (HDLs) Verilog versus VHDL bel (~98) Developed by Data-I/O Targeted to PLDs (programmable logic devices) Limited capabilities (can do state machines) Verilog (~985) Developed by Gateway (now part of adence) Syntax similar to Moved to public domain in 990 VHDL (~987) DoD (Department of Defence) sponsored Syntax similar to da oth I standard languages Most tools support both Verilog is simpler Less syntax, fewer constructs VHDL is more structured an be better for large, complex systems etter modularization 5 6

2 and synthesis and synthesis (con t) xecute a design to verify correctness Synthesis Generate a physical implementation from HDL code Models what a circuit does Multiply is *, ignoring implementation options an include static timing llows you to test design options HDL Description Functional Validation Synthesis Gate or Transistor Description Functional/ Timing Validation Physical Implementation Real hip! Synthesis onverts your code to a netlist an simulate synthesized design Tools map your netlist to hardware and synthesis in the S curriculum S70: Learn simulation S467: Learn synthesis 7 8 Specifying circuits in Verilog ou provide an environment Using non-circuit constructs ctive-hdl waveforms, Read files, print Using Verilog simulation code test fixture Test Fixture (Specification) ircuit Description (Synthesizable) Note: We will ignore timing and test benches until later 9 There are three major styles Instances and wires ontinuous assignments always blocks Structural wire ; and g(,,); not g(,); or g(,,); wire ; assign = & ; assign = ~; assign = ; g g ehavioral g reg,, ; ( or or ) = & ; = ~; = ; 0 Data types Data types that do not exist Values on a wire 0,, x (unknown or conflict), z (tristate or unconnected) Vectors [:0] vector of 4 bits: [], [], [], [0] Unsigned integer value Indices must be constants oncatenating bits/vectors e.g. sign ext [7:0] = {[], [], [], [], [:0]}; [7:0] = {4{[]}, [:0]}; Style: Use a[7:0] = b[7:0] + c[7:0] Not a = b + c; Legal syntax: = &[6:7]; // logical and of bits 6 and 7 of Structures Pointers Objects Recursive types (Remember, Verilog is not or Java or Lisp or!)

3 Numbers Operators Format: <sign><size><base format><number> 4 Decimal number 4 b 4-bit s complement binary of 00 (is 0) b0000_000_00 bit binary number (_ is ignored) h046 -digit (-bit) hexadecimal number Verilog values are unsigned [4:0] = [:0] + [:0]; if = 00 (6) and = 00( 6), then = 0000 (not 00000) is zero-padded, not sign-exted Similar to operators 4 Two abstraction mechanisms asic building blocks: Modules Modules More structural Heavily used in 70 and real Verilog code Functions More behavioral Used to some extent in real Verilog, but not much in 70 Instanced into a design (like macros) Never called Illegal to nest module defs. Modules execute in parallel Names are case sensitive // for comments Name can t with a number Use wires for connections and, or, not are keywords ll keywords are lower case Gate declarations (and, or, etc) List outputs first Inputs second g g g // first simple example module smpl (,,,,); input,,; output,; wire and g(,,); not g(,); or g(,,); module 5 6 Modules are circuit components Structural Verilog Module has ports xternal connections,,,, in example Port types input output inout (tristate) Use assign statements for oolean expressions and & or not ~ g g g // previous example as a // oolean expression module smpl (,,,,); input,,; output,; assign = (&) ~; assign = ~; module 7 module xor_gate (out,a,b); input a,b; output out; wire abar, bbar, t, t; not inva (abar,a); not invb (bbar,b); and and (t,abar,b); and and (t,bbar,a); or or (out,t,t); module abar a 4 inva b bbar b 5 invb a basic gates (keywords): and, or, nand, nor buf, not, xor, xnor and and t t 8 or out 8

4 ehavioral Verilog ehavioral 4-bit adder Describe circuit behavior Not implementation in module full_addr (Sum,out,,,in); input,, in; output Sum, out; assign {out, Sum} = + + in; module dder Sum out module add4 (SUM, OVR,, ); input [:0] ; input [:0] ; output [:0] SUM; output OVR; assign {OVR, SUM[:0]} = [:0] + [:0]; module [:0] is a 4-wire bus labeled it is the MS it 0 is the LS {out, Sum} is a concatenation an also write [0:] it 0 is the MS it is the LS uses are implicitly connected If you write US[:], US[:0] They become part of US[:0] 9 0 ontinuous assignment xample: comparator ssignment is continuously evaluated orresponds to a logic gate ssignments execute in parallel oolean operators (~ for bit-wise negation) assign = ( & ~Z); assign [:0] = 4'b0; assign [5:0] = 6'h00ff; assign # {out, Sum[:0]} = [:0] + [:0] + in; Gate delay (used by simulator) bits can assume four values (0,,, Z) variables can be n-bits wide (MS:LS) arithmetic operator multiple assignment (concatenation) module ompare (qual, larger, larger,, ); input, ; output qual, larger, larger; assign qual = ( & ) (~ & ~); assign larger = ( & ~); assign larger = (~ & ); module Top-down design and bottom-up design are both okay Module ordering doesn t matter because modules execute in parallel omparator example (con t) Sequential assigns don t make any sense // Make a 4-bit comparator from 4 -bit comparators module ompare4(qual, larger, larger, 4, 4); input [:0] 4, 4; output qual, larger, larger; wire e0, e, e, e, l0, l, l, l, 0, l, l, l; ompare cp0(e0, l0, l0, 4[0], 4[0]); ompare cp(e, l, l, 4[], 4[]); ompare cp(e, l, l, 4[], 4[]); ompare cp(e, l, l, 4[], 4[]); assign qual = (e0 & e & e & e); assign larger = (l (l & e) (l & e & e) (l0 & e & e & e)); assign larger = (~larger & ~qual); module assign = ( & ~Z); assign = W ; assign = & Z; assign = ( & ~Z); assign = W ; assign = & Z; Reusing a variable on the left side of several assign statements is not allowed yclic depencies also are bad deps on which deps on which deps on 4

5 Functions lways locks Don t forget variables in this list!! * can be used to represent every value change Use functions for complex combinational logic module and_gate (out, in, in); input in, in; output out; assign out = myfunction(in, in); function myfunction; input in, in; myfunction = in & in; function module enefit: Functions force a result ompiler will fail if function does not generate a result 5 reg,, ; (W or or or Z) = ( & ~Z); = W ; = & Z; if ( & ) = Z; = W ; Variables that appear on the left hand side in an always block must be declared as reg s Sensitivity list: block is executed each time one of them changes value Statements in an always block are executed in sequence ll variables must be assigned on every control path!!! (otherwise you get the dreaded inferred latch ) 6 Sequential Verilog-- locking and non-blocking assignments Sequential Verilog-- ssignments- watch out! locking assignments (Q = ) Variable is assigned immediately New value is used by subsequent statements Non-blocking assignments (Q <= ) Variable is assigned after all scheduled statements are executed Value to be assigned is computed but saved for later parallel assignment Usual use: Register assignment Registers simultaneously take new values after the clock edge xample: Swap locking versus Non-blocking reg,, D; clk) = ; = ; D = ; reg,, D; clk) <= ; <= ; D <= ; LK) temp = ; = ; = temp; LK) <= ; <= ; 7 8 Verilog tips Do not write -code Think hardware, not algorithms Verilog is inherently parallel ompilers don t map algorithms to circuits well Do describe hardware circuits First draw a dataflow diagram Then start coding References Tutorial and reference manual are found in ctivehdl help Starter s Guide to Verilog 00 by Michael iletti copies for borrowing in hardware lab 9