CENG 241 Digital Design 1


 Winfred Golden
 3 years ago
 Views:
Transcription
1 CENG 241 Digital Design 1 Lecture 5 Amirali Baniasadi
2 This Lecture Lab Review of last lecture: GateLevel Minimization Continue Chapter 3:XOR functions, Hardware Description Language HW 2: Due Thursday May 31st. FIRST MIDTERM: THURSDAY JUNE 14, IN CLASS. 2
3 Midterm 1 CENG 241 Digital Design 1 Midterm #1 (sample) Important Note: Show your work for all sections. Consider the following Boolean function: F(A, B, C, D, E) = Σ (8,10,13,15,16,18,21,23,25,27) and d(a, B, C, D, E) = Σ (0,2,5,7,29,31) Use the 1 s in the map to find the simplest Boolean function and implement it using only NAND gates. Draw the logic.(10 points) Use the 0 s in the map to find the simplest Boolean function and implement it using only NOR gates. Draw the logic. (10 points) NOTE: Each gate may have up to 3 inputs. 3
4 Multilevel NAND circuits Sum of Products and Product of Sums result in two level designs Not all designs are twolevel e.g., F=A.(C.D+B)+B.C How do we convert multilevel circuits to NAND circuits? Rules 1Convert all ANDs to NAND gates with ANDinvert symbol 2Convert all Ors to NAND gates with invertor symbols 3Check the bubbles, insert bubble if not compensated 4
5 Multilevel NAND circuits B BC 5
6 Multilevel NAND circuits 6
7 ExclusiveOR Function X XOR Y = X.Y+X.Y two input XOR IS 1 if both inputs are not similar 7
8 Threeinput XOR Function F = A XOR B XOR C Multiple input XOR is 1 only if the number of 1 variables is odd: ODD function 8
9 ODD Function Implementation 9
10 Fourinput XOR Function F detects odd number of 1s, F detects even number of 1 s 10
11 Parity Generation and Checking Parity bit: extra bit to ensure correct transmission of data Parity bit is included in the message to make the number of 1s either odd (odd parity) or even (even parity). We can use XOR to see if the number of 1 s is odd. We can use XORinvert to see if the number of 1 s is even. We include the XOR output in the message Later at receiver we check the number of 1 bits to see if the transmission is correct. 11
12 Parity Generation and Checking circuits 12
13 Hardware Description Language Hardware Description Language explains hardware in textual form Represents digital circuits HDL has two applications: 1Simulation: represents structure and behavior of digital circuits 2Synthesis:Derives a list of components and interconnections from HDL. Two examples of HDL: VHDL, Verilog We use verilog since its easier to learn. 13
14 Hardware Description Languageexample //HDL Example 31 // //Description of the simple circuit of Fig module smpl_circuit(a,b,c,x,y); input A,B,C; output x,y; wire e; and g1(e,a,b); not g2(y, C); or g3(x,e,y); endmodule 14
15 Hardware Description Languageexample How do we take into account gate delays? //HDL Example 32 // //Description of circuit with delay module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,a,b); or #(20) g3(x,e,y); not #(10) g2(y,c); endmodule 15
16 Test bench To simulate circuits we need input signals. The HDL description that provides the input/stimulus is called a test bench 16
17 Test bench example //HDL Example 33 // //Stimulus for simple circuit module stimcrct; reg A,B,C; wire x,y; circuit_with_delay cwd(a,b,c,x,y); initial begin A = 1'b0; B = 1'b0; C = 1'b0; #100 A = 1'b1; B = 1'b1; C = 1'b1; #100 $finish; end endmodule //Description of circuit with delay module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,a,b); or #(20) g3(x,e,y); not #(10) g2(y,c); endmodule 17
18 Test bench example simulation output 18
19 Combinational Logic Combinational Logic: Output only depends on current input Sequential Logic:Output depends on current and previous inputs 19
20 Design Procedure 1.The number of inputs and outputs? 2.Derive the truth table 3.Obtain the Boolean Function 4.Draw the logic diagram, verify correctness 20
21 Design Procedure example Binary AdderSubtractor Basic block is a half adder. Half Adder Design: 1.needs 2 inputs 2 outputs 2. Truth Table: x y C S S=x y+xy C=xy 21
22 Half Adder circuit 22
23 Full Adder? Truth Table: x y z C S
24 Full Adder Map 24
25 Full Adder Circuit 25
26 Full Adder Circuit Half adder? 26
27 4bit Adder Circuit But this is slow... 27
28 Summary Implementation, XOR, Parity Checking, HDL Reading up to page 121end of chapter 3 Homework 2: problems 311, 315, 320, 323 and 324 from textbook 28
NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 2 COMBINATIONAL LOGIC Combinational circuits Analysis
More informationDigital Logic Design. Outline
Digital Logic Design GateLevel Minimization CSE32 Fall 2 Outline The Map Method 2,3,4 variable maps 5 and 6 variable maps (very briefly) Product of sums simplification Don t Care conditions NAND and NOR
More informationGateLevel Minimization
MEC520 디지털공학 GateLevel Minimization JeeHwan Ryu School of Mechanical Engineering GateLevel MinimizationThe Map Method Truth table is unique Many different algebraic expression Boolean expressions may
More informationEEL 4783: HDL in Digital System Design
EEL 4783: HDL in Digital System Design Lecture 1: Introduction* Prof. Mingjie Lin 1 Overview What is an digital embedded system? Why HDL (Hardware Description Language)? Why take this course? Class mechanics
More informationChapter 3. GateLevel Minimization. Outlines
Chapter 3 GateLevel Minimization Introduction The Map Method FourVariable Map FiveVariable Map Outlines Product of Sums Simplification Don tcare Conditions NAND and NOR Implementation Other TwoLevel
More informationHardware Description Languages (HDLs) Verilog
Hardware Description Languages (HDLs) Verilog Material from Mano & Ciletti book By Kurtulus KULLU Ankara University What are HDLs? A Hardware Description Language resembles a programming language specifically
More informationCadence Verilog Tutorial Windows XP machine with Exceed X Emulator
Cadence Verilog Tutorial Windows XP machine with Exceed X Emulator This tutorial will serve as an introduction to the use of the Cadence Verilog simulation environment and as a design tool. The Cadence
More informationEE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE
EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE 1 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationIntroduction to Verilog
Introduction to Verilog COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Hardware Description Language Logic Simulation versus Synthesis
More informationChapter 4. Combinational Logic. Dr. AbuArqoub
Chapter 4 Combinational Logic Introduction N Input Variables Combinational Logic Circuit M Output Variables 2 Design Procedure The problem is stated 2 The number of available input variables & required
More informationUNIT II  COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination
More informationQUESTION BANK FOR TEST
CSCI 2121 Computer Organization and Assembly Language PRACTICE QUESTION BANK FOR TEST 1 Note: This represents a sample set. Please study all the topics from the lecture notes. Question 1. Multiple Choice
More informationFPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block  Gates Digital Design : Bottom Up Approach Gates > Flip Flops Digital
More informationCombinational Logic Circuits
Combinational Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has
More informationHardware description languages
Specifying digital circuits Schematics (what we ve done so far) Structural description Describe circuit as interconnected elements Build complex circuits using hierarchy Large circuits are unreadable Hardware
More informationGateLevel Minimization
GateLevel Minimization Mano & Ciletti Chapter 3 By Suleyman TOSUN Ankara University Outline Intro to GateLevel Minimization The Map Method 2345 variable map methods ProductofSums Method Don t care
More informationVerilog for Combinational Circuits
Verilog for Combinational Circuits LanDa Van ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2014 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/
More informationChapter 4 Combinational Logic
4.1 Introduction Chapter 4 Combinational Logic Logic circuit for digital systems may be broadly classified as combinational or sequential. Combinational logic circuits are made by logic gates whose output
More informationCombinational Logic. Prof. Wangrok Oh. Dept. of Information Communications Eng. Chungnam National University. Prof. Wangrok Oh(CNU) 1 / 93
Combinational Logic Prof. Wangrok Oh Dept. of Information Communications Eng. Chungnam National University Prof. Wangrok Oh(CNU) / 93 Overview Introduction 2 Combinational Circuits 3 Analysis Procedure
More informationCombinational Circuits
Combinational Circuits Combinational circuit consists of an interconnection of logic gates They react to their inputs and produce their outputs by transforming binary information n input binary variables
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationLAB #1 BASIC DIGITAL CIRCUIT
LAB #1 BASIC DIGITAL CIRCUIT OBJECTIVES 1. To study the operation of basic logic gates. 2. To build a logic circuit from Boolean expressions. 3. To introduce some basic concepts and laboratory techniques
More informationElectronic Engineering Part 1 Laboratory Experiment. Digital Circuit Design 1 Combinational Logic. (3 hours)
Electronic Engineering Part 1 Laboratory Experiment Digital Circuit Design 1 Combinational Logic (3 hours) 1. Introduction These days most signal processing is done digitally. Electronic signals (representing
More informationDepartment of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic
Department of Electrical Engineering McGill University ECSE 221 Introduction to Computer Engineering Assignment 2 Combinational Logic Question 1: Due October 19 th, 2009 A convenient shorthand for specifying
More informationDate Performed: Marks Obtained: /10. Group Members (ID):. Experiment # 09 MULTIPLEXERS
Name: Instructor: Engr. Date Performed: Marks Obtained: /10 Group Members (ID):. Checked By: Date: Experiment # 09 MULTIPLEXERS OBJECTIVES: To experimentally verify the proper operation of a multiplexer.
More informationLast Name Student Number. Last Name Student Number
University of Toronto Faculty of Applied Science and Engineering Department of Electrical and Computer Engineering Midterm Examination ECE 241F  Digital Systems Wednesday October 13, 2004, 6:00pm [5]
More informationLogic Gates and Boolean Algebra ENT263
Logic Gates and Boolean Algebra ENT263 Logic Gates and Boolean Algebra Now that we understand the concept of binary numbers, we will study ways of describing how systems using binary logic levels make
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Supplementary Examinations, February 2007 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science
More informationLecture 8: Combinational Verilog. CSE 370, Autumn 2007 Benjamin Ylvisaker. Where We Are. Last lecture: Minimization with K!maps
Lecture 8: Combinational Verilog CSE 370, Autumn 2007 Benjamin Ylvisaker Where We Are Last lecture: Minimization with K!maps This lecture: Combinational Verilog Next lecture: ROMs, PLAs and PALs, oh my!
More informationDigital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
More informationGet Free notes at ModuleI One s Complement: Complement all the bits.i.e. makes all 1s as 0s and all 0s as 1s Two s Complement: One s complement+1 SIGNED BINARY NUMBERS Positive integers (including zero)
More informationCombinational Logic II
Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary AdderSubtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic
More informationLogic and Computer Design Fundamentals. Chapter 2 Combinational Logic Circuits. Part 3 Additional Gates and Circuits
Logic and Computer Design Fundamentals Chapter 2 Combinational Logic Circuits Part 3 Additional Gates and Circuits Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View
More informationCode No: R Set No. 1
Code No: R059210504 Set No. 1 II B.Tech I Semester Regular Examinations, November 2006 DIGITAL LOGIC DESIGN ( Common to Computer Science & Engineering, Information Technology and Computer Science & Systems
More informationEECS 3201: Digital Logic Design Lecture 4. Ihab Amer, PhD, SMIEEE, P.Eng.
EECS 32: Digital Logic Design Lecture 4 Ihab Amer, PhD, SMIEEE, P.Eng. What is a HDL? A highlevel computer language that can describe digital systems in tetual form Two applications of HDL processing:
More informationMidterm Exam Review. CS 2420 :: Fall 2016 Molly O'Neil
Midterm Exam Review CS 2420 :: Fall 2016 Molly O'Neil Midterm Exam Thursday, October 20 In class, pencil & paper exam Closed book, closed notes, no cell phones or calculators, clean desk 20% of your final
More informationReview. EECS Components and Design Techniques for Digital Systems. Lec 05 Boolean Logic 9/404. Seq. Circuit Behavior. Outline.
Review EECS 150  Components and Design Techniques for Digital Systems Lec 05 Boolean Logic 9404 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley Design flow
More informationGateLevel Minimization
GateLevel Minimization ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2011 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines The Map Method
More informationObjectives: 1 Bolean Algebra. Eng. Ayman Metwali
Objectives: Chapter 3 : 1 Boolean Algebra Boolean Expressions Boolean Identities Simplification of Boolean Expressions Complements Representing Boolean Functions 2 Logic gates 3 Digital Components 4
More informationCprE 281: Digital Logic
CprE 281: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Intro to Verilog CprE 281: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
More informationGate Level Minimization Map Method
Gate Level Minimization Map Method Complexity of hardware implementation is directly related to the complexity of the algebraic expression Truth table representation of a function is unique Algebraically
More informationDepartment of Computer Science & Engineering. Lab Manual DIGITAL LAB. Class: 2nd yr, 3rd sem SYLLABUS
Department of Computer Science & Engineering Lab Manual 435 DIGITAL LAB Class: 2nd yr, 3rd sem SYLLABUS. Verification of Boolean theorems using digital logic gates. 2. Design and implementation of code
More informationComputer Organization
Computer Organization (Logic circuits design and minimization) KR Chowdhary Professor & Head Email: kr.chowdhary@gmail.com webpage: krchowdhary.com Department of Computer Science and Engineering MBM Engineering
More informationCS429: Computer Organization and Architecture
CS429: Computer Organization and Architecture Dr. Bill Young Department of Computer Sciences University of Texas at Austin Last updated: January 2, 2018 at 11:23 CS429 Slideset 5: 1 Topics of this Slideset
More informationDr. S. Shirani COE2DI4 Midterm Test #1 Oct. 14, 2010
Dr. S. Shirani COE2DI4 Midterm Test #1 Oct. 14, 2010 Instructions: This examination paper includes 9 pages and 20 multiplechoice questions starting on page 3. You are responsible for ensuring that your
More information數位系統 Digital Systems 朝陽科技大學資工系. Speaker: FuwYi Yang 楊伏夷. 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象, 視之不可見者曰夷
數位系統 Digital Systems Department of Computer Science and Information Engineering, Chaoyang University of Technology 朝陽科技大學資工系 Speaker: FuwYi Yang 楊伏夷 伏夷非征番, 道德經察政章 (Chapter 58) 伏者潛藏也道紀章 (Chapter 14) 道無形象,
More informationChapter 3. Boolean Algebra and Digital Logic
Chapter 3 Boolean Algebra and Digital Logic Chapter 3 Objectives Understand the relationship between Boolean logic and digital computer circuits. Learn how to design simple logic circuits. Understand how
More informationregister:a group of binary cells suitable for holding binary information flipflops + gates
9 차시 1 Ch. 6 Registers and Counters 6.1 Registers register:a group of binary cells suitable for holding binary information flipflops + gates control when and how new information is transferred into the
More informationCSE303 Logic Design II Laboratory 01
CSE303 Logic Design II Laboratory 01 # Student ID Student Name Grade (10) 1 Instructor signature 2 3 4 5 Delivery Date 1 / 15  Experiment 01 (Half adder) Objectives In the first experiment, a half adder
More informationTopics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
More informationCombinational Circuits
Combinational Circuits Jason Filippou CMSC250 @ UMCP 06022016 ason Filippou (CMSC250 @ UMCP) Circuits 06022016 1 / 1 Outline ason Filippou (CMSC250 @ UMCP) Circuits 06022016 2 / 1 Hardware design
More informationwww.vidyarthiplus.com Question Paper Code : 31298 B.E./B.Tech. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2013. Third Semester Computer Science and Engineering CS 2202/CS 34/EC 1206 A/10144 CS 303/080230012DIGITAL
More informationSoftware Engineering 2DA4. Slides 2: Introduction to Logic Circuits
Software Engineering 2DA4 Slides 2: Introduction to Logic Circuits Dr. Ryan Leduc Department of Computing and Software McMaster University Material based on S. Brown and Z. Vranesic, Fundamentals of Digital
More information(ii) Simplify and implement the following SOP function using NOR gates:
DHANALAKSHMI COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EE6301 DIGITAL LOGIC CIRCUITS UNIT I NUMBER SYSTEMS AND DIGITAL LOGIC FAMILIES PART A 1. How can an OR gate be
More informationAssignment (36) Boolean Algebra and Logic Simplification  General Questions
Assignment (36) Boolean Algebra and Logic Simplification  General Questions 1. Convert the following SOP expression to an equivalent POS expression. 2. Determine the values of A, B, C, and D that make
More informationChapter 2 Boolean algebra and Logic Gates
Chapter 2 Boolean algebra and Logic Gates 2. Introduction In working with logic relations in digital form, we need a set of rules for symbolic manipulation which will enable us to simplify complex expressions
More informationBawar Abid Abdalla. Assistant Lecturer Software Engineering Department Koya University
Logic Design First Stage Lecture No.5 Boolean Algebra Bawar Abid Abdalla Assistant Lecturer Software Engineering Department Koya University Boolean Operations Laws of Boolean Algebra Rules of Boolean Algebra
More informationENDTERM EXAMINATION
(Please Write your Exam Roll No. immediately) ENDTERM EXAMINATION DECEMBER 2006 Exam. Roll No... Exam Series code: 100919DEC06200963 Paper Code: MCA103 Subject: Digital Electronics Time: 3 Hours Maximum
More informationChapter Three. Digital Components
Chapter Three 3.1. Combinational Circuit A combinational circuit is a connected arrangement of logic gates with a set of inputs and outputs. The binary values of the outputs are a function of the binary
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
More informationNinput EXNOR gate. Noutput inverter. Ninput NOR gate
Hardware Description Language HDL Introduction HDL is a hardware description language used to design and document electronic systems. HDL allows designers to design at various levels of abstraction. It
More informationECEN 449 Microprocessor System Design. Verilog. Texas A&M University
ECEN 449 Microprocessor System Design Verilog 1 Objectives of this Lecture Unit Get a feel for the basics of Verilog The focus of this unit will be along two separate but equally relevant axes We will
More informationstructure syntax different levels of abstraction
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
More informationHere is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
More informationObjectives: 1. Design procedure. 2. Fundamental circuits. 1. Design procedure
Objectives: 1. Design procedure. 2. undamental circuits. 1. Design procedure Design procedure has five steps: o Specification. o ormulation. o Optimization. o Technology mapping. o Verification. Specification:
More informationSummary. Boolean Addition
Summary Boolean Addition In Boolean algebra, a variable is a symbol used to represent an action, a condition, or data. A single variable can only have a value of or 0. The complement represents the inverse
More informationEric Blasko Dr. Tong Yu CSE310 digital logic Spring 2018 Homework 3, due 5/14/2018 ( Mon ) 12 pm
Eric Blasko Dr. Tong Yu CSE310 digital logic Spring 2018 Homework 3, due 5/14/2018 ( Mon ) 12 pm 1. (15 points) Write a Verilog program that simulates the outputs of graycodetobinarycode converter. First
More informationCSE140L: Components and Design Techniques for Digital Systems Lab. Verilog HDL. Instructor: Mohsen Imani UC San Diego. Source: Eric Crabill, Xilinx
CSE4L: Components and Design Techniques for Digital Systems Lab Verilog HDL Instructor: Mohsen Imani UC San Diego Source: Eric Crabill, Xilinx System Tasks The $ sign denotes Verilog system tasks, there
More informationChapter 2. Boolean Algebra and Logic Gates
Chapter 2. Boolean Algebra and Logic Gates Tong In Oh 1 Basic Definitions 2 3 2.3 Axiomatic Definition of Boolean Algebra Boolean algebra: Algebraic structure defined by a set of elements, B, together
More informationECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7
More informationExperiment 3: Logic Simplification
Module: Logic Design Name:... University no:.. Group no:. Lab Partner Name: Mr. Mohamed ElSaied Experiment : Logic Simplification Objective: How to implement and verify the operation of the logical functions
More informationKING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT
KING FAHD UNIVERSITY OF PETROLEUM & MINERALS COMPUTER ENGINEERING DEPARTMENT COE 202: Digital Logic Design Term 162 (Spring 2017) Instructor: Dr. Abdulaziz Barnawi Class time: U.T.R.: 11:0011:50AM Class
More informationR a) Simplify the logic functions from binary to seven segment display code converter (8M) b) Simplify the following using Tabular method
SET  1 1. a) Convert the decimal number 250.5 to base 3, base 4 b) Write and prove demorgan laws c) Implement two input EXOR gate from 2 to 1 multiplexer (3M) d) Write the demerits of PROM (3M) e) What
More informationChapter 2 Basic Logic Circuits and VHDL Description
Chapter 2 Basic Logic Circuits and VHDL Description We cannot solve our problems with the same thinking we used when we created them.  Albert Einstein Like a C or C++ programmer don t apply the logic.
More informationVALLIAMMAI ENGINEERING COLLEGE. SRM Nagar, Kattankulathur DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS
VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur603 203 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING EC6302 DIGITAL ELECTRONICS YEAR / SEMESTER: II / III ACADEMIC YEAR: 20152016 (ODD
More informationReview. Pipeline bigdelay CL for faster clock Finite State Machines extremely useful You ll see them again in 150, 152 & 164
CS61C L17 Combinatorial Logic Blocks (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #17 Combinatorial Logic Blocks 2007724 Scott Beamer, Instructor Review Pipeline bigdelay CL
More informationLAB #3: ADDERS and COMPARATORS using 3 types of Verilog Modeling
LAB #3: ADDERS and COMPARATORS using 3 types of Verilog Modeling LAB OBJECTIVES 1. Practice designing more combinational logic circuits 2. More experience with equations and the use of Kmaps and Boolean
More informationComputer Organization and Levels of Abstraction
Computer Organization and Levels of Abstraction Announcements Today: PS 7 Lab 8: Sound Lab tonight bring machines and headphones! PA 7 Tomorrow: Lab 9 Friday: PS8 Today (Short) Floating point review Boolean
More informationIntroduction to synthesis. Logic Synthesis
Introduction to synthesis Lecture 5 Logic Synthesis Logic synthesis operates on boolean equations and produce optimized combinational logic Logic Minimization Twolevel logic minimization Twolevel logic
More informationNAND. Grade (10) Instructor. Logic Design 1 / 13
Logic Design I Laboratory 02 NAND NOR XOR # Student ID 1 Student Name Grade (10) Instructor signature 2 3 Delivery Date 1 / 13 Objective To find the basic NAND & NOR & XOR gates concept and study on multiple
More informationBUILDING BLOCKS OF A BASIC MICROPROCESSOR. Part 1 PowerPoint Format of Lecture 3 of Book
BUILDING BLOCKS OF A BASIC MICROPROCESSOR Part PowerPoint Format of Lecture 3 of Book Decoder Tristate device Full adder, full subtractor Arithmetic Logic Unit (ALU) Memories Example showing how to write
More informationCh. 5 : Boolean Algebra &
Ch. 5 : Boolean Algebra & Reduction elektronik@fisika.ui.ac.id Objectives Should able to: Write Boolean equations for combinational logic applications. Utilize Boolean algebra laws and rules for simplifying
More informationA3 A2 A1 A0 Sum4 Sum3 Sum2 Sum1 Sum
LAB #3: ADDERS and COMPARATORS using 3 types of Verilog Modeling LAB OBJECTIVES 1. Practice designing more combinational logic circuits 2. More experience with equations and the use of Kmaps and Boolean
More informationB.Tech II Year I Semester (R13) Regular Examinations December 2014 DIGITAL LOGIC DESIGN
B.Tech II Year I Semester () Regular Examinations December 2014 (Common to IT and CSE) (a) If 1010 2 + 10 2 = X 10, then X is  Write the first 9 decimal digits in base 3. (c) What is meant by don
More informationTutorial on Verilog HDL
Tutorial on Verilog HDL HDL Hardware Description Languages Widely used in logic design Verilog and VHDL Describe hardware using code Document logic functions Simulate logic before building Synthesize code
More informationDLD VIDYA SAGAR P. potharajuvidyasagar.wordpress.com. Vignana Bharathi Institute of Technology UNIT 3 DLD P VIDYA SAGAR
DLD UNIT III Combinational Circuits (CC), Analysis procedure, Design Procedure, Combinational circuit for different code converters and other problems, Binary Adder Subtractor, Decimal Adder, Binary Multiplier,
More informationELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 3 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
More informationHDL for Combinational Circuits. ENEL211 Digital Technology
HDL for Combinational Circuits ENEL211 Digital Technology Lecture Outline Vectors Modular design Tristate gates Dataflow modelling Behavioural Modelling Vectors Often we want multibit quantities in digital
More informationEXPERIMENT #8: BINARY ARITHMETIC OPERATIONS
EE 2 Lab Manual, EE Department, KFUPM EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS OBJECTIVES: Design and implement a circuit that performs basic binary arithmetic operations such as addition, subtraction,
More informationContent beyond Syllabus. Parity checker and generator
Class : SE Div: B Subject : Logic Design Content beyond Syllabus Parity checker and generator What is parity bit? The parity generating technique is one of the most widely used error detection techniques
More information2008 The McGrawHill Companies, Inc. All rights reserved.
28 The McGrawHill Companies, Inc. All rights reserved. 28 The McGrawHill Companies, Inc. All rights reserved. All or Nothing Gate Boolean Expression: A B = Y Truth Table (ee next slide) or AB = Y 28
More informationR10. II B. Tech I Semester, Supplementary Examinations, May
SET  1 1. a) Convert the following decimal numbers into an equivalent binary numbers. i) 53.625 ii) 4097.188 iii) 167 iv) 0.4475 b) Add the following numbers using 2 s complement method. i) 48 and +31
More informationIT 201 Digital System Design Module II Notes
IT 201 Digital System Design Module II Notes BOOLEAN OPERATIONS AND EXPRESSIONS Variable, complement, and literal are terms used in Boolean algebra. A variable is a symbol used to represent a logical quantity.
More informationSUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3
UNIT  I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented
More informationSYNERGY INSTITUTE OF ENGINEERING & TECHNOLOGY,DHENKANAL LECTURE NOTES ON DIGITAL ELECTRONICS CIRCUIT(SUBJECT CODE:PCEC4202)
Lecture No:5 Boolean Expressions and Definitions Boolean Algebra Boolean Algebra is used to analyze and simplify the digital (logic) circuits. It uses only the binary numbers i.e. 0 and 1. It is also called
More informationSIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN
SIR C.R.REDDY COLLEGE OF ENGINEERING, ELURU DEPARTMENT OF INFORMATION TECHNOLOGY LESSON PLAN SUBJECT: CSE 2.1.6 DIGITAL LOGIC DESIGN CLASS: 2/4 B.Tech., I SEMESTER, A.Y.201718 INSTRUCTOR: Sri A.M.K.KANNA
More informationWhere We Are. Quick History Lesson. Lecture 8: Combinational Verilog. Specifying Circuits. Last lecture: Minimization with K!maps
Lecture 8: Combinational Verilog CSE 370, utumn 2007 enjamin Ylvisaker Where We re Last lecture: Minimization with K!maps This lecture: Combinational Verilog Next lecture: ROMs, PLs and PLs, oh my! Homework
More informationUNIT V COMBINATIONAL LOGIC DESIGN
UNIT V COMBINATIONAL LOGIC DESIGN NOTE: This is UNITV in JNTUK and UNITIII and HALF PART OF UNITIV in JNTUA SYLLABUS (JNTUK)UNITV: Combinational Logic Design: Adders & Subtractors, Ripple Adder, Look
More informationHardware description language (HDL)
Hardware description language (HDL) A hardware description language (HDL) is a computerbased language that describes the hardware of digital systems in a textual form. It resembles an ordinary computer
More information