Verilog Tutorial 9/28/2015. Verilog Fundamentals. Originally designers used manual translation + bread boards for verification

Transcription

1 Verilog Fundamentals Verilog Tutorial History Data types Structural Verilog Functional Verilog Adapted from Krste Asanovic Originally designers used manual translation + bread boards for verification Hardware design languages enabled logic level simulation and verification Once design were written in HDLs tools could be used for automatic translation Primary Verilog data type is a bit-vector where bits can take on one of four values 1

2 The Verilog keyword wire is used to denote a standard hardware net Verilog includes ways to specify bit literals in various bases Data types Structural Verilog Functional Verilog Verilog Basics A Verilog module includes a module name and a port list A Verilog module includes a module name and a port list A module can instantiate other modules creating a module hierarchy 2

3 A module can instantiate other modules creating a module hierarchy A module can instantiate other modules creating a module hierarchy Verilog supports connecting ports by position and by name Let s review how to turn our schematic diagram into structural Verilog Let s review how to turn our schematic diagram into structural Verilog Data types Structural Verilog Functional Verilog Gate level Register transfer level High-level behavioral Verilog Fundamentals 3

4 Functional Verilog can roughly be divided into three abstraction levels Gate-level Verilog uses structural Verilog to connect primitive gates Continuous assignments statements assign one net to another or to a literal Using continuous assignments to implement an RTL four input mutliplexer Verilog RTL includes many operators in addition to basic boolean logic Verilog RTL operators 4

5 Always blocks have parallel inter-block and sequential intra-block sematics Always blocks have parallel inter-block and sequential intra-block sematics Always blocks have parallel inter-block and sequential intra-block sematics Always blocks have parallel inter-block and sequential intra-block sematics Always blocks have parallel inter-block and sequential intra-block sematics Continuous and procedural assignment statements are very different 5

6 Always blocks can contain more advanced control constructs What happens if the case statement is not complete? What happens if the case statement is not complete? So is this how we make latches and flipflops? more about Verilog execution semantics more about Verilog execution semantics 6

7 more about Verilog execution semantics more about Verilog execution sematics more about Verilog execution sematics more about Verilog execution semantics more about Verilog execution semantics more about Verilog execution sematics 7

8 more about Verilog execution sematics We didn t model what we expected due to Verilog execution semantics Non-blocking procedural assignments add an extra event queue Non-blocking procedural assignments add an extra event queue The order of non-blocking assignments does not matter Common patterns for latch and flip-flop inference 8

9 Writing Good Synthesizable Verilog Behavioral Verilog is used to model the abstract function of a hardware Verilog can be used to model the highlevel behavior of a hardware block Delay statements should only be used in test harnesses System tasks are used for test harnesses and simulation management Which abstraction is the right one? 9

10 Examples Mux4: Gate-level structural Verilog Mux4: Using continuous assignments Mux4: Behavioral style Mux4: Using always block Mux4: Always block permit more advanced sequential idioms 10

11 Parametrized mux4 Flip-flops Flip-flops with reset Register Register in terms of Flip-flops Static Elaboration: Generate 11

12 A simple state machine for valid/ready signals Implementing the control logic finite state machine in Verilog Implementing the control signal outputs for the finite state machine Implementing the state transitions for the finite state machine Take away points 12