TYPES OF INTERRUPTS: -

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1 There are 3 types of interrupts. TYPES OF INTERRUPTS: - External Interrupts. Internal Interrupts. Software interrupts. Hardware Interrupts (1) External interrupts come from I/O devices, from a timing device (or) from any other external source. (2) Internal interrupts are also called as traps. They arise from illegal (or) erroneous use of an instruction (or) data. Examples: 1. Register overflow. 2. Attempt to divide by zero. 3. An invalid operation code. 4. Stack overflow. 5. Protection violation. (3) Software Interrupts: - It is initiated by executing an instruction. Stack Organization: - Stack: LIFO Stack Pointer: The register that holds the address for the stack is called a SP. Two operations of a stack: Push and Pop. FULL EMPTY 63 SP C B A DR

2 Push operation is implemented with the following sequence of micro operations. SP SP+1 Increment Stack Pointer. M[SP] DR write item on the top of the stack. If (SP=0) then (FULL 1) check if stack is full. EMPTY 0 mark the stack not empty. Note:- Initially SP is cleared to 0, EMPTY is set to 1, FULL is cleared to 0. When data is pushed on to the stack, SP gets incremented by 1. In step 3, we are checking whether Full is set to 1. If SP reaches 0, stack is full of items, so FULL is set to 1. Pop operation is implemented by the following sequence of Micro-Operations. 1. DR M[SP] Read item from the top of the stack. 2. SP SP-1 Decrement stack pointer. 3. If (SP=0) then (EMPTY 1) Check if stack is empty. 4. FULL 0 Mark the stack not full. Instruction Formats: - The bits of the instruction are divided into groups called fields. 1. An operation code field. 2. An address field. 3. A mode field. Most computers fall into one of three types of CPU organizations. 1. Single Accumulator Organization. 2. General Register Organization. 3. Stack Organization. ADD X - Where X is the address of the operand. AC AC + M [X] ADD R1, R1, R2, R2, R3 R3 R1 R2 + R3

3 ADD R1, R2 R2 R1 R1 + R2. Timing Diagram: - Addressing Modes: - Instruction format with mode field. OP Code Mode Address Addressing Mode Field

4 Addressing modes Implied Mode. Immediate Mode. Register Mode. Register Indirect Mode. Auto Increment (or) Auto Decrement Mode. Direct Address Mode. Indirect Address Mode. Relative Address Mode. Indexed Addressing Mode. Base Register Addressing Mode. Data Transfer and Manipulation: - Computer interactions can be classified into three categories. Data transfer instructions. Data manipulation instructions. Program Control instructions. (1) Data Transfer Instructions: - Load Store Move Exchange Input Output Push Pop LD ST MOV XCH IN OUT PUSH POP (2) Data Manipulation Instructions: - Arithmetic Instructions. Logical and Bit Manipulation Instructions. Shift Instructions.

5 Arithmetic Instructions: - Increment Decrement Add Subtract Multiply Divide Add with Carry Subtract with Borrow Negate (2 s Complement) INC DEC ADD SUB MUL DIV ADDC SUBB NEG Logic & Bit Manipulation Instructions: - Clear Complement AND OR Exclusive-OR Clear Carry Set Carry Complement Carry Enable Interrupt Disable Interrupt CLR COM AND OR XOR CLRC SETC COMC EI DI Shift Instructions: - Logical Shift Right Logical Shift Left Arithmetic Shift Right Arithmetic Shift Left Rotate Right Rotate Left Rotate Right through Carry Rotate Left through Carry SHR SHL SHRA SHLA ROR ROL RORC ROLC

6 (3) Program Control Instructions: - Branch Jump Skip Call Return Compare Test (By AND ing) BR JMP SKP CALL RET CMP TST REDUCED INSTRUCTION SET COMPUTER: - An Important aspect of computer Architecture is the design of the Instruction set for the Processor. A Computer with a large number of instructions is classified as a Complex Instruction Set Computer abbreviated as CISC. If the computer use fewer instruction set, the instructions can be executed at a faster rate. This type of computer is called Reduced Instruction Set Computer (or)risc. There are two types of Computer Architectures: CISC Architecture Characteristics: - CISC. RISC. A large number of instructions typically 100 to 250 instructions. Some instructions that perform specialized tasks and are not used frequently. A large variety of addressing modes from 5 to 20 different modes. Variable length instruction formats. Instructions that manipulate operands in memory. RISC Characteristics: - RISC Architecture involves an attempt to reduce execution time by simplifying the instruction set of the computer. Relatively few instructions.

7 Relatively few addressing modes. Memory access limited to load and store instructions. All operations done within the register of CPU. Fixed length, easily decoded instruction format. Single-cycle instruction execution. Hardwired rather than micro programmed control.

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