SUBJECT CODE: IT T35 DIGITAL SYSTEM DESIGN YEAR / SEM : 2 / 3


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1 UNIT  I PART A (2 Marks) 1. Using Demorgan s theorem convert the following Boolean expression to an equivalent expression that has only OR and complement operations. Show the function can be implemented with logic circuits that have only OR gates and inverters: F = (y = z)(x+y)(y+z). (Nov 15) 2. Prove that the logical sum of all minterm of Boolean function 2 variables is 1. (Nov 15) 3. Define canonical expansion. (Nov 15) 4. Convert the following hexadecimal numbers to decimal. (Nov 15) (a) (E9) (b) (3FC.8) 5. Find octal and hexadecimal for the binary number (Apr 16) 6. What is BCD? Mention its use.. (Apr 16) 7. Define Magnitude Comparator.(Nov 13) 8. What is Encoder? (Nov 13) 9. State two absorption properties of Boolean algebra.(apr 14) 10. Why NAND and NOR gates are called as universal gates? (Apr 14) 11. Convert the following decimal numbers to the indicated bases. (Nov 14) (a) to hexadecimal (b) to binary 12. Simplify the Boolean expressions to a minimum number of literals x y+xy +xy+x y. (Nov 14) 13. What is largest binary number that can be expressed with (a) 14 bits (b) 10 bits? (Nov 16) 14. Find the complement of the functions F 1 = x yz + x y z and F 2 = x(y z + yz). (Nov 16) 15. What is minterm? (Nov 16) 16. Convert the ( ) 10 to octal. (Nov 16)
2 PART B (11 Marks) 1. Minimize the given terms: πm(0,1,4,11,13,15) + πd(5,7,8) using QuineMcClusky methods and verify the results using Kmap method.(nov 15) 2. (a) How are AND, OR and NOT realized with NAND gates? (Nov 15) (b) Simplify xy + xz + yz. 3. (a) Explain any four basic theorem of Boolean algebra. (Apr 16) (b) Explain any two methods of representing a negative number. 4. (a) Simplify the Boolean function. (Apr 16) F(u,x,y,z)= (0,1,2,4,5,6,8,9,12,13,14). Using Karnaugh map. 5. Demonstrate the validity of the following identities by means of truth tables: (Nov 13) (a) DeMorgan s theorem for three variables: (x+y+z)=x y z and (xyz) = x +y +z (b) The distributive law : x+yz = (x+y)(x+z) (c) The distribute law: x(y+z)=xy+xz. 6. Explain detail about Gray Code. 7. What are codes? Explain the different coes with examples. (Apr 14) 8. Simplify the following Boolean function in SOP and POS form using Kmap F(A,B,C,D) = m(3,4,9,13,14,15)+ d(2,5,10,12). (Apr 14) 9. Convert the following decimal numbers to the indicated bases. (Nov 14) (c) to hexadecimal (d) to binary 10. Simplify the Boolean expressions to a minimum number of literals x y+xy +xy+x y. (Nov 14) 11. Explain in detail about Boolean function. (Nov 16) 12. What a suitable example, explain karnaugh map. (Nov 16)
3 13. Using tabulation method simplify the Boolean function F(w,x,y,z)= (2,3,4,6,7,11,12,13,14) with don t care conditions d(1,5,15). (Nov 16) 14. Simplify the Boolean function using map method F(w,x,y,z)= (0.2,4,6.8,10,12,14). (Nov 16) UNIT  II Part A (2 Marks) 1. Specify the function of a demultiplexer.(apr 16) 2. Draw the logic diagram of 3bit even parity generator. (Apr 16) 3. Define Register. (Nov 13) 4. Define ROM. (Nov 13) 5. Mention the use of decoders. (Apr 14) 6. What is demultiplexer? Give its application. (Apr 14) 7. Mention the steps involved in design of combinational logic circuits. (Nov 14) 8. Design a circuit using NAND gate, to realize the following gate circuits: (Nov 14) (a) AND gate (b) OR gate 9. Draw a quadruple 2 to 1 line multiplexer and write its function tables.(nov 16) 10. Mention any four applications of combinational circuits.(nov 16) 11. What is fulladder? (Nov 16) 12. Draw the diagram for 3bit parity generation. (Nov 16)(Nov 15) 13. Write an expression for borrow and difference in a full subtractor circuit. (Nov 15) 14. Draw the structure of 8:1 decoder. (Apr 16) 15. Realise the functions f1(x,y,z)= m(1,2,4,5) and f2(x,y,z)= m(1,5,7) using MUX. (Apr 16) Part B (11 Marks) 1. Design a 4 bit BCD to excess3 code converter. Draw the logic diagram. (Nov 15)
4 2. Multiply (1011) 2 by (1101) 2 using addition and shifting operation and also draw the block diagram of 4bit parallel multiplier. (Nov 15) 3. (a) Draw and explain the full adder circuit. (Apr 16) (b) What is code converter? Explain. 4. (a) Explain 3to8 line decoder with its circuit. (Apr 16) (b) What is multiplexer? Mention its use. 5. With a proper truth table and a logic diagram, explain Three toeightline Decoder.(Nov 13) 6. Explain the Multiplexer with its logic diagram in details. (Nov 13) 7. Construct a BCD to Excess 3 code converer using full adders. (Apr 14) 8. Explain with truth table and gate level circuits diagram for a full adder. (Apr 14) 9. Design a combinational logic circuit with three inputs and one output. The output is equal to logic1 when the binary value of the input is less than 3. The output is logic0 otherwise. (Nov 14) 10. Design a 4 to 1 line multiplexer and implement the same using logic gates. (Nov 14) 11. Design a three input majority combinational circuit with circuit truth table. Boolean equation and logic diagram whose output is equal to 1 if the input variable have more 1 s than 0 s. The output is 0 otherwise.(nov 16) 12. Construct a 4 to 16 line decoder with five 2 to 4 line decoders along with enable features.(nov 16) 13. Write about binary parallel adder. (Nov 16) 14. With a neat diagram, explain the concept of multiplexer. (Nov 16) 15. Implement the following function using suitable multiplexer. F(A,B,C) = m(0,2,4,6). (Apr 16) 16. Write a short note on the following: (Apr 16) (a) Magnitude comparator. (b) Parity generator.
5 UNIT  III Part A (2 Marks) 1. What are the guidelines to be followed while making state assignment? (Nov 15) 2. Design a 3 bit ring counter and find the mod of the designed counter. (Nov 15) 3. Mention the difference between combinational circuit and sequential circuit.(apr 16) 4. What is mealy model? (Apr 16) 5. Define Register. (Nov 13) 6. Define ROM. (Nov 13) 7. Write the excitation tables of JK and D flipflops.(apr 14) 8. Draw the diagram of threebit ring counter. (Apr 14) 9. Draw the excitation table for the JK flipflop and mention the advantages. (Nov 14) 10. Compare the mealy and moore model. (Nov 14) 11. What is the significance of dynamic indicator in a flipflop?(nov 16) 12. Write any two difference between serial mode and parallel mode in shift registers.(nov 16) 13. Distinguish between synchronous and asynchronous circuits. (Nov 16) 14. Differentiate flip flops from latches. (Nov 16) 15. Define modules counters. (Apr 16) 16. What is the purpose of registers? (Apr 16) Part B (11 Marks) 1. (a) Explain the operation of masterslave JK flipflop. (Nov 15) (b) Convert D flip flop to T flip flop. (Nov 15) 2. Design a synchronous up / down counter that will count up from zero to one to two to three, and will repeat whenever an external input x is logic 0 and will count down from three to two to one to zero, and will repeat whenever the external input x is logic 1. (Nov 15)
6 3. (a) Explain any three flipflops with its characteristics equation. (Apr 16) (b) What is shift register? Explain. 4. Design a 4bit updown counter and explain the operation. (Apr 16) 5. Explain the EdgeTriggered D flipflop with a neat logic diagram. (Nov 13) 6. With a neat sketch, describe the working principles of Ring Counter. (Nov 13) 7. (a) Explain the working of a master slave JK flip flop. State its advantages.(apr 14) (b) Compare Moore and Mealy circuits. 8. Design a BCD Up/Down counter using SR flipflops. (Apr 14) 9. Draw the state diagram of a 3bit binary counter using design the counter using sequential logic circuits.(nov 14) 10. Explain with neat sketch the principle of operation serial in and serial out shift register. Also draw the truth table for the same. (Nov 14) 11. Design a clocked synchronous sequential circuit which detects the following sequence 0110 / 1001.(Apr 16) 12. Write a short note on the following: (Apr 16) (a) Shift registers (b) Ripple counters (c) Flip flops 13. How many FlipFlops will be complemented in a 10 bit binary ripple counter to reach the next count after the following counts (a) (b) (Nov 16) 14. The contents of a 4 bit register are initially The register is shifted 6 times to right with serial input being What are the contents of register after each shift?(nov 16) 15. Briefly explain any two flip flops with a suitable block diagram. (Nov 16) 16. Write short notes on the following : (Nov 16) (a) Ripple counter (b) Ring counter.
7 UNIT  IV Part A (2 Marks) 1. Compare static RAM dynamic RAM. (Nov 15) 2. What are hazard free digital circuits? (Nov 15) 3. Mention the concept of Hamming code. (Apr 16) 4. How many 128 * 8 RAM chips are needed to provide a memory capacity of 2048 bytes? (Apr 16) 5. What is Counter? (Nov 13) 6. What is Programmable Array Logic? (Nov 13) 7. Compare RAM and ROM. (Apr 14) 8. Define Hazard. (Apr 14) 9. Draw the logic diagram of a 4 to 1 line multiplexer. (Nov 14) 10. What is a shift register? Mention the various types of it. (Nov 14) 11. Define mask programming.(nov 16) 12. What is registered PAL?(Nov 16) 13. What is meant by field programmable logic array? (Nov 16) 14. Differentiate between ROM and PLA. (Nov 16) 15. What are the different types of memory? (Apr 16) 16. List different types of ROMs available and their application areas. (Apr 16) Part B (11 Marks) 1. With a neat block diagram, explain PLA. Implement the functions, f1(x,y,z)= m(1,2,3,7) and f2(x,y,z)= m(0,1,2,6) using 3*4*2. (Nov 15) 2. Explain state table reduction and state assignment technique using the state table given below:(nov 15)
8 Present state Next state Input(x) Output(z) Input(x) X=0 X=1 X=0 X=1 A A B 0 0 B D C 0 1 C F E 0 0 D D F 0 0 E B G 0 0 F G C 0 1 G A F (a) Explain the types of memories and their characteristics. (Apr 16) (b) What is race condition? Explain. 4. (a) Explain the characteristics of PLA with a block diagram. (Apr 16) (b) Explain the hazards in combinational circuits. 5. Describe the Programmable Logic Array in detail with a proper diagram. (Nov 13) 6. Elaborate RAM with its operations.(nov 13) 7. (a) With a neat block diagram, explain PLA.(Apr 16) (b) Implement the functions f1(x,y,z)= m(1,2,3,7) and f2(x,y,z)= m(0,1,2,6) using 3*4*2 PLA (true / complement method) (Apr 16) 8. Explain the state table reduction and state assignment technique using the state table given below. Present state Next state Input(y) Output(z) Input(x) X=0 X=1 X=0 X=1 *A A B 0 0 B D C 0 1
9 C F E 0 0 D D F 0 0 E B G 0 0 F G C 0 1 G A F 0 0 (Apr 16) 9. What do you mean by ROM? Explain its types. (Apr 14) 10. Reduce the number of states in the following state table and tabulate the Reduced state table.(apr 14) Present Next state output State x=0 x=1 x=0 x=1 a F b 0 0 b D c 0 0 c F e 0 0 d G a 1 0 e D c 0 0 f F b 1 1 g G h 0 1 h G a Draw the block diagram of a 1K * 16 RAM and explain how the read/write operation is performed.(nov 14) 12. What is hazards? Explain how the hazard occurs in combinational circuits and also the remedy for eliminating the hazard with an example. (Nov 14) 13. Derive the PLA program table for combinational circuit that sequence a three bit number and minimum the number of product terms.(nov 16) 14. Tabulate the truth table for a 8 * 4 ROM that implements the Boolean function (Nov 16) A(x,y,z) = (0,3,4,6) B(x,y,z) = (0,1,3,7)
10 C(x,y,z) = (0,5) D(x,y,z) = (0,1,4,5,7) 15. Write about error deduction and error correction techniques. (Nov 16) 16. With a neat diagram, explain circuits with latches. (Nov 16) Part A (2 Marks) UNIT  V 1. What are the different data types in Verilog HDL? (Nov 15) 2. Design a three input AND gate using Verilog. (Nov 15) 3. Mention the use of Verilog.(Apr 16) 4. Mention the difference between register and counter. (Apr 16) 5. Define NonBlocking assignment statement. (Nov 13) 6. Write the arithmetic and Logic Verilog HDL operators. (Nov 13) 7. What you mean by HDL? (Apr 14) 8. What are the two combinational circuits in the multiplier? (Apr 14) 9. What is debounce circuit? Draw the logic circuit using SR latch. (Nov 14) 10. Define Noise margin and mention the typical value for CMOS IC. (Nov 14) 11. What is logic synthesis in HDL? (Nov 16) 12. Write the merits of VHDL? (Nov 16) 13. What is shift register? (Nov 16) 14. What is a combinational circuits? (Nov 16) 15. List the different types of modelling in Verilog.(Apr 16) 16. What is a test bench? What is its revelence in Verilog? (Apr 16)
11 Part B (11 Marks) 1. Design and implement 16: 1 Multiplexer using two 8 : 1 MUX in Verilog HDL. (Nov 15) 2. Model a 4 bit linear feedback shift register using Verilog HDL. (Nov 15) 3. Explain the HDL for combinational circuits. (Apr 16) 4. Explain HDL description for binary multiplier. (Apr 16) 5. Give the HDL design module of a HalfAdder. (Nov 13) 6. Elaborate various Levels of Design Description in Verilog. (Nov 13) 7. How Registers and counters can be described in HDL at behaviour level? Explain. (Apr 14) 8. Discuss in detail about HDL description for Binary multiplier. (Apr 14) 9. Write a VHDL model that describes the operation of a shift register. Use notations for input, output, mode control inputs, left and right serial inputs. (Nov 14) 10. (a) Write VHDL code for a full adder using logic equation. (Nov 14) (b) Write a VHDL description of the 4bit counter. 11. Write and verify a Verilog model of a D FlipFlops having synchronous set.(nov 16) 12. Design a HDL behavioural description of a 4 bit register with parallel load and asynchronous clear.(nov 16) 13. Explain in detail about sequential circuits. (Nov 16) 14. Write about Registers and Counters. (Nov 16) 15. Design a 4bit linear shift register using Verilog HDL. (Apr 16) 16. Design and implement a full adder using Verilog HDL (Apr 16) (a) Gate level modelling. (b) Structural modelling (using half adder)
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