ECE 2300 Digital Logic & Computer Organization. More Verilog Finite State Machines
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1 ECE 2300 Digital Logic & Computer Organization Spring 2018 More Verilog Finite Machines Lecture 8: 1
2 Prelim 1, Thursday 3/1, 1:25pm, 75 mins Arrive early by 1:20pm Review sessions Announcements Monday 2/26, 7:00pm, PHL 407 Tuesday 2/27, 7:00pm, PHL 407 Coverage: Lecture 1~7, HW 1~3 Sample prelim released on CMS Solutions to HW 1 & 2 released on CMS HW3 solution to be released on Sunday TA-led Verilog tutorial Next Tuesday (2/27) Bring your laptop! Lecture 8: 2
3 Review: Verilog Design Styles Structural A module is built from other (sub-)modules via instance statements Behavioral Use continuous assignments and/or procedural code in always blocks to indicate what actions to take Lecture 8: 3
4 Review: Procedural Assignments Blocking assignments ( = ) Simulation behavior: Right-hand side (RHS) evaluated sequentially; assignment to LHS is immediate Nonblocking assignment ( <= ) Simulation behavior: RHS evaluated in parallel (order doesn t matter); assignment to LHS is delayed until end of always block reg Y, Z; (posedge clk) begin Y = A & B; Z = ~Y; end Blocking assignments Y next = A & B Z next = ~(A & B) reg Y, Z; (posedge clk) begin Y <= A & B; Z <= ~Y; end Nonblocking assignments Z next = ~Y // the old Y Y next = A & B Lecture 8: 4
5 Review: Procedural Assignments reg Y, Z; (posedge clk) begin Y = A & B; Z = ~Y; end Blocking assignments Corresponding circuit diagrams reg Y, Z; (posedge clk) begin Y <= A & B; Z <= ~Y; end Nonblocking assignments A B A B Y Z Y Z Y and Z are flip-flops in actual hardware Lecture 8: 5
6 Net and Variable Types We will mainly use two data type classes wire: represents a physical connection (or net) between hardware elements A stateless way of connected two elements Can only be used to model combinational logic Cannot be used in the left-hand side in an always block reg: similar to wires, but can be used to store information (or state) like registers This is used in the behavioral style only Can be used to model both combinational & sequential logic Cannot be used in the left-hand side of a continuous assignment statement Lecture 8: 6
7 (Improperly Created) Inferred Latches You re recommended to ensure that each variable within an always block gets assigned a value (under all possible conditions) Otherwise, the Verilog compiler assumes that the last value should be used, and will create a latch reg dout; c) begin /* dout not always assigned a value; latch inferred */ if (c == 1'b1) dout = din; end reg dout; c) begin /* dout assigned a value in both conditions, latch not inferred */ if (c == 1'b1) dout = din; else dout = ~din; end Lecture 8: 7
8 Finite Machine Current Inputs Combinational Logic Outputs Next A Finite Machine (FSM) is an abstract representation of a sequential circuit The state embodies the condition of the system at this particular time The combinational logic determines the output and next state values The output values may depend only on the current state value, or on the current state and input values Lecture 8: 8
9 Elements of an FSM 1. A finite number of inputs 2. A finite number of outputs 3. A finite number of states 4. A specification of all state transitions Current Inputs Combinational Logic Outputs Next Can be described by a state diagram Lecture 8: 9
10 FSM: General Form Inputs Combinational Logic Outputs Inputs and current state determine state transitions Current FF Next Output changes determined by changes in Current state, or Current state + inputs FF CLK Lecture 8: 10
11 Moore Machine Output Combinational Logic Outputs Inputs Next Combinational Logic Outputs only depend on current state value Current FF Next FF Lecture 8: 11
12 Mealy Machine Output Combinational Logic Outputs Inputs Next Combinational Logic Outputs depend on input and current state values Current FF Next FF Lecture 8: 12
13 Diagram Visual specification of an FSM Bubble for every state Arcs showing state transitions Input values shown on the arcs Output values shown within the bubbles (Moore) or on the arcs (Mealy) Clock input implicit (always present, triggering state transitions) Moore FSM Mealy FSM Reset 0 1 Reset 0/0 1 S0 0 0 S S2 1 1/0 S0 0/0 1/1 S1 Lecture 8: 13
14 Moore Diagram Moore FSM Reset 0 1 S0 0 0 S S2 1 1 input, 1 output, 3 states Bubble for each state transitions (arcs) for each input value Input values on the arcs Output values within the bubbles Starts at S0 when Reset asserted Lecture 8: 14
15 Mealy Diagram Mealy FSM Reset 0/0 1/0 S0 0/0 1/1 S1 1 input, 1 output, 2 states Bubble for each state transitions (arcs) for each input value Input values on the arcs (first number) Output values on the arcs (second number) Starts at S0 when Reset asserted Lecture 8: 15
16 FSM Design Procedure (1) Understand the problem statement and determine inputs and outputs This lecture (2) Identify states and create a state diagram (3) Determine the number of required D FFs (4) Implement combinational logic for outputs and next state (5) Simulate the circuit to test its operation Lecture 8: 16
17 Example FSM: Pattern Detector Monitors the input, and outputs a 1 whenever a specified input pattern is detected Example: Output a 1 whenever 111 is detected on the input over 3 consecutive clock cycles Overlapping patterns also detected ( ) Input In Output Out Reset causes FSM to start in initial state Clock input not shown (always present) Lecture 8: 17
18 111 Pattern Detector: Moore Diagram Lecture 8: 18
19 111 Pattern Detector: Mealy Diagram Lecture 8: 19
20 Example FSM: Pushbutton Lock Two pushbutton inputs, X1 and X2 One output, UL ( Unlock ) UL = 1 when X1 is pushed, followed by X2 being pushed twice (X1, X2, X2) Represent X1 and X2 as two bit input 00: neither button pushed 10: X1 pushed 01: X2 pushed 11: both pushed, reset the lock Lecture 8: 20
21 Pushbutton Lock: Moore Diagram Output: UL=1 with (X1, X2, X2) Input: 00 (neither), 10 (X1), 01 (X2), 11 (reset) Lecture 8: 21
22 Readings Before Next Class Tuesday 2/27: Verilog Tutorial Tutorial C: Introduction to Verilog and Quartus II Tuesday 3/6: More Finite Machines H&H 4.9 Lecture 8: 22
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