Verilog Tutorial. Introduction. T. A.: Hsueh-Yi Lin. 2008/3/12 VLSI Digital Signal Processing 2

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1 Verilog Tutorial T. A.: Hsueh-Yi Lin Introduction 2008/3/12 VLSI Digital Signal Processing 2

2 Verilog: A common language for industry HDL is a common way for hardware design Verilog VHDL Verilog is widely adopted in Taiwan s industry VHDL is applied by American Military Realization of HDL into hardware FPGA prototype Cell based design 2008/3/12 VLSI Digital Signal Processing 3 Verilog: A common language for industry Design steps: System design Partitioning Behavior modeling Simulation and synthesis Post simulation, layout 2008/3/12 VLSI Digital Signal Processing 4

3 Verilog coding / Head / Numeric representation 2008/3/12 VLSI Digital Signal Processing 5 Verilog coding 2008/3/12 VLSI Digital Signal Processing 6

4 Declaration and Comment 2008/3/12 VLSI Digital Signal Processing 7 Data types Net physical wire between devices the default data type used in structural modeling and continuous assignment types of nets wire, tri : default wor, trior : wire-ored wand, triand : wire-anded trireg : with capacitive storage tri1 : pull high tri0 ; pull low supply1 ; power supply0 ; ground 2008/3/12 VLSI Digital Signal Processing 8

5 Reg variables used in RTL description a wire, a storage device or a temporary variable reg : unsigned integer variables of varying bit width integer : 32-bit signed integer real time : signed floating-point : 64-bit unsigned integer Parameters run-time constants 2008/3/12 VLSI Digital Signal Processing 9 Data format 2008/3/12 VLSI Digital Signal Processing 10

6 Number representation 2008/3/12 VLSI Digital Signal Processing /3/12 VLSI Digital Signal Processing 12

7 2008/3/12 VLSI Digital Signal Processing 13 Concatenation of signals 2008/3/12 VLSI Digital Signal Processing 14

8 The Description of HDL Description language Always and Initial Combinational circuit by always Sequential circuit by always Correct and wrong description Design Examples for sequential circuits A complete design flow 2008/3/12 VLSI Digital Signal Processing 15 Modeling Structures Net-list structural description for the top level Continuous assignments (combination circuits) data flow specification for simple combinational Assign Verilog operators Procedural blocks (RTL) always and initial blocks allow timing control and concurrency C-like procedure statements primitives (=truth table, state transition table) function and task ( function and subroutine) Gate label(nets) Always Begin 2008/3/12 VLSI Digital Signal Processing 16

9 Gate-Level Modeling Net-list description built-in primitives gates A full-adder module add (co, s, a, b, c) input a, b,c ; output co, s ; xor (n1, a, b) ; xor (s, n1, c) ; nand (n2, a, b) ; nand (n3,n1, c) ; nand (co, n3,n2) ; module 2008/3/12 VLSI Digital Signal Processing 17 Verilog Primitives Basic logic gates only and or not buf xor nand nor xnor bufif1, bufif0 notif1, notif0 2008/3/12 VLSI Digital Signal Processing 18

10 Primitive Pins Are Expandable One output and variable number of inputs nand (y, in1, in2) ; nand (y, in1, in2, in3) ; not and buf nand (y, in1, in2, in3, in4) ; variable number of outputs but only one input 2008/3/12 VLSI Digital Signal Processing 19 Continuous Assignments Describe combinational logic Operands + operators Drive values to a net assign out = a&b ; // and gate assign eq = (a==b) ; // comparator wire #10 inv = ~in ; // inverter with delay wire [7:0] c = a+b ; // 8-bit adder Avoid logic loops assign a = b + a ; asynchronous design 2008/3/12 VLSI Digital Signal Processing 20

11 Operators { } concatenation + - * / arithmetic % modulus > >= < <= relational! logical NOT && logical AND logical OR == logical equality!= logical inequality? : conditional ~ bit-wise NOT & bit-wise AND bit-wise OR ^ bit-wise XOR ^~ ~^ bit-wise XNOR & reduction AND reduction OR ~& reduction NAND ~ reduction NOR ^ reduction XOR ~^ ^~ reduction XNOR << shift left >> shift right 2008/3/12 VLSI Digital Signal Processing 21 Logical, bit-wise and unary operators a = 1011; b = 0010 logical bit-wise unary a b = 1 a b = 1011 a = 1 a && b = 1 a &b = 0010 &a = 0 Conditional operator assign z = ({s1,s0} == 2'b00)? IA : ({s1,s0} == 2'b01)? IB : ({s1,s0} == 2'b10)? IC : ({s1,s0} == 2'b11)? ID : 1'bx ; assign s = (op == ADD)? a+b : a-b ; 2008/3/12 VLSI Digital Signal Processing 22

12 Operator Precedence [ ] bit-select or part-select ( ) parentheses!, ~ logical and bit-wise negation &,, ~&, ~, ^, ~^, ^~ reduction operators +, -unary arithmetic { } concatenation *, /, % arithmetic +, - arithmetic <<, >> shift >, >=, <, <= relational ==,!= logical equality & bit-wise AND ^, ^~, ~^ bit-wise XOR and XNOR bit-wise OR && logical AND logical OR? : conditional 2008/3/12 VLSI Digital Signal Processing 23 The Description of HDL Always and Initial 2008/3/12 VLSI Digital Signal Processing 24

13 RTL Modeling Describe the system at a high level of abstraction Specify a set of concurrently active procedural blocks procedural blocks = digital circuits Blocking : = Non-blocking: => Procedural blocks initial blocks test-fixtures to generate test vectors initial conditions always blocks can be combinational circuits can imply latches or flip-flops 2008/3/12 VLSI Digital Signal Processing 25 RTL Statements Procedural and RTL assignments reg & integer out = a + b ; begin... block statements group statements if... else statements case statements for loops while loops forever loops 2008/3/12 VLSI Digital Signal Processing 26

14 The Description of HDL Combinational circuit by always 2008/3/12 VLSI Digital Signal Processing 27 Combinational Always Blocks A complete sensitivity list (inputs) or b or c) f = a&~c b&c ; Parentheses or b or c or d) z = a + b + c + d ; // z = (a+b) + (c+d) ; 2008/3/12 VLSI Digital Signal Processing 28

15 Combinational Circuit Design Outputs are functions of inputs inputs comb. circuits Outputs Examples MUX decoder priority encoder adder 2008/3/12 VLSI Digital Signal Processing 29 Multiplexor Net-list (gate-level) module mux2_1 (out,a,b,sel) ; output out ; input a,b,sel ; not (sel_, sel) ; and (a1, a, sel_) ; and (b1, b, sel) ; or (out, a1, b1) ; module 2008/3/12 VLSI Digital Signal Processing 30

16 Multiplexor Continuous assignment module mux2_1 (out,a,b,sel) ; output out ; input a,b,sel ; assign out = (a&~sel) (b&sel) ; module RTL modeling or b or sel) if(sel) out = b; else out = a; 2008/3/12 VLSI Digital Signal Processing 31 Multiplexor 4-to-1 multiplexor module mux4_1 (out, in0, in1, in2, in3, sel) ; output out ; input in0,in1,in2,in3 ; input [1:0] sel ; assign out = (sel == 2'b00)? in0 : (sel == 2'b01)? in1 : (sel == 2'b10)? in2 : (sel == 2'b11)? in3 : 1'bx ; module 2008/3/12 VLSI Digital Signal Processing 32

17 module mux4_1 (out, in, sel) ; output out ; input [3:0] in ; input [1:0] sel ; reg out ; or in) begin case(sel) 2 d0: out = in[0] ; 2 d1: out = in[1] ; 2 d2: out = in[2] ; 2 d3: out = in[3] ; default: 1 bx ; case module 2008/3/12 VLSI Digital Signal Processing 33 Decoder 3-to 8 decoder with an enable control module decoder(o,enb_,sel) ; output [7:0] o ; input enb_ ; input [2:0] sel ; reg [7:0] o ; (enb_ or sel) if(enb_) else o = 8'b1111_1111 ; case(sel) 3'b000 : o = 8'b1111_1110 ; 3'b001 : o = 8'b1111_1101 ; 3'b010 : o = 8'b1111_1011 ; 3'b011 : o = 8'b1111_0111 ; 3'b100 : o = 8'b1110_1111 ; 3'b101 : o = 8'b1101_1111 ; 3'b110 : o = 8'b1011_1111 ; 3'b111 : o = 8'b0111_1111 ; default : o = 8'bx ; case module 2008/3/12 VLSI Digital Signal Processing 34

18 Adder RTL modeling module adder(c,s,a,b) ; output c ; output [7:0] s ; input [7:0] a,b ; assign {c,s} = a + b ; module Logic synthesis CLA adder for speed optimization ripple adder for area optimization 2008/3/12 VLSI Digital Signal Processing 35 Tri-State The value z (sela or a) if (sela) out = a ; else out = 1 bz ; assign out = (sela)? a: 1 bz ; Another block or b) if(selb) out =b ; else out = 1 bz ; 2008/3/12 VLSI Digital Signal Processing 36

19 The Description of HDL Sequential circuit by always 2008/3/12 VLSI Digital Signal Processing 37 Sequential Circuit Design Inputs Combinational circuit Memory elements Outputs a feedback path the state of the sequential circuits the state transition synchronous circuits asynchronous circuits 2008/3/12 VLSI Digital Signal Processing 38

20 Registers (Flip-flops) are clk) clk) a positive edge-triggered D flip-flop (posedge clk) q = d ; 2008/3/12 VLSI Digital Signal Processing 39 Procedural Assignments Blocking assignments clk) begin rega = data ; regb = rega ; Non-blocking assignments clk) begin regc <= data ; regd <= regc ; 2008/3/12 VLSI Digital Signal Processing 40

21 Sequential Always Blocks Inferred latches (Incomplete branch specifications) module infer_latch(d, enable, Q); input D, enable; output Q; reg Q; (D or enable) begin if (enable) Q <= D; module Non full case the Q is not specified in a branch a latch like /3/12 VLSI Digital Signal Processing 41 The Description of HDL Correct and wrong description 2008/3/12 VLSI Digital Signal Processing 42

22 Wrong Description module count (clock, reset, and_bits, or_bits, xor_bits); input clock, reset; output and_bits, or_bits, xor_bits; reg and_bits, or_bits, xor_bits; reg [2:0] count; clock) begin if (reset) count <= 0; else count <= count + 1; and_bits <= & count; or_bits <= count; xor_bits <= ^ count; module 2008/3/12 VLSI Digital Signal Processing 43 Six implied registers 2008/3/12 VLSI Digital Signal Processing 44

23 Correct Description Separate combinational and sequential circuits module count (clock, reset, and_bits, or_bits, xor_bits); input clock, reset; output and_bits, or_bits, xor_bits; reg and_bits, or_bits, xor_bits; reg [2:0] count; clock) begin if (reset) count = 0; else count = count + 1; // combinational circuits begin and_bits = & count; or_bits = count; xor_bits = ^ count; module 2008/3/12 VLSI Digital Signal Processing 45 Three registers are used 2008/3/12 VLSI Digital Signal Processing 46

24 The Description of HDL Design Examples for sequential circuits 2008/3/12 VLSI Digital Signal Processing 47 Examples D flip-flop Register D latch shifter counter Pipeline Memory FSM 2008/3/12 VLSI Digital Signal Processing 48

25 Flip-Flop Synchronous clear module d_ff (q,d,clk,clr_) ; output q ; input d,clk,clr_ ; reg q ; (posedge clk) if (~clr_) q = 0 ; else q = d ; module Asynchronous clear (posedge clk or negedge clr_) if (~clr_) q = 0 ; else q = d ; 2008/3/12 VLSI Digital Signal Processing 49 Register module register (q,d,clk,clr_, set_) ; output [7:0] q ; input [7:0] d ; input clk,clr_, set_ ; reg [7:0] q ; (posedge clk or negedge clr_ or negedge set_) if (~clr_) q = 0 ; else if (~set_) q = 8 b1111_1111 ; else q = d ; module 2008/3/12 VLSI Digital Signal Processing 50

26 D Latches D latch (enable or data) if (enable) q = data ; D latch with gated asynchronous data (enable or data or gate) if (enable) q = data & gate ; 2008/3/12 VLSI Digital Signal Processing 51 D latch with gated enable (enable or d or gate) if (enable & gate) q = d ; D latch with asynchronous reset (reset or data or gate) if (reset) q = 1 b0 else if(enable) q = data ; 2008/3/12 VLSI Digital Signal Processing 52

27 Shifter module shifter (so,si,d,clk,ld_,clr_) ; output so ; input [7:0] d ; input si,clk,ld_,clr_ ; // asynchronous clear and synchronous load reg [7:0] q ; assign so = q[7] ; (posedge clk or negedge clr_) if (~clr_) ld_ d q = 0 ; else if (~ld_) si so q = d ; shifter else clk q[7:0] = {q[6:0],si} ; module 2008/3/12 VLSI Digital Signal Processing 53 Counter module bcd_counter(count,ripple_out,clr,clk) ; output [3:0] count ; output ripple_out ; reg [3:0] count ; input clr,clk ; wire ripple_out = (count == 4'b1001)? 0:1 ; // combinational (posedge clk or posedge clr) // combinational + sequential if (clr) ; count = 0 ; else if (count == 4'b1001) count = 0 ; else count = count + 1 ; module 2008/3/12 VLSI Digital Signal Processing 54

28 Pipelines comb. circuits comb. circuits comb. circuits flipflops flipflops flipflops An example assign n_sum = a+b a assign p = sum * d_c n-sum // plus D flip-flops b (posedge clk) begin sum = n_sum ; c d_c = c; out = p; Dff Dff sum d_c p Dff out 2008/3/12 VLSI Digital Signal Processing 55 Memory module memory (data, addr, read, write); input read, write; input [4:0] addr; inout [7:0] data; reg [7:0] data_reg; reg [7:0] memory [0:8'hff]; parameter load_file = "cput1.txt"; assign data = (read)? memory [addr] : 8'hz; (posedge write) memory[addr] = data; initial $readmemb (load_file, memory); module 2008/3/12 VLSI Digital Signal Processing 56

29 Finite State Machine Moore model inputs comb. circuit next state memory elements current state comb. circuit outputs Mealy model inputs comb. circuit next state memory elements current state comb. circuit outputs 2008/3/12 VLSI Digital Signal Processing 57 Mealy Machine Example module mealy (in1, in2, clk, reset,out); input in1, in2, clk, reset; output out; reg current_state, next_state, out; // state flip-flops clk or negedge reset) if (!reset) current_state = 0; else current_state = next_state; // combinational: next-state and outputs or in2 or current_state) case (current_state) 0: begin next_state = 1; out = 1'b0; 1: if (in1) begin next_state = 1'b0; out = in2; else begin next_state = 1'b1; out =!in2; case module 2008/3/12 VLSI Digital Signal Processing 58

30 The Description of HDL A complete design flow 2008/3/12 VLSI Digital Signal Processing 59 Design Example from FSM Traffic Light Controller Picture of Highway/Farmroad Intersection: Farmroad FL C HL Highway Highway HL C FL Farmroad 2008/3/12 VLSI Digital Signal Processing 60

31 Specifications Traffic Light Controller? Tabulation of Inputs and Outputs: Input Signal reset C TS TL Output Signal HG, HY, HR FG, FY, FR ST Description place FSM in initial state detect vehicle on farmroad short time interval expired long time interval expired Description assert green/yellow/red highway lights assert green/yellow/red farmroad lights start timing a short or long interval? Tabulation of Unique States: Some light configuration imply others State S0 S1 S2 S3 Description Highway green (farmroad red) Highway yellow (farmroad red) Farmroad green (highway red) Farmroad yellow (highway red) 2008/3/12 VLSI Digital Signal Processing 61 The block diagram C TS TL Comb. circuits n_state FF s state Comb. circuits HR HG HY FR FG FY 2008/3/12 VLSI Digital Signal Processing 62

32 State transition diagram TL C/ST TS S1 TS/ST TL + C Reset S0 TS/ST S3 TS TL + C/ST S2 TL C S0: HG S1: HY S2: FG S3: FY 2008/3/12 VLSI Digital Signal Processing 63 Verilog Description module traffic_light(hg, HY, HR, FG, FY, FR,ST_o, tl, ts, clk, reset, c) ; output HG, HY, HR, FG, FY, FR, ST_o; input tl, ts, clk, reset, c ; reg ST_o, ST ; reg[0:1] state, next_state ; parameter EVEN= 0, ODD=1 ; parameter S0= 2'b00, S1=2'b01, S2=2'b10, S3=2'b11; assign HG = (state == S0) ; assign HY = (state == S1) ; assign HR = ((state == S2) (state == S3)) ; assign FG = (state == S2) ; assign FY = (state == S3) ; assign FR = ((state == S0) (state == S1)) ; 2008/3/12 VLSI Digital Signal Processing 64

33 // flip-flops (posedge clk or posedge reset) if(reset) // an asynchronous reset begin state = S0 ; ST_o = 0 ; else begin state = next_state ; ST_o = ST ; 2008/3/12 VLSI Digital Signal Processing 65 always@ (state or c or tl or ts) case(state) // state transition S0: if(tl & c) begin else begin next_state = S1 ; ST = 1 ; next_state = S0 ; ST = 0 ; TS TL C/ST S1 TS/ST TL + C Reset S0 TS/ST S3 TS TL + C/ST S2 TL C 2008/3/12 VLSI Digital Signal Processing 66

34 S1: if (ts) begin next_state = S2 ; ST = 1 ; else begin next_state = S1 ; ST = 0 ; S2: if(tl!c) begin next_state = S3 ; ST = 1 ; else begin next_state = S2 ; ST = 0 ; TL C/ST TS S1 TS/ST TL + C Reset S0 TS/ST S3 TS TL + C/ST S2 TL C 2008/3/12 VLSI Digital Signal Processing 67 S3: if(ts) begin next_state = S0 ; ST = 1 ; else begin next_state = S3 ; ST = 0 ; case module TL + C Reset S0 TL C/ST TS/ST TS S1 S3 TS/ST TS TL + C/ST S2 TL C 2008/3/12 VLSI Digital Signal Processing 68

35 Finally 2008/3/12 VLSI Digital Signal Processing 69 Tips Separate combinational and sequential circuits always know your target circuits Separate structured circuits and random logic structured: data path, XORs, MUXs random logic: control logic, decoder, encoder Blocking and Non-blocking Code Organize circuit first!!! Design rules 2008/3/12 VLSI Digital Signal Processing 70

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