I 3 I 2. ! Language of logic design " Logic optimization, state, timing, CAD tools
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1 Course Wrap-up Let s Try the Priority Encoder One More Time = =! Priority Encoder Revisited! What (We Hope) You Learned I 3 O 3 I j O j! Design Methodology! I 2 O 2 I O I O Zero Oj Ij Ij CS 5 - Spring 27 Lecture #29: Recap - CS 5 - Spring 27 Lecture #29: Recap - 2 Let s Try the Priority Encoder One More Time What we HOPE you learned in CS 5! Language of logic design " Logic optimization,, timing, CAD tools! Concept of in digital systems " Analogous to variables and program counters in software systems! Hardware system building " Datapath + = digital systems! Hardware system design methodology " Hardware description languages: Verilog " Tools to simulate design behavior: output = function (inputs) " Logic compilers synthesize hardware blocks of our designs " Mapping onto programmable hardware (code generation)! Contrast with software design " Both map specifications to physical devices " Both must be flawless the price we pay for using discrete math CS 5 - Spring 27 Lecture #29: Recap - 3 CS 5 - Spring 27 Lecture #29: Recap - 4 Current of digital design! Changes in industrial practice " Larger designs " Shorter time to market " Cheaper products! Scale " Pervasive use of computer-aided design tools over hand methods " Multiple levels of design representation! Time " Emphasis on abstract design representations " Programmable rather than fixed function components " Automatic synthesis techniques " Importance of sound design methodologies! Cost " Higher levels of integration " Use of simulation to debug designs CS 5: concepts/skills/abilities! Basics of logic design (concepts)! Sound design methodologies (concepts)! Modern specification methods (concepts)! Familiarity with full set of CAD tools (skills)! Appreciation for differences and similarities (abilities) in hardware and software design New ability: to accomplish the logic design task with the aid of computer-aided design tools and map a problem description into an implementation with programmable logic devices after validation via simulation and understanding of the advantages/disadvantages as compared to a software implementation CS 5 - Spring 27 Lecture #29: Recap - 5 CS 5 - Spring 27 Lecture #29: Recap - 6
2 Representation of Digital Designs! Physical devices (transistors, relays)! Switches! Truth tables! Boolean algebra! Gates! Waveforms! Finite behavior! Register-transfer behavior! Concurrent abstract specifications Simulation, Chipscope & Complex System Description (e.g., SDRAM) Verilog Structural & Behaviorial Descriptions Digital System Design! Door combination lock: " Punch in 3 values in sequence and the door opens; if there is an error the lock must be ; once the door opens the lock must be " Inputs: sequence of input values, " Outputs: door open/close " Memory: must remember combination or always have it available as an input CS 5 - Spring 27 Lecture #29: Recap - 7 CS 5 - Spring 27 Lecture #29: Recap - 8 Implementation in Software integer combination_lock ( ) { integer v, v2, v3; integer error = ; static integer c[3] = 3, 4, 2; v = read_value( ); if (v!= c[]) then error = ; v2 = read_value( ); if (v2!= c[2]) then error = ; v3 = read_value( ); if (v2!= c[3]) then error = ; Implementation as a Sequential Digital System! Encoding: " How many bits per input value? " How many values in sequence? " How do we know a input value is entered? " How do we represent the s of the system?! Behavior: " Clock wire tells us when it s ok to look at inputs (i.e., they have settled after change) " Sequential: sequence of values must be entered " Sequential: remember if an error occurred " Finite- specification value } if (error == ) then return(); else return (); CS 5 - Spring 27 Lecture #29: Recap - 9 CS 5 - Spring 27 Lecture #29: Recap - open/ Abstract Control! Finite- Diagram " States: 5 s # Represent point in execution of machine # Each has outputs " Transitions: 6 from to, 5 self transitions, global # Changes of occur when says it s ok # Based on value of inputs " Inputs:,, results of comparisons " Output: open/ C!=value C2!=value C3!=value S S2 S3 OPEN C=value C2=value CS 5 - Spring 27 Lecture #29: Recap - C3=value open Data-path vs. Control! Internal Structure " Data-path # Storage for combination # Comparators " Control # Finite- machine ler # Control for data-path # State changes led by value comparator C C2 C3 multiplexer CS 5 - Spring 27 Lecture #29: Recap - 2 ler open/
3 Finite- Machine! Finite- Machine " Refine diagram to include internal structure =C CS 5 - Spring 27 Lecture #29: Recap - 3 not not not S S2 S3 OPEN open =C2 =C3 Finite- Machine! Finite- Machine " Generate table (much like a truth-table) next open/ S C S S C S S S2 C2 S2 S2 C2 S2 S2 S3 C3 S3 S3 C3 S3 S3 OPEN open OPEN OPEN open CS 5 - Spring 27 Lecture #29: Recap - 4 not not not S S2 S3 OPEN =C =C2 =C3 open Encoding! Encode State Table " State can be: S, S2, S3, OPEN, or # Needs at least 3 bits to encode:,,,, # And as many as 5:,,,, # Choose 4 bits:,,,, " Output can be: C, C2, or C3 # needs 2 to 3 bits to encode # choose 3 bits:,, " Output open/ can be: open or # needs or 2 bits to encode # choose bits:, CS 5 - Spring 27 Lecture #29: Recap - 5 Encoding! Encode State Table " State can be: S, S2, S3, OPEN, or # Choose 4 bits:,,,, " Output can be: C, C2, or C3 # Choose 3 bits:,, " Output open/ can be: open or # Choose bits:, next open/ CS 5 - Spring 27 Lecture #29: Recap - 6 good choice of encoding! is identical to last 3 bits of open/ is identical to first bit of Controller Implementation! Implementation of the Controller ler open/ special circuit element, called a register, for remembering inputs when told to by comb. logic open/ Design Hierarchy code registers data-path multiplexer comparator register digital system switching networks registers logic combinational logic CS 5 - Spring 27 Lecture #29: Recap - 7 CS 5 - Spring 27 Lecture #29: Recap - 8
4 Design Methodology Structure and Function (Behavior) of a Design Simulation HDL Specification Verification: Design Behave as Required? Functional: I/O Behavior Register-Level (Architectural) Logic-Level (Gates) Transistor-Level (Electrical) Timing: Waveform Behavior Synthesis Generation: Map Specification to Implementation Combinational Logic Implementation! K-map method to map truth tables into minimized gate level descriptions! Alternative implementation approaches: " Two-level logic, multi-level logic, logic implementation with multiplexers " Programmable logic in the form of PLAs, ROMs, Muxes, " Field programmable logic in the form of devices like Xilinx! Combinational logic building blocks " Arithmetic and logic units, including adders/subtractors and other arithmetic functions (e.g., combinational multipliers) CS 5 - Spring 27 Lecture #29: Recap - 9 CS 5 - Spring 27 Lecture #29: Recap - 2 Sequential Logic Implementation! Models for representing sequential circuits " Abstraction of sequential elements " Finite machines and their diagrams " Inputs/outputs " Mealy, Moore, and synchronous Mealy machines! Finite machine design procedure " Deriving diagram " Deriving transition table " Determining next and output functions " Implementing combinational logic! Sequential logic building blocks " Registers, Register files (with multiple read and write ports), Shifters, Counters, RAMs " Arbitrators State Machine Implementation! Partitioned State Machines " Ways to organize single complex monolithic machine into simpler, interacting machines based on functional partitioning # Time approach offers one conceptual method # Much more relevant is what you likely did in your course project! Issues of synchronization across independently ed subsystems " Synchronization of signals " Four cycle handshake CS 5 - Spring 27 Lecture #29: Recap - 2 CS 5 - Spring 27 Lecture #29: Recap - 22! Exam Group 2! Friday, May, 2:3-3:3 PM! Room: 45 Dwinelle! (Long) Design Specification in English for an interesting digital subsystem " Function described in terms of desired input/output behavior " You will need to be able to hand generate waveform diagrams to demonstrate that you understand the design specification!! You may have to partition the subsystem into and datapath " Design the part as one or more interacting Finite State Machines # State Diagrams as well as Verilog for " Design the datapath blocks # Behavioral Verilog mostly, but gate level hand-drawn schematics for some selected parts! You may have to revise the design to improve its performance! For an example, see CS 5 - Spring 27 Lecture #29: Recap - 23 CS 5 - Spring 27 Lecture #29: Recap - 24
5 Past Final Exams! Fall 25: Statistics Coprocessor " Spec for calculation inside processor " Handshake for processor-coprocessor communications " High Level Design, Datapath Components, Coprocessor State Machine, Verilog Description! Spring 24: Content-Addressable Memory " Memory interface and functional specification " High Level Design, Datapath Components, Memory Controller State Machine, Verilog Description, Performance Improvement! Spring 2: Elevator System " Complex system behavior " High Level Design, Datapath Components, Controller State Machine, Extend from to 2 elevators, microprogrammed implementation! The Exam is conceptual and DESIGN-skills oriented! The Exam is not about obscure details of technologies like the Xilinx or Actel internal architectures! The best way to study for The Exam is to review your course project and to reflect on the process you went through in designing and implementing it!! The Exam design problem won t be a video conferencing system -- it will be some kind of digital system with and a datapath that can be specified in a couple of pages of English text!! You will need to write a lot for this Exam! Bring multiple pencils, erasers, rulers, AND AT LEAST TWO BLUE BOOKs!!! You won t need a computer or a calculator!! Open course textbook and open course notes. They probably won t help you much ;-) CS 5 - Spring 27 Lecture #29: Recap - 25 CS 5 - Spring 27 Lecture #29: Recap - 26
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