Computer Architecture and Organization: L06: Instruction Cycle

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1 Computer Architecture and Organization: L06: Instruction Cycle By: A. H. Abdul Hafez 1

2 Outlines 1. Fetch and decode 2. Determine the Type of Instruction 3. Instruction set in details 4. End 2

3 Instruction Cycle A program residing in the memory unit of the computer consists of a sequence of instructions. The program is executed in the computer by going through a cycle for each instruction. Each instruction cycle in turn is subdivided into a sequence of subcycles or phases: 1. Fetch an instruction from memory 2. Decode the instruction 3. Read the effective address from memory if indirect 4. Execute the instruction 3

4 Fetch and Decode Initially PC is loaded with the address of the first instruction in the program SC is cleared to 0, providing T 0 timing signal. The microoperations for the fetch and decode phases are: T 0 : AR PC T 1 : IR M[AR], PC PC +1 T2 : D 0,...,D 7 decode IR(12-14), AR IR(0-11), I IR(15) Since only AR is connected to the address inputs of memory, it is necessary to transfer the address from PC to AR during the clock transition associated with T0. The instruction read from memory is then placed in the IR with the clock transition of T 1 At the same time PC is incremented by one to prepare it for the address of the next instruction of the program. At T 2, the Opcode in IR is decoded, I bit is transferred to Flip Flop I, and IR part (0-11) is transferred into AR. 4

5 Fetch and Decode T 0 : AR PC To provide the data path for the transfer of PC to AR, we must apply timing signal T 0 to achieve the following connection: 1. Place the content of PC onto the bus by making the bus selection inputs S 2 S 1 S 0 equal to Transfer the content of the bus to AR by enabling the LD input of AR The next clock transition initiates the transfer from PC to AR since T 0 =1. (See Mano figure 5.8) 5

6 Fetch and Decode T 1 : IR M[AR], PC PC +1 For the second statemet, it is necessary to use timing signal T 1 to provide the following conditions in the bus system Enable the read input of memory Place the content of memory onto the bus by making S 2 S 1 S 0 = 111 Transfer the content of the bus to IR by enabling the LD input of IR Increment PC by enabling the INR input of PC The next clock transition initiates the read and increment operations since T 2 =1 (See Mano Fig 5.8) 6

7 T0: AR PC T1: IR M[AR], PC PC+1 T2: D7.D0 Decode IR(12-14), AR IR(0-11), I IR(15) T1 T S2 S1 S0 BUS Memory Unit 7 1 Read Address AR LD T 0 T 1 T 15 PC 2 Decoder 1 INR Sequence Counter 1 LD IR Clock 3 Clock Common Bus 7

8 Determine the Type of Instruction The timing signal that is active after decoding is T3. During time T3, the control unit determines the type of instruction that was just read from memory. See flowchart (at Mano Fig. 5.9) next slide. 8

9 Instruction Types The basic computer has three instruction code formats : (a) Memory reference instruction format opcode address I (Opcode = 000 through 110) (b) Register reference instruction format Register operation (Opcode = 111) (c) Input-output instruction format I/O operation (Opcode = 111) 9

10 Start AR PC IR M[AR], PC PC+1 Decode operation code in IR (12-14) AR IR(0-11), I IR(15) T0 T1 T2 (Register or I/O) =1 D 7 =0 (Memory-reference) ( I/O ) =1 =0 (register) (indirect ) =1 =0 (direct ) I I D 7 I T3 Execute input-output Instruction T3 D 7 I T3 T3 D 7 I T3 T3 D 7 I T3 T3 Execute Register-refernce Instruction AR M[AR] Nothing Execute Memory-reference Instruction Flowchart for instruction cycle (initial configuration) 10

11 Register-Reference Instructions Register ref instructions are identified when D7=1 and I=0 Execution is started with timing signal T3 and takes one clock cycle. Register ref instruction is specified by bits (0-11) of IR which also transfer to AR during time T2. D7 I T3 = r (common for all register-refernce instructions) IR( I ) = Bi [bit in IR (0-11) that specifies the operation] r: SC 0 Clear SC CLA rb 11 : AC 0 Clear AC CLE rb 10 : E 0 Clear E CMA rb 9 : AC AC Complement AC CME rb 8 : E E Complement E HLT instruction clears a startstop flip-flop S and stops the SC from counting. To restore the operation of the computer, the start-stop flip-flop must be set manually. CIR rb 7 : AC shr AC, AC(15) E, E AC (0) Circulate right CIL rb 6 : AC shl AC, AC(0) E, E AC (15) Circulate left INC rb 5 : AC AC+1 Increment AC SPA rb 4 : If (AC (15)=0) then (PC PC+1) Skip if positive SNA rb 3 : If (AC (15)=1) then (PC PC+1) Skip if negative SZA rb 2 : If (AC =0) then (PC PC+1) Skip if AC zero SZE rb 1 : If (E=0) then (PC PC+1) Skip if E zero HLT rb 0 : S 0 (S is a start-stop flip-flop) Halt 11computer

12 Start AR PC IR M[AR], PC PC+1 Decode operation code in IR (12-14) AR IR(0-11), I IR(15) T0 T1 T2 (Register or I/O) =1 D 7 =0 (Memory-reference) ( I/O ) =1 =0 (register) (indirect ) =1 =0 (direct ) I I D 7 I T3 Execute input-output Instruction T3 D 7 I T3 T3 D 7 I T3 T3 D 7 I T3 T3 Execute Register-refernce Instruction AR M[AR] Nothing Execute Memory-reference Instruction Flowchart for instruction cycle (initial configuration) 12

13 Memory-Reference Instructions Memory ref instructions are identified when D7=0. The effective address of the instruction is in AR and was placed there during timing signal T2 for direct instruction and during T3 for the indirect instruction. The execution of all Memory instructions starts from timing signal T4. Symbol Operation decoder Symbolic description AND D 0 AC AC ^ M[AR] ADD D 1 AC AC + M[AR], E Cout LDA D 2 AC M[AR] STA D 3 M[AR] AC BUN D 4 PC AR BSA D 5 M[AR] PC, PC AR+1 ISZ D 6 M[AR] M[AR]+1, if M[AR]+1=0 then PC PC

14 Memory-Reference Instructions AND to AC D 0 T 4 : DR M[AR] D 0 T 5 : AC AC ^ DR, SC 0 read operand from memory and store it in DR And AC with DR and save the result in AC ADD to AC D 1 T 4 : DR M[AR] read operand from memory and store it in DR D 1 T 5 : AC AC + DR, E Cout, SC 0 add AC with DR and save the result in AC. LDA: Load to AC D 2 T 4 : DR M[AR] D 2 T 5 : AC DR, SC 0 read operand from memory and store it in DR transferee DR to AC. STA: Store AC D 3 T 4 : M[AR] AC, SC 0 save content of AC in memory. 14

15 BUN: Branch Unconditionally This instruction transfers the program to the instruction specified by the effective address in AR. D 4 T 4 : PC AR, SC 0 transfer the address of the next instruction from AR to PC. Note: remember that PC holds the address of the next instruction. address instruction 100 BUN SPA CLA 15

16 BSA: Branch &save Address This instruction is useful for branching to a portion of the program called subroutine. When the subroutine is finished, the computer returns back to the next instruction after BSA instruction.. D 5 T 4 : M[AR] PC, AR AR+1 D 5 T 5 : PC AR, SC 0 16

17 Return Example of BSA instruction execution Memory Memory BSA BSA 135 PC=021 Next instruction 021 Next instruction.... Jump.... AR= Subroutine Save the next instruction address 135 PC= Subroutine 1 BUN 135 (a) Memory, PC, and AR at time T4 Indirect branch 1 BUN 135 (b) Memory, PC, and AR after 17 execution.

18 ISZ: Increment and skip if Zero D 6 T 4 : DR M[AR] D 6 T 5 : DR DR+1 D 6 T 6 : M[AR] DR, if (DR=0) then (PC PC+1), SC 0. This instruction increments the word specified by the effective address, and if the incremented value is zero, PC is incremented by 1 in order to skip the next instruction. Since it is not possible to increment a word inside the memory, it is necessary to read the word into DR, increment DR, and store the word back into memory. D 5 T 4 : M[AR] PC, AR AR+1 18

19 Flowchart for memory-reference instructions AND ADD LAD D 0 T4 D 1 T4 D 2 T4 DR M[AR] DR M[AR] DR M[AR] D 0 T5 D 1 T5 D 2 T5 AC AC DR AC AC + DR E Cout AC DR 19

20 Flowchart for memory-reference instructions STA BUN BSA ISZ D 3 T4 D 4 T4 D 5 T4 D 6 T4 M[AR] AC PC AR M[AR] PC AR AR+1 DR M[AR] PC AR D 5 T5 D 6 T5 DR DR+1 M[AR] DR IF (DR=0) Then (PC PC+1) D 6 T6 20

21 Start AR PC IR M[AR], PC PC+1 Decode operation code in IR (12-14) AR IR(0-11), I IR(15) T0 T1 T2 (Register or I/O) =1 D 7 =0 (Memory-reference) ( I/O ) =1 =0 (register) (indirect ) =1 =0 (direct ) I I D 7 I T3 Execute input-output Instruction T3 D 7 I T3 T3 D 7 I T3 T3 D 7 I T3 T3 Execute Register-refernce Instruction AR M[AR] Nothing Execute Memory-reference Instruction CAO, Flowchart by Dr. for A.H. instruction Abdul Hafez, cycle (initial CE Dept. configuration) HKU 21

22 Input-Output Configuration The terminal devices send and receive serial information. The INPR and OUTR communicate serially with terminals and in parallel with the AC. FGI and FGO are two single bit flip-flops needed to synchronize the timing rate difference between the terminals and the computer. 22

23 Input operation Initially, FGI is cleared to 0. When a key is struck in the keyboard, an 8-bit code is shifted into INPR and the input flag FGI IS SET TO 1. As long as the flag FGI=1, the content of INPR cannot be changed with a new code. The computer checks the FGI flag, if it is 1, the information in INPR is transferred into AC in parallel and the FGI is cleared to 0. Once the flag is cleared, new information code can be shifted into INPR by striking another key. FGO Printer Receiver interface OUTR AC Keyboard Transmitter interface INPR FGI 01 23

24 Output operation Initially, FGO is set to 1. The computer checks the flag bit, if it is 1, the information from AC is transferred in parallel into OUTR and FGO is cleared to 0. The output device accepts the coded information, prints the corresponding character, and when the operation is completed, it sets FGO to 1. As long as the flag FGO is cleared, the computer does not load a new character code into OUTR. FGO 10 Printer Receiver interface OUTR AC Keyboard Transmitter interface INPR FGI 0 24

25 Input-Output Instructions Input-output instructions are needed for transferring information to and from AC register, for checking the input and output flags and for controlling the interrupt facility. Input-output instructions have op-code 1111 and are recognized when D7=1 and I=1. The execution of all input-output instructions is done during timing signal T3. D7 I T3 =p (common for all input-output instructions) IR( I ) = Bi [bit in IR (6-11) that specifies the instructions] p: SC 0 Clear SC INP pb 11 : AC(0-7) INPR, FGI 0 Input character OUT pb 10 : OUTR AC (0-7), FGO 0 Output character SKI pb 9 : if (FGI=1) then (PC PC + 1) Skip on input flag SKO pb 8 : if (FGO=1) then (PC PC + 1) Skip on output flag ION pb 7 : IEN 1 Interrupt enable ON IOF pb 6 : IEN 0 Interrupt enable OFF 25

26 The end of the Lecture Thanks for your time Questions are welcome 26

Basic Computer Organization and Design Part 2/3

Basic Computer Organization and Design Part 2/3 Adapted by Dr. Adel Ammar Computer Organization Basic Computer Instructions Basic Computer Instruction Format Memory-Reference Instructions (OP-code = 000