EEE111A/B Microprocessors

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1 EEE111A/B Microprocessors Revision Notes Lecture 1: What s it all About? Covers the basic principles of digital signals. The intelligence of virtually all communications, control and electronic devices are controlled by microprocessors/microcontrollers (MPU/MCU) see Fig. 2. Lecture 2: Microcontrollers The Central Processing Unit (CPU or MPU) in the standard von Neumann computer communicates via a single Data bus to a memory unit, input and output ports Fig 2. The single memory unit holds both Program and Data binary code. In the Harvard computer, a separate memory unit with separate Data bus is used for each of the Program and Data memories Fig. 3. A microcontroller (MCU) is a microprocessor (MPU) CPU integrated in the one IC with Program memory, Data memory, input and output ports and peripheral functions such as analog to digital converters, counter/timers, serial ports etc Fig. 1. All computing engines spend their time: fetching down instructions from the Program memory or store. executing the instruction. In the case of a Harvard computer, the two activities can happen in parallel with the n th instruction being executed with data from the Data memory (Data or File store) whilst simultaneously the (n + 1) th is being fetched from the Program store Fig. 4. The Fetch unit comprises: a Program counter to point to the cell in the Program store holding the instruction code about to be fetched down. a 2-register pipeline with the (n+1) th instruction code being stored at the top entry point and the n th instruction being held in the bottom exit register. The Execution unit comprises: an ALU to do the number crunching. a Working register to hold one of the ALU operands and maybe outcome from the ALU. Lecture 3: Introduction to the PIC16F84 Microcontroller The Microchip PIC16F84 (Figs. 1, 2& 4) isaharvard architecture microcontroller with: a Program store holding 1,024 (1K) 14-bit instructions Fig. 3. a 13-bit Program counter which can potentially address up to 8,192 (8K) instructions. a 2-deep 14-bit pipeline. an 8-bit ALU which can do the basic logic operations and addition/subtraction. 1

2 an 8-bit Working register. 2-bank Data/File store (Fig. 5) that can hold: 68 8-bit general-purpose registers (GPRs) or Files. 16 special-purpose registers (SPRs) holding, amongst other the Status register. A Status register located at File 3 which holds the Carry flag (bit 0) and the Zero flag (bit 2). The idea of a program as a logic sequence of elementary steps or instructions. Lecture 4: Introduction to the PIC16F84 Software The binary structure (Fig. 1) of a: Direct addressing instruction, such as addwf, comprising a 6-bit operation code, 1-bit destination bit (to specify W or a File as the destination of the outcome) and a 7-bit File address. The 7-bit address specifies a bank in the Data store maximum size being 2 7 = 128 Files. Literal instruction, such as addlw, with an 8-bit op-code and an 8-bit constant. Instructions categories and their effect on the Carry and Zero flags: The three Move instructions Figs. 2, 3& 5: movf which is typically used to copy data from a File to the Working register; e.g. movf h 20,w. movwf which is used to copy data from the Working register back to a File; e.g. movwf h 20. movlw which is used to put a byte constant into the Working register; e.g. movlw h FF. The two Add instructions Figs. 4, 6&7: addwf which is used to add the byte contents of a File to that of the Working register and put the byte outcome either back in the File or in W; e.g. addwf h 20,w. addlw which is used to add a literal to the contents of W; e.g. addlw 01. The concept of a program written in a symbolic manner being translated into machine code. This type of one-to-one language was called assembly language Fig. 8. Lecture 5: More PIC16F84 Instructions A closer look at the Status register as part of the bank of SPRs in the Data store Fig. 1. The bare bones Instruction set to be provided with the Examination paper. Instruction categories and their effect on the Status flags: The non-addition Arithmetic instructions: clrf (CLeaR File) which is used to zero the contents of any specified File; e.g. clrf h 30 zeros the contents of File h 30 Fig. 2. incf (INCrement File) which is used to augment the contents of any specified File and copy the outcome either back to the File or else to the Working register; e.g. incf h 30,f increments the contents of File h 30 Fig. 3. 2

3 decf (DECrement File) which is used to lessen the contents of any specified File and copy the outcome either back to the File or else to the Working register; e.g. decf h 30,f decrements the contents of File h 30. subwf (SUBtract Working register byte from File byte) which used to subtract two byte variables; e.g. subwf h 30,w subtracts the byte in W from the contents of File h 30 and puts it in W Fig. 4. bsf (Bit Set File) allows the programmer to set to 1 any bit in any File; e.g. bsf h 30,7 sets to 1 bit 7 in File h 30 Fig. 5. bcf (Bit Clear File) allows the programmer to set to 0 any bit in any File; e.g. bcf h 30,2 clears to 0 bit 2 in File h 30. Skip and Jump instructions: goto (GO TO) which causes program execution to jump to another part of the program; e.g. goto D_LOOP jumps to the instruction at the labelled instruction D_LOOP Fig. 6. btfsc (Bit Test File and Skip if bit is Clear) permits the programmer to skip over the next instruction if the specified bit in the target File is clear; e.g. btfsc h 30,5 skips if bit 5 in File h 30 is 0 Fig. 7. btfss (Bit Test File and Skip if bit is Set) permits the programmer to skip over the next instruction if the specified bit in the specified File is set; e.g. btfss h 30,3 skips if bit 3 in File h 30 is 1. Program loops using the Conditional Skip and Goto instructions. Lecture 6: Comparison of Numbers and Logic Operations Comparing for magnitude two unsigned numbers by subtracting them and checking the state of the Carry (NOT Borrow) and Zero flags in the Status register Figs. 1 & 2. How to test whether the contents of a File is zero by copying a File to itself and thereby activating the Z flag; e.g. movf h 30,f. Logic operations: ANDing a bit with 0 clears it. ANDing a bit with 1 does not alter it. IORing a bit with 0 does not alter it. IORing a bit with 1 sets it. The Logic instruction category: comf (COMplement File) which is used to invert all bits of any specified File; e.g. comf h 30 inverts (logic NOT) the contents of File h 30 Fig. 3. andwf (AND Working register with File) which is used to logic AND the byte in the specified File with that in the Working register. The outcome can either be put back in the File or else in the Working register; e.g. andwf h 30,f ANDs the contents of File h 30 with W and puts the outcome in File h 30 Fig. 4. andlw (AND Literal byte with the byte in the Working register) which is used to logic AND the constant byte specified with the contents of the Working register; e.g. 3

4 andlw b ANDs the contents of W with the constant b (h FC ) effectively clearing the lower two bits of W. iorwf (Inclusive-OR Working register with File) which is used to logic Inclusive-OR the byte in the specified File with that in the Working register and copy the outcome either back in the File or else in the Working register; e.g. ior h 30,w IORs the contents of File h 30 with W and puts the outcome in W Fig. 5. iorlw (Inclusive-OR Literal byte with the byte in the Working register) which is used to logic Inclusive-OR the constant byte specified with the contents of the Working register; e.g. iorlw b Inclusive-ORs the contents of W with the constant b (h 03 ) effectively setting the lower two bits of W. Lecture 7: Subroutines The advantages and disadvantages of modular programming. The subroutine as the building block of modular programming Fig. 2: The call instruction used to go to the entry instruction. The return instruction used to come back to the caller at the exit point of a subroutine. The purpose of the stack as a storage area to ensure that a subroutine can always return to the caller program no matter from where it is called Fig. 3: To save (push) the contents of the 13-bit Program Counter when a call instruction is executed that is the address of the jumping-off point. To retrieve (pop) the previously saved jumping-off address from the stack when a return instruction is executed. Lecture 8: Ports and Pins The PIC16F84 has two integral Parallel ports which connect to the external world via pins on the IC Fig. 4. Port A has five bits connected to five pins labelled RA4 RA0 corresponding to bits 5 through 0 of File 05. Port B has eight bits connected to pins labelled RB7 RB0 corresponding to bits 7 through 0 of File 06. Any pin can be set up in software to be either an input (can be read by software as the corresponding bit in the port) or an output (can be twiddled by changing the corresponding bit in the port). Each port has a shadow Data Direction register in Bank 1, called a TRIS register. Each bit in a TRIS register controls the configuration of it s corresponding pin, with a 0 for Output and 1 for Input (0 Output; 1 Input). TRISA is located at File h 85 in Bank 1 and controls the function of pins RA4 RA0. TRISB is located at File h 86 in Bank 1 and controls the function of pins RB7 RB0. For example to make pin RA0 an output and the rest of the Port A pins to be an input, we have: 4

5 bsf STATUS,RP0 ; Switch to Bank1 movlw b ; Bit settings for RA0 to be Output movwf TRISA ; Copy to Direction A register bcf STATUS,RP0 ; Back to Bank0 Where a pin is configured as an input, you can read if its state is low (logic 0) or high (logic 1) by checking the corresponding bit in the appropriate port. For example: CHECK btfss PORTA,4 ; Check the state of pin RA4. IF set THEN skip goto CHECK ; ELSE go to CHECK Where a pin is configured as an output, you can write to it making it low (logic 0) or high (logic 1) by clearing or setting the corresponding bit in the appropriate port. For example: PULSE bsf PORTA,0 ; Bring pin RA0 high. bcf PORTA,0 ; Bring pin RA0 low. goto PULSE ; and repeat forever! L A T E X2ε eee111_revision.tex Version S.J. Katzen April 22,

6 Instruction Mnemonic Operation Flags Arithmetic Add W and File addwf f,d (d) <- W + (f) Add Literal and W addlw L W <- #L + W Bit Clear File bit n bcf f,n f n <- 0 Bit Set File bit n bsf f,n f n <- 1 Clear File clrf f (f) <- 00 Increment File incf f,d (d) <- (f) + 1 Decrement File decf f,d (d) <- (f) - 1 Subtract W from File subwf f,d (d) <- (f) - W Movement Move File movf f,d (d) <- (f) Move W to File movwf f W <- (f) Move Literal to W movlw L W <- #L Logic AND W and File andwf f,d (d) <- W (f) AND Literal and W andlw L W <- #L W Complement File comf f (f) <- (f) Inclusive OR W and File iorwf f,d (d) <- W + (f) Inclusive OR Literal and W iorlw L W <- #L + W Skip and Jump Bit Test File, Skip if Clear btfsc f,b b == 0? PC++ : PC Bit Test File, Skip if Set btfss f,b b == 1? PC++ : PC Call (jump to) subroutine call aaa (TOS) <- pc, pc <- aaa Go to address goto aaa pc <- aaa Return from subroutine return pc <- (TOS) : Flag operates normally : Flag not affected aaa : Address of instruction b : Bit b (0 7) in file C : Carry or Borrow, bit 0 in F3 Z : Zero, bit 2 in F3 d : Destination; 0 = W, 1 = file W : Working register L : 8-bit Literal == : Equivalent to ++ : Increment ( ) : Contents of A?S1:S2 : IF A is True THEN DO S1 ELSE DO S2 TOS : Top Of Stack f : File d : File or W pc : Program Counter Z C 6

7 PIC16F83/84 Special-Purpose Register file summary File Name Power-on All other address Reset Resets Bank 0 00h INDF Uses contents of this to address Data memory (not a physical register) 01h TMR0 8-bit real-time clock/counter XXXX XXXX UUUU UUUU 02h PCL 1 Lower-order 8 bits of the Program Counter h STATUS 1 IRP RP1 RP0 TO PD Z DC C XXX 000??UUU 04h FSR Indirect Data memory address pointer 0 XXXX XXXX UUUU UUUU 05h PORTA RA4 RA3 RA2 RA1 RA0 X XXXX U UUUU 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 XXXX XXXX UUUU UUUU 08h EEDATA Data EEPROM Data register XXXX XXXX UUUU UUUU 09h EEADR Data EEPROM Address register XXXX XXXX UUUU UUUU 0Ah PCLATH Write buffer for top 5 PC bits Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF X U Bank 1 80h INDF Uses contents of this to address Data memory (not a physical register) 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS h PCL 1 Lower-order 8 bits of the Program Counter h STATUS 1 IRP RP1 RP0 TO PD Z DC C XXX 000??UUU 84h FSR Indirect Data memory address pointer 0 XXXX XXXX UUUU UUUU 85h TRISA Port A Direction Register h TRISB Port B Data Direction Register h EECON1 Data EEPROM Data register XXXX XXXX UUUU UUUU 89h EECON2 EEPROM Control register (not a physical register) 8Ah PCLATH Write buffer for top 5 PC bits Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF X U X Not known U Unchanged? Value depends on whether a Watchdog Reset and if in Sleep mode before Reset. Unimplemented; reads as 0. Note 1: Next instruction address if PIC in Sleep mode. 7