COURSE DELIVERY PLAN - THEORY Page 1 of 6

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1 COURSE DELIVERY PLAN - THEORY Page 1 of 6 Department of Information Technology B.E/B.Tech/M.E/M.Tech : B.Tech Information Technology Regulation: 2013 Sub. Code / Sub. Name : CS6303 / Computer Architecture Unit : I LP: CS6303 Rev. No: 00 Date: OVERVIEW & INSTRUCTIONS: Eight ideas Components of a computer system Technology Performance Power wall Uniprocessors to multiprocessors; Instructions operations and operands representing instructions Logical operations control operations Addressing and addressing modes. This unit deals with the Functional units, Uniprocessor to multiprocessor, instructions, control and logical operations, addressing modes. 1 Introduction to computer architecture, Eight ideas 2-Ch.2;Pg Components of a computer system, Technology 1-Ch.1;Pg.13-26, 3-Ch.3;Pg Performance, Power wall, SPEC benchmark 1-Ch.1;Pg.28-48, 2-Ch.2;Pg Uniprocessors to multiprocessors 1-Ch.1;Pg.43-46, 2-Ch.2;Pg Instructions: Language of the machine, Operations of computer hardware, Operands of computer hardware 1-Ch.2;Pg.62-80, 2-Ch.2;Pg Representing instructions in the computer 1-Ch.2;Pg Logical operations 1-Ch.2;Pg Instructions for making decisions, Control operations, supporting procedures in computer hardware 1-Ch.2;Pg Addressing and addressing modes - MIPS Addressing Mode Summary, Decoding Machine Language 1-Ch.2;Pg , 2-Ch.2;Pg.48-57, 3-Ch.11;Pg , 4-Ch.2;Pg Content beyond syllabus covered (if any): SPEC benchmark, supporting procedures in computer hardware. Course Outcome 1: Students will be able to evaluate performance of the computer system and decode machine language * duration: 50 minutes

2 COURSE DELIVERY PLAN - THEORY Page 2 of 6 Unit : II ARITHMETIC OPERATIONS ALU - Addition and subtraction Multiplication Division Floating Point operations Subword parallelism. To gain knowledge about the various arithmetic operations that performed by ALU. 10 Designing of ALU, signed and unsigned numbers, Addition and subtraction, using a hardware description language-verilog. 11 Multiplication - Sequential Version of the Multiplication Algorithm and Hardware, Example for a multiply algorithm, Signed multiplication 12 Faster multiplication, Multiply in MIPS, summary, Division A division algorithm and hardware 1-Ch.2;Pg.73-80, 1-Ch.3;Pg , 1- Ch.B; pg.b20-b48, 2-Ch.3;Pg , 4-Ch.3;Pg Ch.4;Pg , 1-Ch.3;Pg , 2-Ch.3;Pg , 4-Ch.3;Pg Ch.4;Pg , 1-Ch.3;Pg , 2-Ch.3;Pg , 6-Ch.4;Pg Example for a divide algorithm, signed division, Faster division, Divide in MIPS 14 Floating Point - Floating point representation, Floating point addition, Binary floating point addition 15 Floating point multiplication, Binary floating point multiplication, Floating point instructions in MIPS, Accurate arithmetic 1-Ch.3;Pg , 4-Ch.3;Pg Ch.3;Pg , 3-Ch.9;Pg , 4-Ch.3;Pg , 6-Ch.4;Pg Ch.3;Pg , 2-Ch.3;Pg , 3-Ch.9;Pg , 4-Ch.3;Pg Subword parallelism 1-Ch.3;Pg Subword Parallelism With Max-2, Ruby B. Lee, HP. Content beyond syllabus covered (if any): Using a Hardware Description Language, Verilog. Course Outcome 2: Students will be able to design arithmetic and logic unit. * duration: 50 mins

3 COURSE DELIVERY PLAN - THEORY Page 3 of 6 Unit : III PROCESSOR AND CONTROL UNIT Basic MIPS implementation Building datapath Control Implementation scheme Pipelining Pipelined datapath and control Handling Data hazards & Control hazards Exceptions. To expose the students to the concept of pipelining. 17 Basic MIPS implementation An overview of the implementation, Logic design conventions. 1-Ch.4;Pg , 1-Ch.B;Pg.B3-B10 18 Building a datapath, creating a single data path, Example for building a data path 19 Control implementation scheme The ALU control, Designing the control unit, operation of the data path 20 Finalizing Control, example for Implementing Jumps, Why a Single- Cycle Implementation Is Not Used Today 21 Pipelining-An overview of pipelining, designing instruction sets for pipelining, pipeline hazards, structural hazards, data hazards 1-Ch.4;Pg , 2-Ch.4;Pg , 4-Ch.5;Pg Ch.4;Pg , 4-Ch.5;Pg Ch.4;Pg Ch.4;Pg , 4-Ch.5;Pg , 6-Ch.5;Pg A pipelined datapath, graphically representing pipelines 1-Ch.4;Pg , 2-Ch.4;Pg Pipelined control, seperation of control lines according to pipeline stage 1-Ch.4;Pg Data hazards: Forwarding versus Stalling, Dependence detection 1-Ch.4;Pg , 2-Ch.4;Pg Data hazards and stalls, Control hazards, Assume branch not taken, Reducing the delay of branches, Pipelined branch example 26 Dynamic branch prediction, Example for Loops and prediction, Branch hazards 27 Exceptions - How Exceptions Are Handled in the MIPS Architecture, Exceptions in a Pipelined Implementation, Exception in a Pipelined Computer example Content beyond syllabus covered (if any): Nil Course Outcome 3: Students will be able to design and analyze pipelined control units 1-Ch.4;Pg , 2-Ch.4;Pg Ch.4;Pg Ch.4;Pg * duration: 50 mins

4 COURSE DELIVERY PLAN - THEORY Page 4 of 6 Unit : IV PARALLELISM Instruction-level-parallelism Parallel processing challenges Flynn's classification Hardware multithreading Multicore processors To expose the students to the concept of parallel processing architectures. 28 Parallelism and Advanced Instruction- Level Parallelism, The Concept of Speculation, Static Multiple Issue, An Example: Static Multiple Issue with the MIPS ISA 29 Example for Simple Multiple-Issue Code Scheduling, Example for Loop Unrolling for Multiple-Issue Pipelines, Dynamic Multiple- Issue Processors 30 Dynamic Pipeline Scheduling, limited amounts of ILP also limit the extent to which such stalls can be hidden. Power Efficiency and Advanced Pipelining 1-Ch.4;Pg , 3-Ch.14;Pg , 4-Ch.10;Pg Ch.4;Pg Ch.4;Pg Challenges of parallel processing 1-Ch.6;Pg , 6-Ch.7;Pg Flynn's classification 1-Ch.6;Pg , Web reference 33 Hardware multithreading 1-Ch.6;Pg Multicore processors and their performance, Performance and energy efficiency of the Intel core i7 Multicore 35 Putting multicore and SMT together, Benchmarking Four Multi cores Using the Roofline Model 1-Ch.6;Pg Ch.6;Pg Revision Content beyond syllabus covered (if any): Nil Course Outcome 4: Students will be able to design parallel processing architectures. * duration: 50 mins;

5 COURSE DELIVERY PLAN - THEORY Page 5 of 6 Unit : V MEMORY AND I/O SYSTEMS Memory hierarchy - Memory technologies Cache basics Measuring and improving cache performance - Virtual memory, TLBs - Input/output system, programmed I/O, DMA and interrupts, I/O processors. To familiarize the students with hierarchical memory system including cache memories and virtual memory. To expose the students with different ways of communicating with I/O devices and standard I/O interfaces. 37 Memory hierarchy design Introduction, Basics of Memory Hierarchies: An quick review 38 Memory technology and Optimizations, SRAM Technology, DRAM technology, Improving memory performance inside a DRAM chip 39 The Basics of Caches, Accessing a Cache, Handling Cache Misses, Handling Writes, Designing the Memory System to Support Caches 40 Measuring and Improving Cache Performance, Calculating Cache Performance and Average Memory Access Time, Locating a Block in the Cache, Reducing the Miss Penalty Using Multilevel Caches 1-Ch.5;Pg , 4-Ch.12;Pg Ch.5;Pg , 6-Ch.9;Pg Ch.5;Pg , 3-Ch.4;Pg , 4-Ch.12;Pg Ch.5;Pg Virtual memory, Placing a Page and Finding It Again, Page Faults, Integrating Virtual Memory, TLBs, and Caches, Implementing Protection with Virtual Memory, Handling TLB Misses and Page Faults 1-Ch.5;Pg , 2-Ch.8;Pg , 4-Ch.12;Pg Input/output system 4-Ch.12;Pg programmed I/O 3-Ch.4;Pg , 4-Ch.12;Pg , 6-Ch.987;Pg DMA and interrupts 3-Ch.4;Pg , 4-Ch.12;Pg , 6-Ch.9;Pg I/O processors 3-Ch.4;Pg , 6-Ch.9;Pg Content beyond syllabus covered (if any): Nil Course Outcome 5: Students will be able to evaluate performance of memory systems. * duration: 50 mins

6 COURSE DELIVERY PLAN - THEORY Page 6 of 6 Sub Code / Sub Name: CS6303 / Computer Architecture Mapping CO PO: PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 CO1 A B A B C C CO2 A A CO3 A A A B B CO4 A A A B B B A CO5 A A A B B A B A Excellent; B Good; C - Average Text Books: 1. David A. Patterson and John L. Hennessey, Computer organization and design, Morgan Kauffman, Elsevier, Fifth edition, erence books: 2. V.Carl Hamacher, Zvonko G. Varanesic and Safat G. Zaky, Computer Organisation, VI edition, McGraw-Hill Inc, William Stallings Computer Organization and Architecture, Seventh Edition, Pearson Education, Vincent P. Heuring, Harry F. Jordan, Computer System Architecture, Second Edition, Pearson Education, Govindarajalu, Computer Architecture and Organization, Design Principles and Applications", first edition, Tata McGraw Hill, New Delhi, John P. Hayes, Computer Architecture and Organization, Third Edition, Tata McGraw Hill, Prepared by Approved by Signature Name Designation Dr. C. Yaashuwanth, Ms. J. Sharon Ranjitha Esther Assoc. Prof / IT AP / IT Dr.D.Balasubramaniam HOD / IT Date 27/06/ /06/2015 Remarks *: * If the same lesson plan is followed in the subsequent semester/year it should be mentioned and signed by the Faculty and the HOD