The Virtex FPGA and Introduction to design techniques
|
|
|
- Judith Rose
- 5 years ago
- Views:
Transcription
1 The Virtex FPGA and Introduction to design techniques SM098 Computation Structures Lecture 6 Simple Programmable Logic evices Programmable Array Logic (PAL) AN-OR arrays are common blocks in SPL and CPL architectures Implements two level logic functions like: F = ABC + B + C SM098 Computation Structures Lecture 6 2
2 36 Product Term Allocator Additional Product Terms (from other macrocells) Product Term Set 0 Product Term Clock Product Term Reset Product Term OE Additional Product Terms (from other macrocells) Global Set/Reset Global Clocks 3 S /T R OUT PTOE X5878 To FastCONNECT Switch Matrix To Blocks X5879 Simple Programmable Logic evices I - I 8 CLK/ I0 8 Programmable AN Array 32 x 64 Vantis PALV6V8 MC 0 MC MC 2 MC 3 MC 4 MC 5 MC 6 MC 7 OE/I X 0 OE V CC To Adjacent Macrocell Macrocell SG SL0 X 0 X 0 X SL X CLK 0 0 X *SG SL0 X From Adjacent Pin SM098 Computation Structures Lecture 6 3 Complex Programmable Logic evices CPLs have much higher capacity than SPLs, but the architecture is similar. Function block Xilinx XC9500 architecture Macrocell JTAG Port 3 JTAG Controller In-System Programming Controller From 36 FastCONNECT Switch Matrix Programmable AN-Array Product Term Allocators OUT PTOE To FastCONNECT Switch Matrix To Blocks 36 8 Function Block Macrocells to 8 Macrocell 8 /GCK /GSR /GTS 3 2 or 4 Blocks FastCONNECT Switch Matrix Function Block 2 Macrocells to 8 Function Block 3 Macrocells to 8 Function Block N Macrocells to 8 3 Global Global Set/Reset Clocks Macro cell SM098 Computation Structures Lecture 6 4
3 Field Programmable Gate Arrays - Xilinx XC4000 SM098 Computation Structures Lecture 6 5 Virtex Architecture SRAM based, needs external configuration memory Two main configurable elements: configurable logic blocks (CLBs) and input/output blocks (IOBs) CLBs interconnect through a general routing matrix (GRM). The VersaRing interface provides additional routing resources around the periphery of the device. The Virtex architecture also includes the following circuits that connect to the GRM. edicated block memories of 4096 bits each Clock LLs for clock-distribution delay compensation and clock domain control 3-State buffers (BUFTs) associated with each CLB that rive dedicated segmentable horizontal routing resources LL IOBs VersaRing BRAMs LL IOBs VersaRing CLBs VersaRing IOBs LL IOBs VersaRing BRAMs LL SM098 Computation Structures Lecture 6 6
4 Virtex routing resources A view from FPGA editor. Blue boxes are slices (2 slices = CLB). Grey lines are local interconnect. Red lines are long lines. Green lines are pin wires. Three switch boxes per CLB. SM098 Computation Structures Lecture 6 7 Virtex clock distribution There are four primary global clock nets that are driven by four global buffers. If these clock nets are used clock skew will not be a problem. GCLKPA3 GCLKPA2 Global Clock Rows GCLKBUF3 GCLKBUF2 Global Clock Column Global Clock Spine GCLKBUF GCLKBUF0 GCLKPA GCLKPA0 gclkbu_2.eps SM098 Computation Structures Lecture 6 8
5 Virtex IOB The Virtex IOBs are configurable to support several different high speed standards CE CE Weak Keeper SR CE CE OBUFT PA SR I CE Programmable elay IBUF SR Vref R LK CE ds022_02_09300 SM098 Computation Structures Lecture 6 9 Virtex CLB Xilinx definitions: Logic cell (LC) - 4 input LUT, carry logic and a storage element A slice consist of two LCs A CLB consists of 4.5 CLBs. The /2 LC comes from the fact that some additional logic is available for implementing functions with more than 4 inputs COUT COUT G4 G3 G2 G LUT Carry & Control SP EC YB Y Y G4 G3 G2 G LUT Carry & Control SP EC YB Y Y BY RC XB BY RC XB F4 F3 F2 F LUT Carry & Control SP EC X X F4 F3 F2 F LUT Carry & Control SP EC X X BX RC RC BX Slice Slice 0 CIN CIN slice_b.eps SM098 Computation Structures Lecture 6 0
6 Virtex slice - detailed view The additional logic are the F5 and F6 multiplexers. COUT CY YB G4 G3 G2 G I3 I2 I I0 WE LUT I O 0 INIT EC Y Y BY REV F5IN F6 XB CY F5 F5 CK WE WSO BY G X BX A4 WSH BX I INIT EC X F4 F3 F2 F I3 I2 I I0 WE LUT I O REV 0 SR CLK CE CIN SM098 Computation Structures Lecture 6 Virtex - look-up tables The Virtex LUTs can be configure to implement: 4-input LUTs 6x-bit synchronous RAM Two LUTs in one slice can be combined to implement 6x2-bit or 32x-bit synchronous RAM 6x-bit dual-port synchronous RAM 6-bit shift register SM098 Computation Structures Lecture 6 2
7 Virtex slice - FPGA Editor view SM098 Computation Structures Lecture 6 3 library ieee; use ieee.std_logic_64.all; Example entity Example is port ( A, B, C, : in std_logic; -- Inputs Reset, Clk, En : in std_logic; -- Reset, Clock, Clock enable Y : out std_logic); -- Output end Example; architecture RTL of Example is begin -- RTL process(clk) begin if rising_edge(clk) then if Reset = then Y <= 0 ; elsif En = then Y <= A xor B xor C xor ; end if; end if; end process; end RTL; How will this be implemented? How many slices? SM098 Computation Structures Lecture 6 4
8 Example SM098 Computation Structures Lecture 6 5 Example 2 8-bit adder with carry input and output How can this be implemented in a Virtex? How many slices? library ieee; use ieee.std_logic_64.all; use ieee.numeric_std.all; entity Example2 is port ( A, B : in unsigned(7 downto 0); Cin : in std_logic; R : out unsigned(7 downto 0); Cout : out std_logic); end Example2; architecture RTL of Example2 is begin -- RTL process(a, B, Cin) variable r_tmp : unsigned(8 downto 0); variable cin_tmp : integer range 0 to ; begin if Cin = 0 then cin_tmp := 0; else cin_tmp := ; end if; r_tmp := ( 0 & A) + B + cin_tmp; R <= r_tmp(7 downto 0); Cout <= r_tmp(8); end process; end RTL; SM098 Computation Structures Lecture 6 6
9 Example 2 Four slices - the carry chain is the high lighted (red) net Next slide shows this slice SM098 Computation Structures Lecture 6 7 Example 2 One full adder per slice SM098 Computation Structures Lecture 6 8
10 A Clk Reset FC [0] s[0] FC [0] [] s[] FC [] [2] s[2] FC [2] [3] s[3] FC [3] [4] s[4] FC [4] [5] s[5] FC [5] [6] s[6] FC [6] [7] s[7] FC [7] [8] s[8] FC [8] [9] s[9] FC [9] FC [0] [0] FC [] [] FC [2] [2] FC [3] [3] s[0] FC [4] [4] s[] s[2] s[3] s[4] s[5] Y library ieee; use ieee.std_logic_64.all; entity Example3 is port ( A : in std_logic; Clk, Reset : in std_logic; Y, Y2 : out std_logic); end Example3; Example 3 - shift register architecture RTL of Example3 is signal S, S2 : std_logic_vector(5 downto 0); begin -- RTL 6 FFs 8 slices Shift : process(clk, Reset) begin if Reset = then S <= (others => 0 ); elsif rising_edge(clk) then S <= S(4 downto 0) & A; end if; end process; Shift2 : process(clk) begin if rising_edge(clk) then S2 <= S2(4 downto 0) & A; end if; end process; Y <= S(5); Y2 <= S2(5); end RTL A Clk 0 SRL6 A0 A A2 A3 CLK un2.i_ /2 slice F un2.out[0] Y2 SM098 Computation Structures Lecture 6 9 Virtex Block RAM Each Block RAM is a synchronous dual-ported 4096-bit RAM with independent control signals for each port ata widths may be configured independently WEA ENA RSTA CLKA ARA[#:0] IA[#:0] WEB ENB RSTB CLKB ARB[#:0] IB[#:0] RAMB4_S#_S# OA[#:0] OB[#:0] You have actually already used the block RAM in one lab. Virtex evice # of Blocks Total Block SelectRAM Bits XCV ,768 XCV ,960 XCV ,52 XCV ,344 XCV ,536 XCV ,920 XCV ,304 XCV ,688 XCV ,072 SM098 Computation Structures Lecture 6 20
11 Virtex LLs A elayed Locked Loop (LL) can align internal and external clocks. Effectively eliminates onchip clock distribution delay. This maximizes the achievable speed. Chip Chip 2 LL LL Clock Clock ata Comparator Error elay Clock distribution Virtex have four LLs. The LLs can also be used to divide or double the incoming clock frequency internally. The output of the LL can drive the global clock routing recourses and clock skew can be eliminated. SM098 Computation Structures Lecture 6 2 Virtex compared to Virtex-E Virtex Maximum Block RAM Maximum evice System Gates CLB Array Logic Cells Available Bits SelectRAM+ Bits XCV50 57,906 6x24, ,768 24,576 XCV00 08,904 20x30 2, ,960 38,400 XCV50 64,674 24x36 3, ,52 55,296 XCV ,666 28x42 5, ,344 75,264 XCV ,970 32x48 6, ,536 98,304 XCV ,252 40x60 0, ,920 53,600 XCV600 66, 48x72 5, ,304 22,84 XCV ,439 56x84 2, ,688 30,056 XCV000,24,022 64x96 27, , ,26 Virtex-E evice System Gates Logic Gates CLB Array Logic Cells ifferential Pairs User BlockRAM Bits istributed RAM Bits XCV50E 7,693 20,736 6 x 24, ,536 24,576 XCV00E 28,236 32, x 30 2, ,920 38,400 XCV200E 306,393 63, x 42 5, ,688 75,264 XCV300E 4,955 82, x 48 6, ,072 98,304 XCV400E 569,952 29, x 60 0, ,840 53,600 XCV600E 985,882 86, x 72 5, ,92 22,84 XCV000E,569,78 33, x 96 27, ,26 393,26 XCV600E 2,88,742 49, x 08 34, , ,664 XCV2000E 2,54,952 58, x 20 43, ,360 64,400 XCV2600E 3,263, , x 38 57, ,664 82,544 XCV3200E 4,074, , x 56 73, ,968,038,336 SM098 Computation Structures Lecture 6 22
12 How to find the best implementation? You have to know the target architecture in order to make efficient design implementations Synthesis tools will not always provide the optimal solution. Structural coding can aid the synthesis tool - provided that the designer knows a better solution Use vendor specific module generations tools, such as Xilinx CoreGenerator. CoreGenerator can generate optimized cores such as arithmetic functions, FFTs, FIR filters etc SM098 Computation Structures Lecture 6 23 CoreGenerator flow CORE Generator VHO VEO HL Editor Behavioral Simulation Models VHL Verilog HL Test Bench EN Verilog & VHL Instantiation Symbol VHL Verilog Synthesizer EIF Xilinx CoreLib CORE Generator or IP Install SF HL Editor <Vendor> CoreLib Timing Simulation Flow Schematic Editor Schematic Simulation Tools simprim Unified EIF Functional Simulation Flow EIF VHL Verilog Unisim VITAL & Verilog simprim Implementation Tools VITAL, Verilog, Gate-level EIF VHL Verilog SF X8974 SM098 Computation Structures Lecture 6 24
13 What is best - what are the requirements? Some requirements can be: Short time to market Low resource usage - area High operating frequency Low power consumption (Mikael will talk about this next lecture) epending on what requirement is most important, different design solutions will be oprimal for the particular requirements SM098 Computation Structures Lecture 6 25 Time to market If time to market is the most important requirement your boss will not be satisfied if you try to optimize other requirements that are already met. Your will not get a raise if you manage to save 5 CLBs because you spent two days optimizing a counter. This probably how most of you work in the lab. You try to meet the lab requirements before the deadline but don t care much if your solution is the most efficient in terms of speed or area. Am I right? SM098 Computation Structures Lecture 6 26
14 Resource usage If you are optimizing for area you should consider Sequential execution instead of parallel execution Bit serial implementation of data paths Scheduling of data paths, interleaving of resources in time Choosing the algorithm that minimizes area... SM098 Computation Structures Lecture 6 27 Speed If you are optimizing for speed you should consider Parallel execution Pipelining Choosing the fastest algorithm... Next and last lecture I will give you a practical example on how one algorithm, a FIR filtering, can be implemented in hardware. We will optimize it for area and for speed and we will come up with two separate implementations SM098 Computation Structures Lecture 6 28
15 Final question Which of these two implementations are optimal? Max x T Max x T A 2T A T B C 3A 2T T A F B C A T 2T 3A F 3A A T T S ecoder S ecoder A A Critical path = 3T Area = 8A Critical path = 4T Area = 6A SM098 Computation Structures Lecture 6 29
Programmable Logic. Simple Programmable Logic Devices
Programmable Logic SM098 Computation Structures - Programmable Logic Simple Programmable Logic evices Programmable Array Logic (PAL) AN-OR arrays are common blocks in SPL and CPL architectures Implements
Today. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses
Today Comments about assignment 3-43 Comments about assignment 3 ASICs and Programmable logic Others courses octor Per should show up in the end of the lecture Mealy machines can not be coded in a single
Virtex-II Architecture
Virtex-II Architecture Block SelectRAM resource I/O Blocks (IOBs) edicated multipliers Programmable interconnect Configurable Logic Blocks (CLBs) Virtex -II architecture s core voltage operates at 1.5V
! Program logic functions, interconnect using SRAM. ! Advantages: ! Re-programmable; ! dynamically reconfigurable; ! uses standard processes.
Topics! SRAM-based FPGA fabrics:! Xilinx.! Altera. SRAM-based FPGAs! Program logic functions, using SRAM.! Advantages:! Re-programmable;! dynamically reconfigurable;! uses standard processes.! isadvantages:!
Chapter 8 FPGA Basics
Chapter 8 FPGA Basics NCHU EE Yin-Tsung Hwang YT Hwang VLSI SP 1 What are PLs? YT Hwang VLSI SP 2 Programmable Logic evices A pre-fabricated ASIC capable of performing any logic subject to user programming
CPE/EE 422/522. Introduction to Xilinx Virtex Field-Programmable Gate Arrays Devices. Dr. Rhonda Kay Gaede UAH. Outline
CPE/EE 422/522 Introduction to Xilinx Virtex Field-Programmable Gate Arrays Devices Dr. Rhonda Kay Gaede UAH Outline Introduction Field-Programmable Gate Arrays Virtex Virtex-E, Virtex-II, and Virtex-II
ECE 545 Lecture 12. FPGA Resources. George Mason University
ECE 545 Lecture 2 FPGA Resources George Mason University Recommended reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional Details 2 What is an FPGA? Configurable Logic Blocks
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 ROM (review) Memory device in which permanent binary information is stored. Example: 32 x 8 ROM Five input lines (2 5 = 32) 32 outputs, each representing a memory
FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
Basic FPGA Architectures. Actel FPGAs. PLD Technologies: Antifuse. 3 Digital Systems Implementation Programmable Logic Devices
3 Digital Systems Implementation Programmable Logic Devices Basic FPGA Architectures Why Programmable Logic Devices (PLDs)? Low cost, low risk way of implementing digital circuits as application specific
Field Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA) Lecturer: Krébesz, Tamas 1 FPGA in general Reprogrammable Si chip Invented in 1985 by Ross Freeman (Xilinx inc.) Combines the advantages of ASIC and uc-based systems
HDL Coding Style Xilinx, Inc. All Rights Reserved
HDL Coding Style Objective After completing this module, you will be able to: Select a proper coding style to create efficient FPGA designs Specify Xilinx resources that need to be instantiated for various
Hardware Design with VHDL Design Example: BRAM ECE 443
BRAM There are two sources of memory available on most FPGA boards. Internal (on-chip memory) External SRAMs and DRAMs. Internal memory is either distributed (from the LUTs) or block (dedicated on-chip
Topics. Midterm Finish Chapter 7
Lecture 9 Topics Midterm Finish Chapter 7 Xilinx FPGAs Chapter 7 Spartan 3E Architecture Source: Spartan-3E FPGA Family Datasheet CLB Configurable Logic Blocks Each CLB contains four slices Each slice
Lecture 7. Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits. Hardware Description Language)
Standard ICs FPGA (Field Programmable Gate Array) VHDL (Very-high-speed integrated circuits Hardware Description Language) 1 Standard ICs PLD: Programmable Logic Device CPLD: Complex PLD FPGA: Field Programmable
Field Programmable Gate Array
Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational
INTRODUCTION TO FPGA ARCHITECTURE
3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)
In our case Dr. Johnson is setting the best practices
VHDL Best Practices Best Practices??? Best practices are often defined by company, toolset or device In our case Dr. Johnson is setting the best practices These rules are for Class/Lab purposes. Industry
ECEU530. Project Presentations. ECE U530 Digital Hardware Synthesis. Rest of Semester. Memory Structures
ECEU53 ECE U53 igital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu November 5, 26 Lecture 8: Student project presentations Memories and FPGAs Tri-state buffers and busses Student project presentations:
ECE 645: Lecture 1. Basic Adders and Counters. Implementation of Adders in FPGAs
ECE 645: Lecture Basic Adders and Counters Implementation of Adders in FPGAs Required Reading Behrooz Parhami, Computer Arithmetic: Algorithms and Hardware Design Chapter 5, Basic Addition and Counting,
ECE 448 Lecture 5. FPGA Devices
E 448 Lecture 5 FPGA evices E 448 FPGA and ASIC esign with VHL George Mason University Required reading 7 Series FPGAs Configurable Logic Block: User Guide Overview Functional etails 2 What is an FPGA?
PROGRAMMABLE MODULES SPECIFICATION OF PROGRAMMABLE COMBINATIONAL AND SEQUENTIAL MODULES
PROGRAMMABLE MODULES SPECIFICATION OF PROGRAMMABLE COMBINATIONAL AND SEQUENTIAL MODULES. psa. rom. fpga THE WAY THE MODULES ARE PROGRAMMED NETWORKS OF PROGRAMMABLE MODULES EXAMPLES OF USES Programmable
Lecture 12 VHDL Synthesis
CPE 487: Digital System Design Spring 2018 Lecture 12 VHDL Synthesis Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030 1 What is Synthesis?
EE178 Lecture Module 2. Eric Crabill SJSU / Xilinx Fall 2007
EE178 Lecture Module 2 Eric Crabill SJSU / Xilinx Fall 2007 Lecture #4 Agenda Survey of implementation technologies. Implementation Technologies Small scale and medium scale integration. Up to about 200
Basic FPGA Architecture Xilinx, Inc. All Rights Reserved
Basic FPGA Architecture 2005 Xilinx, Inc. All Rights Reserved Objectives After completing this module, you will be able to: Identify the basic architectural resources of the Virtex -II FPGA List the differences
FPGAs in a Nutshell - Introduction to Embedded Systems-
FPGAs in a Nutshell - Introduction to Embedded Systems- Dipl.- Ing. Falk Salewski Lehrstuhl Informatik RWTH Aachen salewski@informatik.rwth-aachen.de Winter term 6/7 Contents History FPGA architecture
CDA 4253 FPGA System Design Op7miza7on Techniques. Hao Zheng Comp S ci & Eng Univ of South Florida
CDA 4253 FPGA System Design Op7miza7on Techniques Hao Zheng Comp S ci & Eng Univ of South Florida 1 Extracted from Advanced FPGA Design by Steve Kilts 2 Op7miza7on for Performance 3 Performance Defini7ons
Luleå University of Technology Kurskod SMD098 Datum Skrivtid
Luleå University of Technology Kurskod SMD098 Datum 2001-12-17 Skrivtid 14.00 18.00 Tentamen i Beräkningstrukturer Antal uppgifter: 6 Max poäng: 35 Lärare: Jonas Thor Telefon: 2549 Tillåtna hjälpmedel:
ECE 545 Lecture 17 RAM. George Mason University
ECE 545 Lecture 17 RAM George Mason University Recommended reading XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques [ UG687 (v 14.5) March 20, 2013 ] Sections:
Evolution of Implementation Technologies. ECE 4211/5211 Rapid Prototyping with FPGAs. Gate Array Technology (IBM s) Programmable Logic
ECE 42/52 Rapid Prototyping with FPGAs Dr. Charlie Wang Department of Electrical and Computer Engineering University of Colorado at Colorado Springs Evolution of Implementation Technologies Discrete devices:
ECE 699: Lecture 9. Programmable Logic Memories
ECE 699: Lecture 9 Programmable Logic Memories Recommended reading XST User Guide for Virtex-6, Spartan-6, and 7 Series Devices Chapter 7, HDL Coding Techniques Sections: RAM HDL Coding Techniques ROM
VHDL in 1h. Martin Schöberl
VHDL in 1h Martin Schöberl VHDL /= C, Java, Think in hardware All constructs run concurrent Different from software programming Forget the simulation explanation VHDL is complex We use only a small subset
Luleå University of Technology Kurskod SMD152 Datum Skrivtid
Luleå University of Technology Kurskod SMD152 Datum 2003-10-24 Skrivtid 9.00 13.00 1 Manual synthesis (10 p, 2 p each) Here you are given five different VHDL models. Your task is to draw the schematics
Lecture 3: Modeling in VHDL. EE 3610 Digital Systems
EE 3610: Digital Systems 1 Lecture 3: Modeling in VHDL VHDL: Overview 2 VHDL VHSIC Hardware Description Language VHSIC=Very High Speed Integrated Circuit Programming language for modelling of hardware
Lecture 11 Memories in Xilinx FPGAs
Lecture 11 Memories in Xilinx FPGAs ECE 448 FPGA and ASIC Design with VHDL Recommended reading XAPP463 Using Block RAM in Spartan-3 Generation FPGAs Google search: XAPP463 XAPP464 Using Look-Up Tables
FPGA architecture and design technology
CE 435 Embedded Systems Spring 2017 FPGA architecture and design technology Nikos Bellas Computer and Communications Engineering Department University of Thessaly 1 FPGA fabric A generic island-style FPGA
Altera FLEX 8000 Block Diagram
Altera FLEX 8000 Block Diagram Figure from Altera technical literature FLEX 8000 chip contains 26 162 LABs Each LAB contains 8 Logic Elements (LEs), so a chip contains 208 1296 LEs, totaling 2,500 16,000
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs)
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Fall 2002 EECS150 - Lec06-FPGA Page 1 Outline What are FPGAs? Why use FPGAs (a short history
Outline. EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) FPGA Overview. Why FPGAs?
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Outline What are FPGAs? Why use FPGAs (a short history lesson). FPGA variations Internal logic
DIGITAL LOGIC WITH VHDL (Fall 2013) Unit 1
DIGITAL LOGIC WITH VHDL (Fall 23) Unit DESIGN FLOW DATA TYPES LOGIC GATES WITH VHDL TESTBENCH GENERATION DESIGN FLOW Design Entry: We specify the logic circuit using a Hardware Description Language (e.g.,
Virtex-II Architecture. Virtex II technical, Design Solutions. Active Interconnect Technology (continued)
Virtex-II Architecture SONET / SDH Virtex II technical, Design Solutions PCI-X PCI DCM Distri RAM 18Kb BRAM Multiplier LVDS FIFO Shift Registers BLVDS SDRAM QDR SRAM Backplane Rev 4 March 4th. 2002 J-L
CS211 Digital Systems/Lab. Introduction to VHDL. Hyotaek Shim, Computer Architecture Laboratory
CS211 Digital Systems/Lab Introduction to VHDL Hyotaek Shim, Computer Architecture Laboratory Programmable Logic Device (PLD) 2/32 An electronic component used to build reconfigurable digital circuits
ECE 545: Lecture 11. Programmable Logic Memories
ECE 545: Lecture 11 Programmable Logic Memories Recommended reading Vivado Design Suite User Guide: Synthesis Chapter 4 RAM HDL Coding Techniques Initializing RAM Contents 7 Series FPGAs Memory Resources:
Timing in synchronous systems
BO 1 esign of sequential logic Outline Timing in synchronous networks Synchronous processes in VHL VHL-code that introduces latches andf flip-flops Initialization of registers Mealy- and Moore machines
ECE 545: Lecture 11. Programmable Logic Memories. Recommended reading. Memory Types. Memory Types. Memory Types specific to Xilinx FPGAs
ECE 545: Lecture 11 Programmable Logic Memories Recommended reading Vivado Design Suite User Guide: Synthesis Chapter 4 RAM HDL Coding Techniques Initializing RAM Contents 7 Series FPGAs Resources: User
EECS150 - Digital Design Lecture 16 Memory 1
EECS150 - Digital Design Lecture 16 Memory 1 March 13, 2003 John Wawrzynek Spring 2003 EECS150 - Lec16-mem1 Page 1 Memory Basics Uses: Whenever a large collection of state elements is required. data &
Digital System Construction
Digital System Construction FYSIKUM Lecture 4: More VHDL, memory, PRNG Arithmetic Memories Pipelines and buffers Pseudorandom numbers IP core generation in Vivado Introduction to Lab 3 Digital Systemkonstruktion
VHDL simulation and synthesis
VHDL simulation and synthesis How we treat VHDL in this course You will not become an expert in VHDL after taking this course The goal is that you should learn how VHDL can be used for simulation and synthesis
ECE 448 Lecture 5. FPGA Devices
ECE 448 Lecture 5 FPGA Devices George Mason University Required reading Spartan-6 FPGA Configurable Logic Block: User Guide CLB Overview Slice Description 2 Recommended reading Highly recommended for the
CprE 583 Reconfigurable Computing
Recap Moore FSM Example CprE / ComS 583 Reconfigurable Computing Moore FSM that recognizes sequence 10 0 1 0 1 S0 / 0 S1 / 0 1 S2 / 1 Prof. Joseph Zambreno Department of Electrical and Computer Engineering
Chapter 2. Cyclone II Architecture
Chapter 2. Cyclone II Architecture CII51002-1.0 Functional Description Cyclone II devices contain a two-dimensional row- and column-based architecture to implement custom logic. Column and row interconnects
ECE 545 Lecture 12. FPGA Embedded Resources 12/8/11. Resources. Recommended reading. Use of Embedded FPGA Resources in SHA-3 Candidates
ECE 545 Lecture 12 FPGA Embedded Resources Resources FPGA Embedded Resources web page available from the course web page George Mason University 2 Recommended reading XAPP463 Using Block RAM in Spartan-3
Pipelining & Verilog. Sequential Divider. Verilog divider.v. Math Functions in Coregen. Lab #3 due tonight, LPSet 8 Thurs 10/11
Lab #3 due tonight, LPSet 8 Thurs 0/ Pipelining & Verilog Latency & Throughput Pipelining to increase throughput Retiming Verilog Math Functions Debugging Hints Sequential Divider Assume the Divid (A)
FPGA. Logic Block. Plessey FPGA: basic building block here is 2-input NAND gate which is connected to each other to implement desired function.
FPGA Logic block of an FPGA can be configured in such a way that it can provide functionality as simple as that of transistor or as complex as that of a microprocessor. It can used to implement different
EECS150 - Digital Design Lecture 16 - Memory
EECS150 - Digital Design Lecture 16 - Memory October 17, 2002 John Wawrzynek Fall 2002 EECS150 - Lec16-mem1 Page 1 Memory Basics Uses: data & program storage general purpose registers buffering table lookups
Abi Farsoni, Department of Nuclear Engineering and Radiation Health Physics, Oregon State University
Hardware description language (HDL) Intended to describe circuits textually, for a computer to read Evolved starting in the 1970s and 1980s Popular languages today include: VHDL Defined in 1980s by U.S.
The Xilinx XC6200 chip, the software tools and the board development tools
The Xilinx XC6200 chip, the software tools and the board development tools What is an FPGA? Field Programmable Gate Array Fully programmable alternative to a customized chip Used to implement functions
Xilinx ASMBL Architecture
FPGA Structure Xilinx ASMBL Architecture Design Flow Synthesis: HDL to FPGA primitives Translate: FPGA Primitives to FPGA Slice components Map: Packing of Slice components into Slices, placement of Slices
CCE 3202 Advanced Digital System Design
CCE 3202 Advanced Digital System Design Lab Exercise #2 This lab exercise will show you how to create, synthesize, and test a 3-bit ripple counter. A ripple counter is simply a circuit that outputs the
Hardware Description Language VHDL (1) Introduction
Hardware Description Language VHDL (1) Introduction Digital Radiation Measurement and Spectroscopy NE/RHP 537 Introduction Hardware description language (HDL) Intended to describe circuits textually, for
Schedule. ECE U530 Digital Hardware Synthesis. Rest of Semester. Midterm Question 1a
ECE U530 Digital Hardware Synthesis Prof. Miriam Leeser mel@coe.neu.edu November 8, 2006 Midterm Average: 70 Lecture 16: Midterm Solutions Homework 6: Calculator Handshaking HW 6: Due Wednesday, November
Review: Timing. EECS Components and Design Techniques for Digital Systems. Lec 13 Storage: Regs, SRAM, ROM. Outline.
Review: Timing EECS 150 - Components and Design Techniques for Digital Systems Lec 13 Storage: Regs,, ROM David Culler Electrical Engineering and Computer Sciences University of California, Berkeley http://www.eecs.berkeley.edu/~culler
TSEA44 - Design for FPGAs
2015-11-24 Now for something else... Adapting designs to FPGAs Why? Clock frequency Area Power Target FPGA architecture: Xilinx FPGAs with 4 input LUTs (such as Virtex-II) Determining the maximum frequency
EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 15 Memories
EE 459/500 HDL Based Digital Design with Programmable Logic Lecture 15 Memories 1 Overview Introduction Memories Read Only Memories Random Access Memories FIFOs 2 1 Motivation Most applications need memory!
ELCT 501: Digital System Design
ELCT 501: Digital System Lecture 4: CAD tools (Continued) Dr. Mohamed Abd El Ghany, Basic VHDL Concept Via an Example Problem: write VHDL code for 1-bit adder 4-bit adder 2 1-bit adder Inputs: A (1 bit)
Assignment. Last time. Last time. ECE 4514 Digital Design II. Back to the big picture. Back to the big picture
Assignment Last time Project 4: Using synthesis tools Synplify Pro and Webpack Due 11/11 ning of class Generics Used to parameterize models E.g., Delay, bit width Configurations Configuration specification
ECE 545 Lecture 8. Data Flow Description of Combinational-Circuit Building Blocks. George Mason University
ECE 545 Lecture 8 Data Flow Description of Combinational-Circuit Building Blocks George Mason University Required reading P. Chu, RTL Hardware Design using VHDL Chapter 7, Combinational Circuit Design:
CMPT 250: Computer Architecture. Using LogicWorks 5. Tutorial Part 1. Somsubhra Sharangi
CMPT 250: Computer Architecture Using LogicWorks 5 Tutorial Part 1 Somsubhra Sharangi What is VHDL? A high level language to describe digital circuit Different that a programming language ( such as Java)
C-Based Hardware Design
LECTURE 6 In this lecture we will introduce: The VHDL Language and its benefits. The VHDL entity Concurrent and Sequential constructs Structural design. Hierarchy Packages Various architectures Examples
Digital Design Laboratory Lecture 2
ECE 280 / CSE 280 Digital Design Laboratory Lecture 2 Adder Design Basic building block is a full adder Chained together as a ripple carry adder Carry lookahead adder is an other option Propagate and generate
1 ST SUMMER SCHOOL: VHDL BOOTCAMP PISA, JULY 2013
MARIE CURIE IAPP: FAST TRACKER FOR HADRON COLLIDER EXPERIMENTS 1 ST SUMMER SCHOOL: VHDL BOOTCAMP PISA, JULY 2013 Introduction to VHDL Calliope-Louisa Sotiropoulou PhD Candidate/Researcher Aristotle University
FPGA Lecture for LUPO and GTO Vol , 31 August (revised 2013, 19 November) H. Baba
FPGA Lecture for LUPO and GTO Vol. 1 2010, 31 August (revised 2013, 19 November) H. Baba Contents Basic feature of FPGA Basic usage for LUPO New project Read and Write Basic behavioral VHDL simulation
Design Problem 3 Solutions
CSE 260 Digital Computers: Organization and Logical Design Jon Turner Design Problem 3 Solutions In this problem, you are to design, simulate and implement a sequential pattern spotter, using VHDL. This
CSE 260 Introduction to Digital Logic and Computer Design. Exam 1 Solutions
CSE 6 Introduction to igital Logic and Computer esign Exam Solutions Jonathan Turner /3/4. ( points) raw a logic diagram that implements the expression (B+C)(C +)(B+ ) directly (do not simplify first),
ECE 448 Lecture 4. Sequential-Circuit Building Blocks. Mixing Description Styles
ECE 448 Lecture 4 Sequential-Circuit Building Blocks Mixing Description Styles George Mason University Reading Required P. Chu, FPGA Prototyping by VHDL Examples Chapter 4, Regular Sequential Circuit Recommended
What is Xilinx Design Language?
Bill Jason P. Tomas University of Nevada Las Vegas Dept. of Electrical and Computer Engineering What is Xilinx Design Language? XDL is a human readable ASCII format compatible with the more widely used
EENG 2910 Project III: Digital System Design. Due: 04/30/2014. Team Members: University of North Texas Department of Electrical Engineering
EENG 2910 Project III: Digital System Design Due: 04/30/2014 Team Members: University of North Texas Department of Electrical Engineering Table of Content i Contents Abstract...3 Introduction...3 Report...4
Tutorial 4 HDL. Outline VHDL PROCESS. Modeling Combinational Logic. Structural Description Instantiation and Interconnection Hierarchy
CS3: Hardware Lab Tutorial 4 HDL Outline VHDL basic language concepts basic design methodology Examples A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati i i i3 i4 Modeling Combinational
CCE 3202 Advanced Digital System Design
CCE 3202 Advanced Digital System Design Lab Exercise #2 Introduction You will use Xilinx Webpack v9.1 to allow the synthesis and creation of VHDLbased designs. This lab will outline the steps necessary
COE 405, Term 062. Design & Modeling of Digital Systems. HW# 1 Solution. Due date: Wednesday, March. 14
COE 405, Term 062 Design & Modeling of Digital Systems HW# 1 Solution Due date: Wednesday, March. 14 Q.1. Consider the 4-bit carry-look-ahead adder (CLA) block shown below: A 3 -A 0 B 3 -B 0 C 3 4-bit
Verilog for High Performance
Verilog for High Performance Course Description This course provides all necessary theoretical and practical know-how to write synthesizable HDL code through Verilog standard language. The course goes
ENGG3380: Computer Organization and Design Lab4: Buses and Peripheral Devices
ENGG3380: Computer Organization and Design Lab4: Buses and Peripheral Devices School of Engineering, University of Guelph Winter 2017 1 Objectives: The purpose of this lab is : Learn basic bus design techniques.
A Dynamically Reconfigurable FPGA-based Content Addressable Memory for IP Characterization
Master Thesis ELE/ESK/2000-3 A Dynamically Reconfigurable FPGA-based Content Addressable Memory for IP Characterization Supervisors: Axel Jantsch Kjell Torkelsson Examinator: Axel Jantsch Master of Science
Sequential Statement
Sequential Statement Sequential Logic Output depends not only on current input values but also on previous input values. Are building blocks of; Counters Shift registers Memories Flip flops are basic sequential
Asynchronous FIFO Design
Asynchronous FIFO Design 2.1 Introduction: An Asynchronous FIFO Design refers to a FIFO Design where in the data values are written to the FIFO memory from one clock domain and the data values are read
Summary of FPGA & VHDL
FYS4220/9220 Summary of FPGA & VHDL Lecture #6 Jan Kenneth Bekkeng, University of Oslo - Department of Physics 16.11.2011 Curriculum (VHDL & FPGA part) Curriculum (Syllabus) defined by: Lectures Lecture6:
Sequential Logic - Module 5
Sequential Logic Module 5 Jim Duckworth, WPI 1 Latches and Flip-Flops Implemented by using signals in IF statements that are not completely specified Necessary latches or registers are inferred by the
CDA 4253 FGPA System Design Xilinx FPGA Memories. Hao Zheng Comp Sci & Eng USF
CDA 4253 FGPA System Design Xilinx FPGA Memories Hao Zheng Comp Sci & Eng USF Xilinx 7-Series FPGA Architecture On-Chip block RAM On-Chip block RAM Distributed RAM by Logic Fabric Distributed RAM by Logic
VHDL And Synthesis Review
VHDL And Synthesis Review VHDL In Detail Things that we will look at: Port and Types Arithmetic Operators Design styles for Synthesis VHDL Ports Four Different Types of Ports in: signal values are read-only
Digital Systems Design
Digital Systems Design Review of Combinatorial Circuit Building Blocks: VHDL for Combinational Circuits Dr. D. J. Jackson Lecture 2-1 Introduction to VHDL Designer writes a logic circuit description in
PINE TRAINING ACADEMY
PINE TRAINING ACADEMY Course Module A d d r e s s D - 5 5 7, G o v i n d p u r a m, G h a z i a b a d, U. P., 2 0 1 0 1 3, I n d i a Digital Logic System Design using Gates/Verilog or VHDL and Implementation
Outline of Presentation
Built-In Self-Test for Programmable I/O Buffers in FPGAs and SoCs Sudheer Vemula and Charles Stroud Electrical and Computer Engineering Auburn University presented at 2006 IEEE Southeastern Symp. On System
Virtex -E 1.8 V Field Programmable Gate Arrays
0 Virtex -E 1.8 V Field Programmable Gate Arrays DS022-2 (v2.6) November 19, 2002 0 0 Production Product Specification Architectural Description Virtex-E Array The Virtex-E user-programmable gate array,
The process. Sensitivity lists
The process process itself is a concurrent statement but the code inside the process is executed sequentially Process label (optional) Process declarative region Process body entity Test is, : in bit;
RUN-TIME RECONFIGURABLE IMPLEMENTATION OF DSP ALGORITHMS USING DISTRIBUTED ARITHMETIC. Zoltan Baruch
RUN-TIME RECONFIGURABLE IMPLEMENTATION OF DSP ALGORITHMS USING DISTRIBUTED ARITHMETIC Zoltan Baruch Computer Science Department, Technical University of Cluj-Napoca, 26-28, Bariţiu St., 3400 Cluj-Napoca,
Virtex -E 1.8 V Extended Memory Field Programmable Gate Arrays
0 Virtex -E 1.8 V Extended Memory Field Programmable Gate Arrays DS025-1 (v3.0) March 21, 2014 0 0 Production Product Specification Features Fast, Extended Block AM, 1.8 V FPGA Family - 560 Kb and 1,120
Programmable Logic Devices FPGA Architectures II CMPE 415. Overview This set of notes introduces many of the features available in the FPGAs of today.
Overview This set of notes introduces many of the features available in the FPGAs of today. The majority use SRAM based configuration cells, which allows fast reconfiguation. Allows new design ideas to
Architecture by Xilinx, Inc. All rights reserved.
Architecture 2002 by Xilinx, Inc. All rights reserved. Spartan-IIE Technical Details Table of Contents Spartan-IIE Overview Logic and Routing Embedded Memory System Clock Management Interfaces Select I/O
Two HDLs used today VHDL. Why VHDL? Introduction to Structured VLSI Design
Two HDLs used today Introduction to Structured VLSI Design VHDL I VHDL and Verilog Syntax and ``appearance'' of the two languages are very different Capabilities and scopes are quite similar Both are industrial
Introduction to VHDL #3
ECE 322 Digital Design with VHDL Introduction to VHDL #3 Lecture 7 & 8 VHDL Modeling Styles VHDL Modeling Styles Dataflow Concurrent statements Structural Components and interconnects Behavioral (sequential)