תכן חומרה בשפת VERILOG הפקולטה להנדסה

Transcription

1 תכן חומרה בשפת VERILOG סמסטר ב' תשע"ג משה דורון מרצה: מתרגלים: אריאל בורג, חג'ג' חן הפקולטה להנדסה 1

2 Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling Lecture 6 - Data flow modeling Lecture 7 - Gate Level modeling Lecture 8 - Tasks and Functions Lecture 9 - Advanced Modeling Techniques Lecture 10 - System Tasks and Compiler directives Lecture 11 - Switch Level modeling Lecture 12 - Coding Styles and Test Benches Lecture 13 - Synthesis issues 2

3 3 Lecture 1 - Introduction Course Objectives Evolution of CAD What is HDL What is Verilog Verilog History Design Advantages Language Capabilities Levels of Abstraction Design Flow Design Methodologies Basic Unit module Structural Hierarchy Description Style Module Ports Module Instantiation Exercise 1

4 Course Objectives Gain thorough understanding of the essential concepts and capabilities of Verilog HW Description Language Gain practical experience in writing Verilog code for Hardware Systems Design, Verification and Synthesis Participants will be able to approach their Verilogbased Digital Design Projects with confidence 4

5 Evolution of EDA Over 30 years, Integrated Circuits (ICs) scaled up in complexity from hundreds gates to millions gates Electronic Design Automation (EDA) techniques evolved, enabling Chip Designers to cope with the ever increasing design complexity Today, EDA support HW Design Languages, Behavioral Simulation, Functional Verification, Synthesis to Gate- Level Netlist and Automatic ICs Placement and Routing During last 4 years, the hot trend is High Level Synthesis 5

6 What is Hardware Description Language (HDL) A convenient, powerful, Device-independent representation of Digital Logic (Behavior and Structure) Boosts Design Methodology: Functionality can be verified early in the design process. Simulation at a higher level, enable architectural evaluation and decisions. Coupling HDL Compiler with Logic Synthesis tools, automatically converts a Technology-independent HDL Design description and Functionality to a Gate-Level implementation, in different target Technologies. 6

7 7 What is Verilog One of the two major HDLs used by Hardware Designers in Industry and Academia. Ada-like VHDL is the other one Advantages: C- based Syntax, easy to master and use Condensed and efficient code Intensively used by Israeli Hi-Tech Industry Disadvantage: Poor constructs self-checking

8 Verilog History 1985: Introduced as Hardware modeling language by Gateway Design System 1990: Cadence acquired Gateway and became the language owner 1995: Verilog became an IEEE Standard 1364 Verilog 2001 fixed lot of Verilog 1995 problems 8

9 9 Verilog Design Advantages Single Language for Design & Simulation Increased ability to work with massive HW design HW documentation, Design reuse Verilog Simulator Tools allow you to perform the following tasks in the design process without building a Hardware Prototype: - Determine the feasibility of new design ideas - Try more than one approach to a design problem - Verify Functionality - Identify Design Problems

10 Language Capabilities Design can be described in a wide range of levels: Switch, Gate, Register Transfer Level (RTL), Algorithmic Design can be modeled in a mixed style Behavioral, Dataflow and Structural At the Behavioral level, Design can be described in RTL, Architecture and Algorithmic levels Hierarchical design can be described, up to any level, using the module instantiation construct A design can be of arbitrary size. No limit imposed 10

11 Language Capabilities (2) Two data types: net (wire) & variable (reg - abstract data storage element) Primitive Logic Gates and Switch-Level Gates, are built-in Language used for Test Bench - Stimuli & Monitor results Flexibility of creating a Combinational or Sequential, User Defined Primitive (UDP) Programming Language Interface (PLI), allow foreign functions access Verilog module info enables Designer s interaction with the Simulator 11

12 12 Levels of Abstraction Verilog is a High-level Language, having constructs supporting various Design s Abstraction Levels: (Top-to-Bottom) Behavioral - A module is implemented in terms of desired algorithm, without knowing the HW implementation details. Data Flow- A module is designed by specifying the data flow between registers and how data is a processed. (RTL) Gate Level- A module is implemented in terms of logic gates and the interconnections between them. Switch Level- A module is implemented in terms of switches (transistors), storage nodes, resistors and the interconnections between them.

13 Design Flow using Verilog Specification Architecture Design Coding in Verilog Simulation & Verification Compilation Function/Performance Definition Structure and Function (Behavior) of the Design Efficient, well-documented coding Design Behave as Required? Timing: Waveform Behavior HDL description into Netlist 13 Synthesis Mapping Logic Optimization Mapping Verified Design to target HW - FPGA or ASIC

14 14 Design Methodologies

15 Basic Unit The Module Verilog describes a digital system as a set of modules Element or a collection of lower level design blocks A module can be instantiated in another module Each module has an interface and contents description Modules communicate externally with input, output and bi-directional ports 15

16 16 Module Structure module module_name (port_list) ; declarations: port declaration (input, output, inout, ) data type declaration (reg, wire, parameter, ) task and function declaration statements: initial block always block Behavioral module instantiation gate instantiation Structural UDP instantiation continuous assignment Data-flow endmodule

17 Example - AND module (data flow & behavioral) module AND (out, in1, in2) ; // <module name> <ports list> input in1, in2 ; output wire out ; assign out = in1 & in2 ; // data flow - continuous Assignment endmodule in1 out in2 module AND (out, in1, in2) ; // <module name> <ports list> input in1, in2 ; output reg out ; // must be reg type when used as LHS in an always block in1 or in2) // always block (sensitivity list) - behavioral out = in1 & in2 ; /* statements inside always block are executed only when one or more signals in the list changes value */ endmodule 17

18 Example - NAND (gate level) module a b nand q module Nand (q, a, b) ; // <module name> <ports list> output q ; input a, b ; endmodule nand (q, a, b) ; // Language gate primitive 18

19 Example D_FF (behavioral) module module D_FF(clk, nrst, d, q) ; input clk, nrst, d ; output reg q ; clk or negedge nrst) if (!nrst) q <= 0 ; else q <= d ; endmodule 19 d q clk nrst // Event-based Timing Control // reset state // normal operation

20 Structural Hierarchy Description Style Direct instantiation and connections of modules from a separate calling module - From the structural hierarchy of the design A module may be declared anywhere in a design relative to where it is called Signals in the higher calling module, are connected to signals in the lower called module by either: - Named association - Positional association 20

21 Module interconnections: Ports Within a Verilog system model, module interconnections occur at two levels: Peer to peer: modules interconnect with each other: Module A Module B Hierarchical: one module incorporates the other: Module A Module B 21

22 22 Module Ports Ports provide interface for the module to communicate with its environment. Declaration: <Port direction> <width> <port_name> ; Port direction can be input, output or inout. Example: module my_module (my_input_port, my_inout_port, my_output_port ) ; input [4:0] my_input_port ; inout my_inout_port ; output wire (or reg) [14:0] my_output_port ; endmodule

23 Port Specifications An input port specifies an internal name for a vector or scalar, driven by external entity. An output port specifies an internal name for a vector or scalar, driven by internal entity, available external to the module. An inout port specifies an internal name for a vector or scalar driven either by an internal or external entity. bi-directional Input or inout port cannot be declared as of type register. Port is always considered as net, unless declared elsewhere as reg (only for output port) 23

24 Correct Port Connection net net inout reg or net net input reg or net output net module 24

25 25 Module Instantiation - Port connections Ports of the instances could be connected by name or by order list. For small # of ports, connect by order list, else, by name. module fa_tb ; module FA4 (sum, cout, a, b, cin) ; reg [3:0] A, B ; output wire [3:0] sum ; reg CIN ; output wire cout ; wire [3:0] SUM ; input [3:0] a, b ; wire COUT ; input cin ; endmodule endmodule // Instantiate/connect by Positional association (order list): FA4 fa_byorder (SUM, COUT, A, B, CIN) ; // Instantiate/connect by Named association (port name): FA4 fa_byname (cout(cout),.sum(sum),.b(b),.cin(cin),.a(a) ;

26 Test Bench and UUT Instantiation Module Test Bench incorporates, hierarchically, the Unit Under Test (UUT) module Stimuli Unit Under Test Monitor registers inputs wires outputs wires, regs wires 26

27 27 D_FF Test Bench `include D_FF.v" // include the UUT Verilog file for simulator parsing `timescale 1ns / 100ps /* compiler directive. sets simulation s time unit and precision */ module D_FF_tb () ; reg Clk, Nrst, D ; // Stimuli signals wire Q ; // Monitor signal D_FF UUT(Clk, Nrst, D, Q) ; // instantiation of the D_FF (UUT) initial begin Clk = 1'b0; Nrst = 1'b0, D = 1'b0 ; // System monitoring function $monitor($time,"clk=%b,nrst=%b,d=%b;q=%b",clk,nrst,d,q) ; end always #1 Clk = ~Clk ; // Clock declaration initial begin #2 Nrst = 1'b1 ; // Out of reset #2 D = 1'b1 ; #2 $finish ; // System function - end simulation run end endmodule

28 General Info תרגולי מעבדה מקומות ישיבה קבועים במעבדה השתתפות חובה ב- 10 מתוך 13 תרגולי מעבדה ציון ציון הקורס ייקבע ע"י ממוצע מיטב ביצועי 10 מעבדות ספרים בספריה Verilog HDL: A Guide to Digital Design and Synthesis Design Through Verilog HDL A Verilog HDL Primer Digital VLSI Design with Verilog ספרות 28

29 29 Exercise 1 4bit Counter 4bit Binary Counter cntr_4b.v Test Bench for the Counter cntr_4b_tb.v Synchronous or Asynchronous Reset Up/Down Counter Decimal Counter - Counts from 0 to 9 Programmable Divider - Preloaded Counter Notes: - Use Notepad++ to write the Verilog code - Use Cadence Incisive Unified Simulator (IUS)