1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4]

Transcription

1 HW 3 Answer Key 1. Prove that if you have tri-state buffers and inverters, you can build any combinational logic circuit. [4] You can build a NAND gate from tri-state buffers and inverters and thus you can build any combinational logic circuit since NAND is logically complete. Proof: We know, from class, that the set of AND, OR & NOT are logically complete. By DeMorgan s Law, we can construct OR from AND & NOT. Thus, the set of AND & NOT is logically complete. It follows that NAND is also logically complete. Other methods could have been building a NOR, AND & NOT, OR & NOT or something else that s logically complete. 2. If a 4-bit ripple-carry adder has a worst-case delay of 8ns, what would you expect would be the worst-case delay of a 32-bit ripple-carry adder? Justify your answer. [1] 4-bit ripple-carry adder is composed of 4 1-bit full adders chained together. If we assume each full adder has a worst-case delay of 2ns, where the 2ns delay is the time from when inputs propagate to the carry-out, then a 32-bit ripple carry adder would have a worstcase delay of 64ns.

2 3. Design a 6-bit unsigned comparator using gates and combinational logic. The device should have two 4-bit inputs (A[3:0] and B[3:0]) and two outputs, one called "equal" (which should be a 1 if A=B) and one called "lt" (which should be a 1 if A is less than B). Hint: You will likely want to build a "one-bit" comparitor in a way similar to a full-adder and chain them (much like a ripple-carry adder).[5] A B A=B A<B For a 1-bit less-than-or-equal comparator, we have the truth table to the left. We can note that an XNOR and AND gate ORed together gives the exact same truth table A B A B!A*B A B+!A*B Checking for equality is simply checking that each bit is equal on a bitwise level and ANDing the results of each bit. If all bits match, then we have equality. If at least one doesn t, then we don t have equality. Checking for less-than is a bit trickier. When comparing less-than on a bitwise level, if one bit is less than, such as A[5:0] = and B[5:0] = , then we already known that we have less-than by looking at the most significant bit and we don t need to check the other bits. However, less-than is not just a simple OR of all the bitwise lessthins since individual bits could be less than. What we notice is that as we traverse the bitwise comparisons starting from most significant, we only continue to do less-than comparisons if the preceding bits are equal. That is, if A[5] and B[5] are the equal, then we want to check for less-than on bits A[4] and B[4] and so on. One bit comparitor

3 4. Design a circuit which takes in a 4-digit two's complement number (A[3:0]) and outputs a value B[3:0] which is exactly half the value of A, rounding up. You can use one adder (any size) and standard gates. [3] We notice that in binary, shifting the bits right is the same as an Integer divide-by-two (though we need to sign extend). This means that even numbers will divide without any remainder and thus do not need rounding. This is true for positive and negative numbers. For odd numbers, an integer divide-by-two leaves a remainder. We notice that odd numbers have a 1 as the least significant bit so we can use that as input to our adder to round the shifted result up. This is true for positive and negative numbers. This is one possible solution. One could have also put A0 into Ci, instead. You could also have added before shifting, but this would require handling of special cases such as 7.

4 5. Define the terms "setup time" and "hold time". Your answer should include a picture. [2] Setup time: the time a flip-flop s input must be stable before the clock edge arrives Hold time: the time a flip-flop s inputs must stay stable after the clock edge arrives

5 [2] [2] [2] A D latch s output echoes the input D when C is 1, and holds its previous value when C is 0. A D flip-flop s outputs the input D on the rising edge of C and holds that value otherwise.

6 9. Design a state transition diagram for a state machine which has one input, x, and one output z. z should go high if the last four values of x were either 1001 or (You likely won't be able to do this problem until after the lecture on 1/30)[5] [2] unk unk unk unk unk ace [1] a. 2 bits c. 4 bits e. 10 bits