VHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY. Design descriptions & design constructions examples are taken from foundation series examples

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1 1 VHDL 3 BASIC OPERATORS AND ARCHITECTURE BODY Design descriptions & design constructions examples are taken from foundation series examples

2 2 What we have done in Lab 1 entity AND_Gate is port ( a : in STD_LOGIC; b : in STD_LOGIC; F : out STD_LOGIC); end AND_Gate; architecture AND_arch of AND_Gate is begin F <= a and b; end AND_arch; Hardware Simulation architecture Behavioral of AND_TEST is component AND_Gate port(a, b: in STD_LOGIC; F: out STD_LOGIC); end component; signal ai, bi: STD_LOGIC; signal Fi: STD_LOGIC; begin AND_Gate port map (a => ai, b => bi, F => Fi); process begin ai <= '0'; bi <= '0'; wait for 100 ns; ai <= '1'; bi <= '0'; wait for 100 ns; ai <= '0'; bi <= '1'; wait for 100 ns; ai <= '1'; bi <= '1'; wait; end process; end Behavioral;

3 3 We will learn VHDL operators Different architecture design methods 1) Structural 2) Data flow 3) Behavioral Design constructions Use of signals and variables

4 4 VHDL OPERATORS And their usage

5 5 Typical Operators Logical / Relation e.g and,= VHDL Operators Basic e.g., +,-,&, Abs,** Shift e.g. SLR

6 6 Logical / relation operators Logical operators: and, or, nand, nor, xor, xnor, not have their usual meanings. nand is not associative (A nand B) nand C A nand (B nand C) (Exercise 3.1) A nand B nand C is illegal Relation operators (result is Boolean) = equal /= not equal < less than <= less than or equal > greater than >= greater than or equal

7 7 Student ID: Name: Date: (Submit this at the end of the lecture.) Exercise 3.1 Fill in? to show that NAND-gate is not associative A B C A nand B (A nand B) nand C B nand C A nand (B nand C) ? ? ? ? 1

8 9 Shift operators Logical shift and rotate sll shift left logical, fill blank with 0 srl shift right logical, fill blank with 0 rol rotate left logical, circular operation E.g rol 3 is ror rotate right logical, circular operation Arithmetic shift sla shift left arithmetic, fill blank with 0, same as sll sra shift right arithmetic, fill blank with sign bit (MSB)

9 10 Exercise 3.2 On shift and rotate A <= ; A sll 2 = A srl 3 = A sla 3 = A sra 2 = A rol 3 = A ror 5 =

10 12 Basic operators + - * / arithmetic add, for integer, float. arithmetic subtract, for integer, float. multiplication division rem remainder mod modulo (e.g. A mod B = A - (B*N), N is an integer) abs absolute value ** exponentiation (e.g., 2**3 is 8) & concatenation (e.g., 0 & 1 is 01 )

11 13 ARCHITECTURE BODY 3 types of design description Design description 1. Structural (parallel) Use port map 2. Data Flow (parallel) Use concurrent statements 3. Behavioral (serial) Use process

12 14 (1) Structural design description method {Using port map} Design description 1. Structural (parallel) Use port map 2. Data Flow (parallel) Use concurrent statements 3. Behavioral (serial) Use process

13 15 Structural design Like a circuit but describe it by text Component A Related by port map in architecture Component B Component C

14 16 Structural design steps Step 1: Create entities Step 2: Create components from entities Step 3: Create port map to relate the components

15 17 1) library IEEE; 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity and2 is 4) port (a,b: in STD_LOGIC; 5) c: out STD_LOGIC ); 6) end and2; 7) architecture and2_arch of and2 is 8) begin 9) c <= a and b; 10) end and2_arch; 11) ) library IEEE; 13) use IEEE.STD_LOGIC_1164.ALL; 14) entity or2 is 15) port (a,b: in STD_LOGIC; 16) c: out STD_LOGIC ); 17) end or2; 18) architecture or2_arch of or2 is 19) begin 20) c <= a or b; 21) end or2_arch; A working example a) library IEEE; b) use IEEE.STD_LOGIC_1164.ALL; c) d) entity test is e) port ( in1: in STD_LOGIC; in2: in STD_LOGIC; f) in3: in STD_LOGIC; g) out1: out STD_LOGIC ); h) end test; i) architecture test_arch of test is j) component and2 --create component k) port (a,b: in std_logic; c: out std_logic); l) end component ; m) component or2 --create component n) port (a,b: in std_logic; c: out std_logic); o) end component ; p) signal con1_signal: std_logic; q) begin r) label1: and2 port map (in1, in2, con1_signal); s) label2: or2 port map (con1_signal, in3, out1); t) end test_arch;

16 18 1) library IEEE; 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity and2 is 4) port (a,b: in STD_LOGIC; 5) c: out STD_LOGIC ); 6) end and2; 7) architecture and2_arch of and2 is 8) begin 9) c <= a and b; 10) end and2_arch; 11) ) library IEEE; 13) use IEEE.STD_LOGIC_1164.ALL; 14) entity or2 is 15) port (a,b: in STD_LOGIC; 16) c: out STD_LOGIC ); 17) end or2; 18) architecture or2_arch of or2 is 19) begin 20) c <= a or b; 21) end or2_arch; Step1 of Structural Description Create entities a b a b AND OR c c

17 19 Step 2 : Create components from entities j) component and2 --create components-- k) port (a,b: in std_logic; c: out std_logic); l) end component ; m) component or2 n) port (a,b: in std_logic; c: out std_logic); o) end component ; p) signal con1_signal: std_logic; a = input b = input e.g., component and2 intermediate signal (optional) c = output

18 20 Step 3 : Connect components using port map q) begin lines can be interchanged! r) label1: and2 port map (in1, in2, con1_signal); s) label2: or2 port map (con1_signal, in3, out1); t) end test_arch; label1, label2: line labels port map: reserved word in1 in2 in3 con1_signal out1 It is still this circuit even the two lines are interchanged!

19 21 1) library IEEE; 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity and2 is 4) port (a,b: in STD_LOGIC; 5) c: out STD_LOGIC ); 6) end and2; 7) architecture and2_arch of and2 is 8) begin 9) c <= a and b; 10) end and2_arch; 11) ) library IEEE; 13) use IEEE.STD_LOGIC_1164.ALL; 14) entity or2 is 15) port (a,b: in STD_LOGIC; 16) c: out STD_LOGIC ); 17) end or2; 18) architecture or2_arch of or2 is 19) begin 20) c <= a or b; 21) end or2_arch; Step 1 Step 1 Review: A working example a) library IEEE; b) use IEEE.STD_LOGIC_1164.ALL; c) d) entity test is e) port ( in1: in STD_LOGIC; in2: in STD_LOGIC; f) in3: in STD_LOGIC; g) out1: out STD_LOGIC ); h) end test; i) architecture test_arch of test is j) component and2 --create component k) port (a,b: in std_logic; c: out std_logic); l) end component ; m) component or2 --create component n) port (a,b: in std_logic; c: out std_logic); o) end component ; p) signal con1_signal: std_logic; q) begin r) label1: and2 port map (in1, in2, con1_signal); s) label2: or2 port map (con1_signal, in3, out1); t) end test_arch; Step 2 Step 3

20 22 Exercise 3.3 (a) Draw the schematic diagram if a VHDL program has lines (i) label_u0:and2 port map (a, c, x); (ii) label_u1:or2 port map (b, x, y); (b) When will lines (i) and (ii) be executed? Answer: (c) Complete lines (i) and (ii) if the circuit is (i) label_u0:? (ii) label_u1:? a b c x y

21 24 Another working example entity test_andand2 is port ( in1: in STD_LOGIC; in2: in STD_LOGIC; in3: in STD_LOGIC; out1: out STD_LOGIC ); end test_andand2; architecture test_andand2_arch of test_andand2 is component and2 port (a, b: in std_logic; c: out std_logic); end component ; signal con1_signal: std_logic; begin label1: and2 port map (in1, in2, con1_signal); label2: and2 port map (con1_signal, in3, out1); end test_andand2_arch; No need to create the component for the same entity for several times in1 in2 in3 But you can use the component multiple times con1_signal out1

22 25 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and2 is port (a,b: in STD_LOGIC; c: out STD_LOGIC ); end and2; architecture and2_arch of and2 is begin c <= a and b; end and2_arch; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity xor2 is port (a,b: in STD_LOGIC; c: out STD_LOGIC ); end xor2; architecture xor2_arch of xor2 is begin c <= a xor b; end xor2_arch; Half Adder library IEEE; --Vivado 14.4 ok use IEEE.STD_LOGIC_1164.ALL; entity half_adder is -- another example port ( x: in bit; y: in bit; sum: out bit; carry: out bit ); end half_adder; architecture half_adder_arch of half_adder is component xor2 port(a,b: in bit; c: out bit); end component; component and2 port( a,b: in bit; c: out bit); end component; begin label1: xor2 port map (x, y, sum); label2: and2 port map (x, y, carry); end half_adder_arch;

23 26 Exercise 3.4 Draw the schematic diagram of the half-adder library IEEE; --Vivado 14.4 ok use IEEE.STD_LOGIC_1164.ALL; entity half_adder is -- another example port ( x: in bit; y: in bit; sum: out bit; carry: out bit ); end half_adder; architecture half_adder_arch of half_adder is component xor2 port(a,b: in bit; c: out bit); end component; component and2 port( a,b: in bit; c: out bit); end component; begin label1: xor2 port map (x, y, sum); label2: and2 port map (x, y, carry); end half_adder_arch;

24 28 (2) Data flow description method {Using concurrent statements} Design description 1. Structural (parallel) Use port map 2. Data Flow (parallel) Use concurrent statements 3. Behavioral (serial) Use process

25 29 Data flow: concurrent execution (no need to use port map ) 1) library IEEE; %Vivado tested ok 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity eqb_comp4 is 4) port (a, b: in std_logic_vector(3 downto 0); 5) equals, bigger: out std_logic); 6) end eqb_comp4; 7) architecture dataflow4 of eqb_comp4 is 8) begin 9) equals <= '1' when (a = b) else '0';--concurrent 10) bigger <='1' when (a > b) else '0';--concurrent 11) end dataflow4;

26 30 Exercise 3.5 Exercise based on entity eqb_comp4 1 entity eqb_comp4 is 2 port (a, b: in std_logic_vector(3 downto 0); 3 equals,bigger: out std_logic); 4 end eqb_comp4; 5 architecture dataflow4 of eqb_comp4 is 6 begin 7 equals <= '1' when (a = b) else '0 ';--concurrent 8 bigger <= 1 when (a > b) else 0 ;--concurrent 9 end dataflow4; When will lines 7, 8 be executed? Answer:

27 32 Exercise 3.6 Draw the schematic of this code 1) library IEEE; --Vivado ) use IEEE.STD_LOGIC_1164.ALL; 3) entity abc is 4) port (a, b,c: in std_logic; 5) y: out std_logic); 6) end abc; 7) architecture abc_arch of abc is 8) signal x : std_logic; 9) begin 10) x <= a nor b; 11) y <= x and c; 12) end abc_arch;

28 34 Structural vs. Data flow Structural (port map) architecture test_arch of test is component and2 port (a,b: in std_logic; c: out std_logic); end component ; component nor2 port (a,b: in std_logic; c: out std_logic); end component ; signal x: std_logic; begin label1: nor2 port map (a, b, x); label2: and2 port map (x, c, y); end test_arch; Data flow (concurrent) architecture test_arch of test is signal x : std_logic; begin x <= a nor b; y <= x and c; end test_arch; a b c x y

29 35 (3) Behavioral design description method {Using process( ) } Design description 1. Structural (parallel) Use port map 2. Data Flow (parallel) Use concurrent statements 3. Behavioral (serial) Use process

30 36 Behavioral design Behavioral design is sequential Just like a sequential program The keyword is process Sequential inside a process The main character is process (sensitivity list)

31 37 library IEEE; --vivado14.4 use IEEE.STD_LOGIC_1164.ALL; entity eqcomp4 is port( port (a, b: in std_logic;_vector(3 downto 0) equals: out std_logic); end eqcomp4; architecture behavioral of eqcomp4 is begin comp: process (a, b) begin if a = b then equals <= '1'; else equals <= '0'; end if; end process; end behavioral; Behavioral design: Sequential! Keyword is process! Sequential execution: Just like a sequential software program!

32 38 Exercise 3.7 (a) When will the line 9), the process( ), be executed? Answer: (b) When will lines after process ( ) begin be executed? Answer: 1) library IEEE; --vivado14.4 ok 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity eqcomp4 is port( 4) a,b: in std_logic_vector(3 downto 0); 5) equals: out std_logic); 6) end eqcomp4; 7) architecture behavioral of eqcomp4 is 8) begin 9) comp: process (a, b) 10) begin 11) if a = b then 12) equals <= '1'; 13) else 14) equals <= '0'; 15) end if; 16) end process; 17) end behavioral;

33 40 Concurrent vs. Sequential Concurrent Every statement inside the architecture body is executed concurrently, except statements enclosed by a process. Sequential Statements within a process are executed sequentially, and result is obtained when the whole process is complete. process(sensitivity list): when one or more signals in the sensitivity list change state, the process executes once. You may treat a process as one concurrent statement in the architecture body.

34 41 Concurrent with Sequential 1) library IEEE; --vivado14.4 ok 2) use IEEE.STD_LOGIC_1164.ALL; in1 3) entity conc_ex is in2 4) port (in1, in2,in3: in std_logic; in3 5) out1,out2 : inout std_logic); 6) end conc_ex; 7) architecture for_ex_arch of conc_ex is 8) begin 9) process (in1, in2) 10) begin 11) out1 <= in1 and in2; 12) end process; 13) out2 <= out1 and in3; -- concurrent statement 14) end for_ex_arch; out1 out2 The process (9-12) and line 13 are concurrent!

35 42 DESIGN CONSTRUCTIONS Design constructions Concurrent Sequential stand-alone statements live (no process) in process( ) when else with select when case when for in to loop if then else

36 43 Design constructions Concurrent: statements that can be stand-alone when-else with-select-when Concurrent NO process Sequential: statements that can only live inside the process case-when for-in-to-loop if-then-else Sequential WITH process

37 44 Concurrent Statements that can stand-alone (Concurrent 1) when-else (Concurrent 2) with-select-when

38 45 (Concurrent 1) when-else: 1) library IEEE; --vivado14.4 ok 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity when_ex is 4) port (in1, in2 : in std_logic; 5) out1 : out std_logic); 6) end when_ex; 7) architecture when_ex_a of when_ex is 8) begin 9) out1 <= '1' when in1 = '1' and in2 = '1' else '0'; 10) end when_ex_a; in1 in2 and-gate out

39 46 Exercise 3.8: Fill in the blank in line 8 using when else 1 entity when_ex is 2 port (in1, in2 : in std_logic; 3 4 end when_ex; 5 -- out1 : out std_logic); 6 architecture when_ex_a of when_ex is 7 begin 8? 9 end when_ex_a; in1 in2 out

40 48 (Concurrent 2) with-select-when: 1) library IEEE; --vivado14.4 ok 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity with_ex is 4) port (in1, in2 : in std_logic; 5) out1 : out std_logic); 6) end with_ex; 7) ) architecture with_ex_a of with_ex is 9) begin 10) with in1 select 11) out1 <= in2 when '1', --means when in1='1' then out1 <= in2 12) 0 when others; --means other cases then out1 <='0' 13) end with_ex_a; in1 in2 and-gate out

41 49 when-else vs. with-select-when (Concurrent 1) when-else: Condition based construction out1 <= '1' when in1 = '1' and in2 = '1' else '0'; (Concurrent 2) with-select-when: Signal based construction with in1 select out1 <= in2 when '1', --means when in1='1' then out1 <= in2 0 when others; --means other cases then out1 <='0' in1 in2 and-gate out1

42 50 Sequential (within a process) Statements that can only live inside processes (Sequential 1) case-when (Sequential 2) for-in-to-loop (Sequential 3) if-then-else

43 1) library IEEE; --tested ise, vivado14.4 ok 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity test_case is 4) port ( in1, in2: in std_logic; 5) out1,out2 : out std_logic); 6) end test_case; 7) architecture case_arch of test_case is 8) signal b : std_logic_vector (1 downto 0); 9) begin 10) process (b) 11) begin case b is Means implies 12) when "00" "11" => out1 <= '0'; 13) out2 <= '1'; 14) when others => out1 <= '1'; 15) out2 <= '0'; 16) end case; 17) end process; means 18) b <= in1 & in2; case 00 or 11 19) end case_arch; Exercise 3.9 (Sequential 1) case-when a) List the line numbers of the concurrent lines. Answer: b) List the line numbers of the sequential lines. Answer: c) Fill in the truth table b(1) b(0) Out1 Out2 0 0?? 0 1?? 1 0?? 1 1?? 51

44 53 Things about case-when: 1) => means implies not bigger. 2) All cases must be present Remember to use others to complete all cases!

45 54 when-else, with-select-when, case-when (Concurrent 1) when-else b <= "1000" when a = "00" else "0100" when a = "01" else "0010" when a = "10" else "0001" when a = "11"; (Concurrent 2) with-select-when with a select b <= "1000" when "00", "0100" when "01", "0010" when "10", "0001" when "11"; (Sequential 1) case-when process(a) begin case a is when "00" => b <= "1000"; when "01" => b <= "0100"; when "10" => b <= "0010"; when "11" => b <= "0001"; when others => null; end case; end process;

46 55 (Sequential 2) for-in-to-loop 1) library IEEE; --%ISE tested ok, vivado 14.4 ok 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity for_ex is 4) port (in1: in std_logic_vector(3 downto 0); 5) out1: out std_logic_vector(3 downto 0)); 6) end for_ex; 7) architecture for_ex_arch of for_ex is 8) begin 9) process (in1) 10) begin 11) label_for: for i in 0 to 3 loop 12) out1 (i) <= not in1(i); 13) end loop; 14) end process; 15) end for_ex_arch; in(3:0) out(3:0)

47 56 Exercise 3.10 Rewrite arch1 without a process( ) 1 architecture arch1 of ex1 is 2 begin 3 process (in1) 4 begin lab0 : for i in 0 to 3 loop out1 (i) <= not in1(i); end loop; end process; 9 end for_ex_arch; 1 architecture arch1 of ex1 is 2 begin end for_ex_arch;

48 58 (Sequential 3) if-then-else 1) library IEEE; --%ISE tested ok 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity if_ex is 4) port (in1,in2: in std_logic; 5) out1: out std_logic); 6) end if_ex; 7) architecture if_ex_a of if_ex is 8) begin 9) process (in1, in2) 10) begin 11) if in1 = '1' and in2 = '1' then 12) out1 <= '1'; 13) else 14) out1 <= '0'; 15) end if; 16) end process; 17) end if_ex_a; in1 in2 and-gate out

49 59 Use of signals and variables Signals (global) Variable (live inside processes only) We will learn more about this in Finite state machines design

50 60 Signal assignment <= Global, concurrent execution <= signal assignment Do not confused with the relation operator <= equal or smaller A1 <= B1 or C1 A1 signal must be declared outside a process, It is a signal representing an internal wire or an in/out/buffer signal in port. B1 C1 A1

51 61 Variable assignment := Local, sequential execution := variable assignment Variables can only be declared and used in the sequential part (inside process) of VHDL Local to a process. A2 := B2 and C2 Similar to signal assignment but A2 must be a variable.

52 62 Quick revision You should know Operators and usage Architecture design methods 1) Structural (port map) 2) Data flow (concurrent statements) 3) Behavioral (process) Use of signals and variables Signals assignment use <=, can be used in concurrent and sequential statements Variable assignment use :=, can only be used in sequential statements -- inside process() only

53 63 Exercise 3.11 State concurrent and sequential lines 1) architecture for_ex_arch of for_ex is 2) begin 3) outx1 < = out1 and in3; 4) process (in1, in2) 5) begin 6) out1 <= in1 and in2; 7) end process; 8) outx2 < = out1 or in3; 9) end for_ex_arch;

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