Structural Modeling with Verilog

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1 Structural Modeling with Verilog Recall that the ultimate purpose of verilog is that of a modeling language for cirucits. Moreover, verilog supports both structural and behaviorial modeling. structural modeling (glass box): a circuit is defined by explicitly showing how to construct it using logic gates,predefined modules, and the connections between them. behaviorial modeling (black box): a circuit is defined in terms of its behavior; e.g. in showing the relationships between the outputs and inputs. This may be done using truth-tables, Boolean equations, or arithmetic equations. Structural Modeling In structural modeling we first think of our circuit as a box or module which is encapuslated from its outer environment, in such a way that its only communication with the outer environment is through input and output ports. We then set out to describe the structure within the module by explicitly describing its gates and submodules, and how they connect with one another as well as to the module ports. In other words, structural modeling is akin to drawing a schematic diagram for the circuit. As an example, consider the full-adder below. 1

2 In what follows we will examine the rules and syntax for creating structural models in verilog, and give some examples. Syntax for defining modules. module module_name(iport_1,iport_2,...,iport_n,oport_1,oport_2,...,oport_m) //note: order of ports doesn t matter //declare the type of each port input iport_1,iport_2,...,iport_n; output oport_1,oport_2,...,oport_m; //optional: declare wires that connect gates and submodules // e.g. wire wire1,wire2,wire3; //provide a list of interconnected primitives or other modules // that comprise the module being defined Example 1. Define a module which models the full-adder circuit. 2

3 Alternative for declaring the ports of a module: module module_name (output oport_1,oport_2,...,oport_n, input iport_1,iport_2,...,iport_m); In Example 1 primitives were used to define the structure of Full Adder. The next Example shows that instantiations of user-defined modules may also be used to structurally model a circuit. Important: when using modules within a module, an instance name for the module must be used. Example 2. Use the Full Adder module to define a 4-bit ripple-carry adder. 3

4 The module Adder RC 4bit represents an example of top-down design, in which, on one level, the ripple-cary adder is defined in terms of four full adders. The full adder is then designed on another level of abstraction in terms of either half adders or primitive logic gates. This yields a hierarchical design having an abstraction-depth equal to 2. Thus, associated with a top-down design is a design tree whose levels represent different levels of abstraction, where the higher one goes up the tree, the more abstract the design becomes. The leaves of the tree are built-in primitives which do not need defining. The highest level of the tree is often referred to as the architectural level. Example 3. Draw the Adder RC 4bit design hierarchy in the form of a tree. 4

5 The name and declarations scope. All declarations and indentifiers have a scope that is local to the module, function, task, or procedure in which it was declared. Formal and acutal names for nets. formal name: the name given to the net in the declaration of the module. actual name: the name used in the instantiation of the module. Example 4. Consider the following declarations. What are the formal and actual names of module M1? module My_Module(output y, input u,w); or (y,u,w); module Your_Module(output y, input u,v,w,z); wire c1,c2; My_Module M1(c1,u,V); My_Module M2(c2,w,z); and (y,c1,c2); Rules for input and output variables. 1. formal input and inout ports must be nets, not registers 2. formal output ports can be a net, register, or integer 3. actual input ports can be a net, register, or integer 4. actual output and inout ports must be nets 5

6 Options for port connections. When instantiating a module, the (actual) port names in the port list must be in one-to-one correspondence with the module s formal names. There are two ways to make the association. connection by position: the i th port in the instantiated list corresponds with the i th port of the formal list. connection by name: the formal names are mapped to the actual names using the notation.formal name(actual name). Example 5. Rewrite the port list for modules M1 and M2 using the connection-by-name option. 6

7 Example 6. Use verilog to model a 4-bit comparator which uses two 2-bit comparators. 7

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