Programming for the Intel Many Integrated Core Architecture By James Reinders. The Architecture for Discovery. PowerPoint Title

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1 Programming for the Intel Many Integrated Core Architecture By James Reinders The Architecture for Discovery PowerPoint Title

2 Intel Xeon Phi coprocessor 1. Designed for Highly Parallel workloads 2. and Power efficiency 3. and Highly programmable 4. and Highly compacble to preserve soeware and expercse investments

3 Source Multicore CPU Compilers Libraries, Parallel Models Multicore CPU Intel MIC architecture coprocessor

4 Intel Xeon Phi Product Family: Game Changer for HPC Performance & Programmability Source Compilers Libraries, Parallel Models Multicore CPU Multicore CPU Intel MIC architecture coprocessor Unparalleled productivity most of this software does not run on a GPU - Robert Harrison, NICS, ORNL R. Harrison, Opportunities and Challenges Posed by Exascale Computing - ORNL's Plans and Perspectives, National Institute of Computational Sciences, Nov 2011

5 Extending the software ecosystem to deliver on the promise for software development for an SMP-on-a-chip Tools: great support The performance secret? Scale + Vectorize J Tasking / threading Soapbox on Vectorization Open Source Knights Corner Documents Performance TACC symposium

6 Intel C/C++ and Fortran Compilers w/openmp Intel MKL, Intel Cilk Plus, Intel TBB, and Intel IPP Intel Inspector XE, Intel VTune Ampli fier XE, Intel Advisor

7 Intel C/C++ and Fortran Compilers w/openmp Intel MKL, Intel Cilk Plus, Intel TBB, and Intel IPP Intel Inspector XE, Intel VTune Ampli fier XE, Intel Advisor Intel Parallel Studio XE

8 Intel C/C++ and Fortran Compilers w/openmp Intel MKL, Intel Cilk Plus, Intel TBB, and Intel IPP Intel Inspector XE, Intel VTune Ampli fier XE, Intel Advisor Intel MPI Library Intel Trace Analyzer and Collector Intel Parallel Studio XE

9 Intel C/C++ and Fortran Compilers w/openmp Intel MKL, Intel Cilk Plus, Intel TBB, and Intel IPP Intel Inspector XE, Intel VTune Ampli fier XE, Intel Advisor Intel MPI Library Intel Trace Analyzer and Collector Intel Parallel Studio XE

10 SoEware Development Ecosystem 1 for Intel MIC Compilers, Run environs Open Source gcc (kernel build only, not for applications), Python Commercial Intel C++ Compiler, Intel Fortran Compiler, MYO, CAPS * HMPP * compiler, ScaleMP * Debugger gdb Intel Debugger, Rogue Wave * TotalView *, Allinea * DDT Libraries TBB 1, MPICH2, FFTW, NetCDF Profiling & Analysis Tools NAG *, Intel MKL, Intel MPI, OpenMP * (in Intel compilers), Cilk Plus (in Intel compilers), Coarrray Fortran (Intel), Rogue Wave * IMSL, Intel IPP Intel VTune Amplifier XE, Intel Trace Analyzer & Collector, Intel Inspector XE Workload Scheduler Altair * PBS Professional, Adaptive * Computing Moab 1 These are all announced. Intel has said there are more accvely being developed but are not yet announced. Those in BOLD are available as of June Commercial support of TBB available from Intel. *Other names and brands may be claimed as the property of others.

11 SoEware Development Ecosystem 1 for Intel MIC Compilers, Run environs Open Source gcc (kernel build only, not for applications), Python Commercial Intel C++ Compiler, Intel Fortran Compiler, MYO, CAPS * HMPP * compiler, ScaleMP * Debugger gdb Intel Debugger, Rogue Wave * TotalView *, Allinea * DDT Libraries TBB 1, MPICH2, FFTW, NetCDF Profiling & Analysis Tools NAG *, Intel MKL, Intel MPI, OpenMP * (in Intel compilers), Cilk Plus (in Intel compilers), Coarrray Fortran (Intel), Rogue Wave * IMSL, Intel IPP Intel VTune Amplifier XE, Intel Trace Analyzer & Collector, Intel Inspector XE Workload Scheduler Altair * PBS Professional, Adaptive * Computing Moab 1 These are all announced. Intel has said there are more accvely being developed but are not yet announced. Those in BOLD are available as of June Commercial support of TBB available from Intel. *Other names and brands may be claimed as the property of others.

12 Extending the software ecosystem to deliver on the promise for software development for an SMP-on-a-chip Tools: great support The performance secret? Scale + Vectorize J Tasking / threading Soapbox on Vectorization Open Source Knights Corner Documents Performance TACC symposium

13 Cluster Models Intel Xeon Processor Intel MIC Coprocessor Main () MPI () Func () Intel Xeon Phi Coprocessor Beyond Acceleration MPI ranks only from MIC architecture cores. Single node or cluster. Ranks are homogeneous. Standard MPI, standard compilers, standard tools. Intel Xeon Processor Main () MPI () Func () Intel MIC Coprocessor Main () MPI () Func () MPI ranks from processors and coprocessors. Standard MPI, standard compilers, standard tools. Single node or cluster. Ranks are heterogeneous. Opening up new possibilities. Off-load Model Intel Xeon Processor Main () MPI () Func () Intel MIC Coprocessor Func () Serial code is run on the processor and parallel code is moved to coprocessor for execution. Language Extensions for Offload and x86 architecture offer significant improvements in compute flexibility. It is your Code. It is your Choice.

14 Intel Xeon Phi Coprocessor Beyond AcceleraCon GPU AcceleraCon Intel Xeon Phi Intel Xeon Processor Intel MIC Coprocessor Main () MPI () Func () Cluster Models Homogenous clustering Intel Xeon Processor Main () MPI () Func () Intel MIC Coprocessor Main () MPI () Func () Heterogeneous clustering Intel Xeon Processor Main () MPI () Func () GPU Func () Intel Xeon Processor Main () MPI () Func () Intel MIC Coprocessor Func () Off- load Model

15 Offload DirecCves and Standard Requirements Feature OpenACC LEO Desired Standard Support for C and C++, Fortran Support single code base of hetero- machine Overlap communicacon and computacon Interoperate with MPI Interoperate with OpenMP* Offload to GPU Offload to MIC Coprocessor Ability to support all accelerators Ability to support all GPUs Ability to support all co- processors Proof of performance portability Support for nested parallelism User- managed memory consistency MulCple vendor support Restrict clause support Support for dynamic dispatch Parallel on/off separate from offload PGI*, CAPS* compiler support 2012 Cray* compiler support soon Intel compiler support 2010* Broad standards body approval OpenMP* 4.0 (late 2012) maybe * not publicly available *Other names and brands may be claimed as the property of others. OpenMP 4.0?

16 Extending the software ecosystem to deliver on the promise for software development for an SMP-on-a-chip Tools: great support The performance secret? Scale + Vectorize J Tasking / threading Soapbox on Vectorization Open Source Knights Corner Documents Performance TACC symposium

17 Vector Width

18 Auto Vectorization: Useful, but limited by language void v_add (float *c, float *a, float *b) { for (int i=0; i<= MAX; i++) c[i]=a[i]+b[i]; } C/C++ language implies that vectorizing this loop is illegal Some code can be re-written in a way that the compiler can vectorize Hard to learn Impossible to completely automate Consider a Solution: Allow the programmer to express operations without unintended serial execution, using a new syntax.

19 What went wrong? Arrays not really in the language Pointers are, evil pointers!

20 What went wrong? Arrays not really in the language Pointers are, evil pointers! a.k.a. Fortran got this right how could C and C++ be so wrong for vectorization? How can we patch things up?

21 Source:

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31 Cilk Plus solution: Array Notations à Vector Operations <array base> [<lower bound>:<length>[:<stride>]] +! A[:] // All of vector A B[2:6] // Elements 2 to 7 of vector B C[:][5] // Column 5 of matrix C D[0:3:2] // Elements 0,2,4 of vector D if (a[:] > b[:]) { c[:] = d[:] * e[:]; } else { c[:] = d[:] * 2; } A simple and elegant solution: a language construct for vector level parallelism.

32 Source:

33 Intel Cilk Plus Ice breaker? Conversation starter? Ready for use, and ready for conversation. Both. Intel Compiler: Windows*, Linux*, Mac OS* X gcc: experimental branch Open Specification Other inspiration ISPC: research compiler exploring SPMD on SIMD *Other names and brands may be claimed as the property of others. 33

34 Intel Cilk Plus Ice breaker? Conversation starter? Ready for use, and ready for conversation. Both. Intel Compiler: Windows*, Linux*, Mac OS* X gcc: experimental branch Open Specification Other inspiration ISPC: research compiler exploring SPMD on SIMD *Other names and brands may be claimed as the property of others. 34

35 Intel Cilk Plus Vector parallelism Cilk Plus has two syntaxes for vector parallelism Array Notation #pragma simd TBB relies on things outside TBB for vector parallelism. TBB + #pragma simd is an attractive combination Thread parallelism Cilk Plus is a strict fork-join language Straitjacket enables strong guarantees about space. TBB permits arbitrary task graphs Flexibility provides hanging rope. 35

36 TBB and Cilk Plus make a great combination Vector parallelism Cilk Plus has two syntaxes for vector parallelism Array Notation #pragma simd TBB relies on things outside TBB for vector parallelism. TBB + #pragma simd is an attractive combination Thread parallelism Cilk Plus is a strict fork-join language Straitjacket enables strong guarantees about space. TBB permits arbitrary task graphs Flexibility provides hanging rope. 36

37 Vector Width

38 Vector Width Bottom line: Hardware vector capabilities are growing. Knights Corner makes them pretty interesting. Standard languages need help, C/C++ especially. Pragmas with auto-vectorization offer best all around answer. We look to engage everyone in finding better ways.

39 Extending the software ecosystem to deliver on the promise for software development for an SMP-on-a-chip Tools: great support The performance secret? Scale + Vectorize J Tasking / threading Soapbox on Vectorization Open Source Knights Corner Documents Performance TACC symposium

40 Knights Corner Where to learn more hep://intel.com/soeware/mic

41 Knights Corner: Open Source SoEware Stack Open Source So.ware Stack for Knights Corner Consists of the following: Embedded Linux Minimally Modified GCC and Driver SoEware GDB Intel Many Integrated Core (MIC) PlaDorm So.ware Stack (MPSS) Dependent on Linux Kernel Tested with Red Hat * Enterprise 6.0, 6.1, and 6.2 and SuSE * Linux Enterprise Server (SLES) 11 SP1. Updates made to open source to support: Knights Corner InstrucCon Set ApplicaCon Binary Interface (ABI) IniCalizaCon and Control an SMP- on- a- chip Glue SoEware to Support Coprocessor CommunicaCons with Host *Other names and brands may be claimed as the property of others.

42 Knights Corner SpecificaCon hep://intel.com/soeware/mic

43 TACC- Intel Highly Parallel CompuCng Symposium hep://intel.com/soeware/mic

44 TACC- Intel Highly Parallel CompuCng Symposium hep://intel.com/soeware/mic

45 TACC- Intel Highly Parallel CompuCng Symposium hep://intel.com/soeware/mic

46 Structured Parallel Programming using TBB and Cilk Plus Teaching structured parallel programming Designed for programmers not computer architects Teach best methods (known as paeerns) Coming: end of June 2012

47 Thank you Dual Tune Scale and vectorize helps and Together hep://intel.com/soeware/mic

48 Thank you Dual Tune Scale and vectorize helps and Together hep://intel.com/soeware/mic

49 Legal Disclaimer & OpCmizaCon NoCce INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO THIS INFORMATION INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Performance tests and racngs are measured using specific computer systems and/or components and reflect the approximate performance of Intel products as measured by those tests. Any difference in system hardware or soeware design or configuracon may affect actual performance. Buyers should consult other sources of informacon to evaluate the performance of systems or components they are considering purchasing. For more informacon on performance tests and on the performance of Intel products, reference soeware/products. Copyright 2012, Intel CorporaCon. All rights reserved. Intel, the Intel logo, Xeon, Core, Phi, VTune, and Cilk are trademarks of Intel CorporaCon in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Optimization Notice Intel s compilers may or may not optimize to the same degree for non-intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #