Announcements HW1 is due on this Friday (Sept 12th) Appendix A is very helpful to HW1. Check out system calls

Transcription

1 Announcements HW1 is due on this Friday (Sept 12 th ) Appendix A is very helpful to HW1. Check out system calls on Page A-48. Ask TA (Liquan chen: liquan@ece.rutgers.edu) about homework related questions. 331 W02.1 Fall 2003

2 Review I: Execute Cycle Q1: How does control know which instruction to fetch? Fetch Q2: who does decode? What happens in decode phase? Exec Decode Q3: How do control and datapath interact to finish exec phase? Q4: What does datapath have? 331 W02.2 Fall 2003

3 Review II: word length What does 32-bit architecture mean? 331 W02.3 Fall 2003

4 Hardware/Software Interface Application software System software Instruction set architecture includes everything programmers need to know to make a binary program to work Instruction Arithmetic and Logic Unit (ALU), registers, etc hardware Instruction set architecture (architecture) 331 W02.4 Fall 2003

5 The Instruction Set Architecture software instruction set architecture hardware The interface description separating the software and hardware. 331 W02.5 Fall 2003

6 How Do the Pieces Fit Together? Application Operating System Memory system Compiler Firmware Instr. Set Proc. Datapath & Control Digital Design Circuit Design I/O system Instruction Set Architecture Coordination of many levels of abstraction Under a rapidly changing set of forces Design, measurement, and evaluation 331 W02.6 Fall 2003

7 Assembly Language Language of the machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS arithmetic instructions We ll be working with the MIPS instruction set architecture similar to other architectures developed since the 1980's used by NEC, Nintendo, Silicon Graphics, Sony, 32-bit architecture - 32 bit data line and address line - data and addresses are 32-bit 331 W02.7 Fall 2003

8 MIPS R3000 Instruction Set Architecture Instruction Categories Load/Store Computational Jump and Branch Floating Point - coprocessor Memory Management Special Registers R0 - R31 PC HI LO 3 Instruction Formats: all 32 bits wide OP rs rt rd sa funct OP rs rt immediate OP jump target Q: How many already familiar with MIPS ISA? 331 W02.8 Fall 2003

9 MIPS Arithmetic Instruction MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 Each arithmetic instruction performs only one operation Each arithmetic instruction specifies exactly three operands destination source1 op source2 Those operands are contained in the datapath s register file ($t0, $s1,$s2) Operand order is fixed (destination first) 331 W02.9 Fall 2003

10 Compiling More Complex Statements Assuming variable b is stored in register $s1, c is stored in $s2, d is stored in $s3 and the result is to be left in $s0, and $t0 is a temporary register, what is the assembler equivalent to the C statement h = (b - c) + d 331 W02.10 Fall 2003

11 Registers Registers are Faster than main memory Can hold variables so that - code density improves (since registers are named with fewer bits than a memory location) why is that? Register addresses are indicated by using $ 331 W02.11 Fall 2003

12 MIPS Register File Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath s register file Holds thirty-two 32-bit registers - With two read ports and - One write port src1 addr src2 addr dst addr write data Register File 32 locations 32 bits src1 data src2 data 331 W02.12 Fall 2003

13 Naming Conventions for Registers 0 $zero constant 0 1 $at reserved for assembler 2 $v0 expression evaluation & 3 $v1 function results 4 $a0 arguments 5 $a1 6 $a2 7 $a3 8 $t0 temporary: caller saves... (callee can clobber) 15 $t7 16 $s0 callee saves... (caller can clobber) 23 $s7 24 $t8 temporary (cont d) 25 $t9 26 $k0 reserved for OS kernel 27 $k1 28 $gp pointer to global area 29 $sp stack pointer 30 $fp frame pointer 31 $ra return address 331 W02.13 Fall 2003

14 Registers vs. Memory Arithmetic instructions operands must be registers, only thirty-two registers provided Processor Devices Control Memory Input Datapath Output What about programs with lots of variables? Store variables in the memory Load variables from memory to registers before use; store them back to memory after use. 331 W02.14 Fall 2003

15 Accessing Memory MIPS has two basic data transfer instructions for accessing memory lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory The data transfer instruction must specify where in memory to read from (load) or write to (store) memory address where in the register file to write to (load) or read from (store) register destination (source) The memory address is formed by summing the constant portion of the instruction and the contents of the second register 331 W02.15 Fall 2003

16 Processor Memory Interconnections Memory is viewed as a large, single-dimension array, with an address A memory address is an index into the array read addr/ write addr 32 Processor read data 32write data 32 Memory 2 32 Addressable locations Q: what should be the smallest addressable unit? 331 W02.16 Fall 2003

17 MIPS Data Types Integer: (signed or unsigned) 32 bits Character: 8 bits Floating point numbers: 32 bits Memory addresses (pointers): 32 bits Instructions: 32 bits Bit String: sequence of bits of a particular length 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word 331 W02.17 Fall 2003

18 Byte Addresses Since 8-bit bytes are so useful, most architectures address individual bytes in memory memory: 2 32 bytes = 2 30 words Therefore, the memory address of a word must be a multiple of 4 (alignment restriction) Aligned Alignment restriction: requires that objects fall on address that is multiple of their size. Not Aligned 331 W02.18 Fall 2003

19 Addressing Objects: Endianess and Alignment Big Endian: leftmost byte is word address IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian: rightmost byte is word address Intel 80x86, DEC Vax, DEC Alpha (Windows NT) msb little endian byte 0 lsb bigendianbyte W02.19 Fall 2003

20 MIPS Memory Addressing The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register $s3 holds 8 Memory Data Word Address lw $t0, 4($s3) #what? is loaded into $t0 sw $t0, 8($s3) #$t0 is stored where? 331 W02.20 Fall 2003

21 Compiling with Loads and Stores Assuming variable b is stored in $s2 and that the base address of integer array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b... A[3] A[2] A[1] A[0]... $s3+12 $s3+8 $s3+4 $s3 331 W02.21 Fall 2003

22 Compiling with a Variable Array Index Assuming A is an integer array whose base is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b 331 W02.22 Fall 2003

23 MIPS Instructions, so far Category Instr Op Code Example Meaning Arithmetic add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s3 (R format) subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3 Data transfer load word 35 lw $s1, 100($s2) $s1 = Memory($s2+10 0) (I format) store word 43 sw $s1, 100($s2) Memory($s2+10 0) = $s1 331 W02.23 Fall 2003

24 Machine Language - Arithmetic Instruction Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2 registers have numbers $t0=$8, $s1=$17, $s2=$18 Instruction Format: op rs rt rd shamt funct Can you guess what the field names stand for? 331 W02.24 Fall 2003

25 MIPS Instruction Fields op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits = 32 bits op rs rt rd shamt funct 331 W02.25 Fall 2003

26 Machine Language - Load Instruction Consider the load-word and store-word instructions, What would the regularity principle have us do? New principle: Good design demands a compromise Introduce a new type of instruction format I-type for data transfer instructions previous format was R-type for register Example: lw $t0, 24($s2) op rs rt 16 bit number Where's the compromise? 331 W02.26 Fall 2003

27 Memory Address Location Example: lw $t0, 24($s2) Memory 0xf f f f f f f f $s2 = 0x $s2 0x Note that the offset can be positive or negative data 0x c 0x x x word address (hex) 331 W02.27 Fall 2003

28 Machine Language - Store Instruction Example: sw $t0, 24($s2) op rs rt 16 bit number A 16-bit address means access is limited to memory locations within a region of ±2 13 or 8,192 words (±2 15 or 32,768 bytes) of the address in the base register $s2 331 W02.28 Fall 2003

29 Assembling Code Remember the assembler code we compiled last lecture for the C statement A[8] = A[2] - b lw $t0, 8($s3) #load A[2] into $t0 sub $t0, $t0, $s2 #subtract b from A[2] sw $t0, 32($s3) #store result in A[8] Assemble the MIPS object code for these three instructions 331 W02.29 Fall 2003

30 Review: MIPS Data Types Integer: (signed or unsigned) 32 bits Character: 8 bits Floating point numbers: 32 bits Memory addresses (pointers): 32 bits Instructions: 32 bits Bit String: sequence of bits of a particular length 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word 331 W02.30 Fall 2003

31 Beyond Numbers Most computers use 8-bit bytes to represent characters with the American Std Code for Info Interchange (ASCII) ASCII Char ASCII Char ASCII Char ASCII Char ASCII Char ASCII Char 0 Null 32 space ` 112 p 1 33! A 97 a 113 q B 98 b 114 r 3 35 # C 99 c 115 s 4 EOT 36 $ D 100 d 116 t 5 37 % E 101 e 117 u 6 ACK 38 & F 102 f 118 v G 103 g 119 w 8 bksp 40 ( H 104 h 120 x 9 tab 41 ) I 105 i 121 y 10 LF 42 * 58 : 74 J 106 j 122 z ; 75 K 107 k 123 { 12 FF 44, 60 < 76 L 108 l / 63? 79 O 111 o 127 DEL So, we need instructions to move bytes around 331 W02.31 Fall 2003

32 Loading and Storing Bytes MIPS provides special instructions to move bytes lb sb $t0, 1($s3) #load byte from memory $t0, 6($s3) #store byte to memory op rs rt 16 bit number What 8 bits get loaded and stored? load byte places the byte from memory in the rightmost 8 bits of the destination register - what happens to the other bits in the register? store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory 331 W02.32 Fall 2003

33 Example of Loading and Storing Bytes Given following code sequence and memory state (contents are given in hexidecimal), what is the state of the memory after executing the code? add $s3, $zero, $zero lb $t0, 1($s3) sb $t0, 6($s3) Memory What value is left in $t0? F F F F F F F F A 0 Data What if the machine was little 8 Endian? 4 0 Word Address (Decimal) 331 W02.33 Fall 2003

34 Review: MIPS Instructions, so far Category Instr Op Code Example Meaning Arithmetic add 0 and 32 add $s1, $s2, $s3 $s1 = $s2 + $s3 (R format) subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3 Data load word 35 lw $s1, 100($s2) $s1 = Memory($s2+100) transfer store word 43 sw $s1, 100($s2) Memory($s2+100) = $s1 (I format) load byte 32 lb $s1, 101($s2) $s1 = Memory($s2+101) store byte 40 sb $s1, 101($s2) Memory($s2+101) = $s1 331 W02.34 Fall 2003

35 Review: MIPS R3000 ISA Instruction Categories Load/Store Computational Jump and Branch Floating Point - coprocessor Memory Management Special 3 Instruction Formats: all 32 bits wide Registers R0 - R31 PC HI LO 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits OP rs rt rd shamt funct R format OP rs rt 16 bit number I format OP 26 bit jump target 331 W02.35 Fall 2003