ECE232: Hardware Organization and Design

Transcription

1 ECE232: Hardware Organization and Design Lecture 4: MIPS Instructions Adapted from Computer Organization and Design, Patterson & Hennessy, UCB

2 From Last Time Two values enter from the left (A and B) Need to perform (A+B)+A In -> X (Load A) In -> Y (Load B) A+B -> Y (A+B)+A -> Out Four steps and then repeat InPass OutPass In Out LoadX X Y LoadY Function ALU AluPass ECE232: MIPS Instructions-I 2

3 Building Blocks Tri-State Buffer Truth table Gated D-latch (based on static value of enable pin, E) input output E D Q Q Comment 0 X Q prev Q prev No change Reset Set ECE232: MIPS Instructions-I 3

4 Arithmetic Logic Unit Examine the functionality of this 74LS382 ALU chip datasheet Performs 8 functions ECE232: MIPS Instructions-I 4

5 Conventions In the world, there are all kinds of conventions that we take for granted. Some are more commonly shared than others: ECE232: MIPS Instructions-I 5

6 Unsigned Binary Integers Given an n-bit number x = x + Range: 0 to +2 n 1 n 1 n n 12 + xn 22 +! + x12 x02 Example = = = Using 32 bits 0 to +4,294,967,295 Using 64 bits 0 to + 18,446,744,073,709,551,616 ECE232: MIPS Instructions-I 6

7 2s-Complement Signed Integers Bit 31 is sign bit 1 for negative numbers 0 for non-negative numbers ( 2 n 1 ) can t be represented Non-negative numbers have the same unsigned and 2scomplement representation Some specific numbers 0: : Most-negative: Most-positive: Example (4 bits): 0111 à à 8 ECE232: MIPS Instructions-I 7

8 2s-Complement Signed Integers Given an n-bit number x = x + n 1 n n 12 + xn 22 +! + x12 x02 Range: 2 n 1 to +2 n 1 1 Example = = 2,147,483, ,147,483,644 = 4 10 Using 32 bits 2,147,483,648 to +2,147,483,647 ECE232: MIPS Instructions-I 8

9 Addressing words: Big or Small Endian Big Endian: address of most significant byte = word address (xx00 = Big End of word) IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA (found in old Macintosh with PowerPC chip) Little Endian: address of least significant byte = word address (xx00 = Little End of word) Intel 80x86, DEC Vax, DEC Alpha (found in all modern PC computers: Mac and Windows) little endian byte 0 msb lsb big endian byte 0 ECE232: MIPS Instructions-I 9

10 Computer Organization 5 classic components of any computer Processor (CPU) (active) Control ( brain ) Datapath Computer Memory (passive) (where programs, & data live when running) Devices Input Output Keyboard, Mouse Disk (where programs, & data live when not running) Display, Printer The CPU Control fits in closely with datapath ECE232: MIPS Instructions-I 10

11 Program View of Memory Processor (CPU) Control Datapath Computer Memory Devices Input Output Memory viewed as a large, single -dimension array, with an address? 8 bits of data A memory address is an index into array The index points to a byte of memory - "Byte addressing" A 32-bit machine addresses memory by a 32-bit address Access bytes (8 bits), words (32 bits) or half-words bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data ECE232: MIPS Instructions-I 11

12 Memory word addressing CPU Address Bus Memory Every word in memory has an address Today machines address memory as bytes, hence word addresses differ by 4 Memory[0], Memory[4], Memory[8], Word 0 (bytes 0 to 3) Word 1 (bytes 4 to 7) 0x x x x C 0x x x x C 0xfffffff4 0xfffffffc 0xfffffffc Called the address of a word Memory 4GB Max (Typically 512MB-2GB) ECE232: MIPS Instructions-I 12

13 Registers Computer Processor (CPU) Control Memory Devices Input Datapath Registers Output Once a memory is fetched, the data must be placed somewhere in CPU Advantages of registers registers are faster than memory registers can hold variables and intermediate results memory traffic is reduced, so program runs faster code density improves (later) ECE232: MIPS Instructions-I 13

14 Registers code for A = B + C (This is not MIPS code, It is in English) load R1,B load R2,C add R3,R1,R2 store R3,A # R1 = B # R2 = C # R3 = R1+R2 # A = R3 Many current processors support 32 registers (MIPS) The more registers available, the fewer memory accesses will be necessary Registers can hold lots of intermediate values Instructions must include bits to specify which registers to operate on register address ECE232: MIPS Instructions-I 14

15 Instruction Set Architecture (ISA) Application (FireFox) Software Hardware Compiler Assembler Processor Operating System Memory (Unix; Windows) Datapath & Control Digital Design Circuit Design transistors, IC layout I/O system Instruction Set Architecture Key Idea: abstraction hide unnecessary implementation details helps us cope with enormous complexity of real systems ECE232: MIPS Instructions-I 15

16 The MIPS Instruction Set Used as the example throughout the book Stanford MIPS commercialized by MIPS Technologies ( Large share of embedded core market Applications in consumer electronics, network/storage equipment, cameras, printers, Typical of many modern ISAs See MIPS Reference Data tear-out card, and Appendices B and E ECE232: MIPS Instructions-I 16

17 Arithmetic Operations Add and subtract, three operands Two sources and one destination add a, b, c # a gets b + c All arithmetic operations have this form Design Principle 1: Simplicity favors regularity Regularity makes implementation simpler Simplicity enables higher performance at lower cost ECE232: MIPS Instructions-I 17

18 Arithmetic Example C or Java code: f = (g + h) - (i + j); Compiled MIPS code: add t0, g, h # temp t0 = g + h add t1, i, j # temp t1 = i + j sub f, t0, t1 # f = t0 - t1 ECE232: MIPS Instructions-I 18

19 Register Operands Arithmetic instructions use register operands MIPS has a bit register file Use for frequently accessed data Numbered 0 to bit data called a word Assembler names $t0, $t1,, $t9 for temporary values $s0, $s1,, $s7 for saved variables Design Principle 2: Smaller is faster c.f. (compare with) main memory: millions of locations ECE232: MIPS Instructions-I 19

20 Register Operand Example C or Java code: f = (g + h) - (i + j); f,, j in $s0,, $s4 Compiled MIPS code: add $t0, $s1, $s2 add $t1, $s3, $s4 sub $s0, $t0, $t1 ECE232: MIPS Instructions-I 20

21 Simplified Datapath Two register fetches in one cycle Load from memory Store to memory Registers A L U Data Memory From Register for SW To register for LW ECE232: MIPS Instructions-I 21

22 Memory Operands Main memory used for composite data Arrays, structures, dynamic data To apply arithmetic operations Load values from memory into registers Store result from register to memory Memory is byte addressed Each address identifies an 8-bit byte Words are aligned in memory Address must be a multiple of 4 MIPS is Big Endian Most-significant byte at least address of a word c.f. Little Endian: least-significant byte at least address ECE232: MIPS Instructions-I 22

23 Memory Operand Example 1 C code: g = h + A[8]; g in $s1, h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 4 bytes per word lw $t0, 32($s3) # load word add $s1, $s2, $t0 offset base register ECE232: MIPS Instructions-I 23

24 Memory Operand Example 2 C code: A[12] = h + A[8]; h in $s2, base address of A in $s3 Compiled MIPS code: Index 8 requires offset of 32 lw $t0, 32($s3) add $t0, $s2, $t0 sw $t0, 48($s3) # load word # store word ECE232: MIPS Instructions-I 24