EE 231 Fall EE 231 Lab 3
|
|
|
- Adam Brown
- 5 years ago
- Views:
Transcription
1 EE 231 Lab 3 Decoders and Multiplexers Decoders and multiplexers are important combinational circuits in many logic designs. Decoders convert n inputs to a maximum of unique 2 n outputs. A special case is the BCDto-seven-segment decoder, where a four-bit decimal digit (represented in BCD) is decoded into the corresponding seven segment code used as an input to the seven-segment display (Figure 1). 1. Prelab Figure 1. 7-Segment Display 1. Wire wrap the two 7-segment displays along with the pin header needed on a perf board. Schematics of MAN74 7-segment display. 2. Fill in the truth table for the BCD-to-7-segment decoder shown in Table 1, e.g., if the input is 0011, LEDs a,b,c,d and g should be on while LEDs f and e will be off (see Figure 1). For inputs 0xA through 0xF, naturally they don t correspond to any number in the range 0-9, therefore output the corresponding hex value instead, i.e., for 0xA the display should show the letter A. 3. A simple computer has several main blocks, e.g., Arithmetic logic unit (ALU): performs arithmetic operations on numbers. Memory: where the program is stored. Multiplexers: select which piece of information to be passed on. Decoders: to determine, based on the input, whether to read from memory or input/output lines. 1
2 Computer control unit: outputs the control signals that direct the operation of the rest of the computer. Even though we are not building a computer, this information gives you some prospective on the different components that you will be building and what they may be used for. In this lab we will focus on the multiplexer that chooses either a reset address ( RST ADDR), program counter (PC), memory address register (MAR), or Index Register X (IRX). These signals are used to determine the information required to enter the arithmetic logic unit component of the computer. (a) Design a multiplexer with ADDR SEL as the select signal, RST ADDR (we will use address 0xFF), PC, MAR, and X as 8-bit input signals. (b) Design a Verilog program to implement this multiplexer. Table 1. Truth table for 7-segment-display decoder ( 1 LED is on, and 0 it is off). 2. Lab 1. Place a block of 8 DIP switches on your breadboard, see Figure Connect each lead on one side to VCC. 3. Put a 1k resistor from each of the leads on the other side to ground. Also on this side, place a row of 8 pin headers so that you have outputs from all of these switches. 2
3 4. In order to be able to connect to the board you will need to solder pin headers to one of the prototyping areas (see Figure 3). Use area A. For now solder the first two rows (Figure 4). 5. Use Figure 5 for the pin labels. 6. Now that you have all the hardware setup. Design the BCD-to-sevensegment decoder and test it using different inputs using the dip switches. 7. Implement the multiplexer program that you developed in the prelab, as shown in Figure 6. To test the multiplexer we need to hard wire (in Verilog) RST ADDR to 0xFF, PC to address 0x0A, and MAR to 0x10. Connect IR to the 8 DIP switches, and MEM SEL to 2 push-button switches on the board. Figure 2. Dip Switches Figure 3. MAX II Micro Board 3
4 Figure 4. MAXII Micro Board With PIN Headers Figure 5. I/O Map of Prototyping Areas. 4
5 Figure 6. Implementation of a simple multiplexer 3. Supplementary Material 3.1 More on Verilog Three-State Gates If the control signal is 1, the output is enabled, and if the control signal is 0, the output is disabled and the gate is in high-impedance mode. There are three types of three-state gates. 1. bufif1(output, input, control): output equals the input if the control signal is 1, and high-impedance state,z, if the control signal is bufif0(output, input, control): the control signal is the complement of bufif1. 3. notif1(output, input, control): same as bufif1 except the output is the complement of the input if the control signal is notif0(output, input, control): same as bufif0 except the output is the complement of the input if the control signal is Logic Levels 0 Logic zero, false condition 1 logic one, true condition x unknown logic value z high impedance 3.2 Verilog Behavioral Modeling 5
6 3.2.1 always and reg 1. Behavioral modeling uses the keywords always. Figure 6. Three-state Gate 2. Target output is a type reg. Unlike a wire, reg is updated only when a new value is assigned. In other words, it is not continuously updated as wire data types. 3. always may be followed by an event control expression. 4. always is followed by the followed by a list of variables. Each time there is a change in those variables, the always block is executed. 5. There is no semicolon at the end of the always block. 6. The list of variables are separated by logical operator or and not bitwise OR operator. 7. Below is an example of an always block. or B) if-else Statements if-else statements provide a means for conditional outputs based on the arguments of the if statement case Statements 6
7 case Statements provide an easy way to represent a multi-branch conditional statement. 1. The first statement that makes a match is executed. 2. Unspecified bit patterns could be treated sing default keyword. output out; input s,a,b; reg out; if(s) out=a; else out=b; // if select is 1 then out is A // else output is B Program 1 Four-to-one Line Multiplexer module mux_4x1_example( output reg out, input [1:0] s, // select represented by 2 bits input in_0, in_1, in_2, in_3); in_1, in_2, in_3, s) case(s) 2 b00: out = in_0; // if s is 00 then output is in_0 2 b01: out = in_1; // if s is 01 then output is in_1 2 b10: out = in_2; // 2 b11: out = in_3; endcase endmodule 7
EE 231 Fall EE 231 Lab 3. Decoders and Multiplexers. Figure 1: 7-Segment Display. Memory: where the program is stored.
EE 231 Lab 3 Decoders and Multiplexers Decoders and multiplexers are important combinational circuits in many logic designs. Decoders convert n inputs to a maximum of unique 2 n outputs. A special case
EE 231 Fall Lab 2: Decoders and Multiplexers. Introduction
Lab 2: Decoders and Multiplexers Introduction Decoders and multiplexers are important combinational circuits in many logic designs. Decoders convert n inputs to a maximum of unique 2 n outputs. A special
Lab 3: Standard Combinational Components
Lab 3: Standard Combinational Components Purpose In this lab you will implement several combinational circuits on the DE1 development board to test and verify their operations. Introduction Using a high-level
Spring 2017 EE 3613: Computer Organization Chapter 5: Processor: Datapath & Control - 2 Verilog Tutorial
Spring 2017 EE 3613: Computer Organization Chapter 5: Processor: Datapath & Control - 2 Verilog Tutorial Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio
Workshop on Digital Circuit Design in FPGA
Workshop on Digital Circuit Design in FPGA Session-1 Presented By Mohammed Abdul Kader Assistant Professor, Dept. of EEE, IIUC Email:kader05cuet@gmail.com Website: kader05cuet.wordpress.com The field-programmable
EE 231 Fall EE 231 Lab 2
EE 231 Lab 2 Introduction to Verilog HDL and Quartus In the previous lab you designed simple circuits using discrete chips. In this lab you will do the same but by programming the CPLD. At the end of the
To design a 4-bit ALU To experimentally check the operation of the ALU
1 Experiment # 11 Design and Implementation of a 4 - bit ALU Objectives: The objectives of this lab are: To design a 4-bit ALU To experimentally check the operation of the ALU Overview An Arithmetic Logic
Verilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering
Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering VERILOG FUNDAMENTALS HDLs HISTORY HOW FPGA & VERILOG ARE RELATED CODING IN VERILOG HDLs HISTORY HDL HARDWARE DESCRIPTION LANGUAGE
EECS 270 Midterm Exam
EECS 270 Midterm Exam Fall 2009 Name: unique name: Sign the honor code: I have neither given nor received aid on this exam nor observed anyone else doing so. Scores: NOTES: Problem # Points 1 /11 2 /4
Lab 5: Arithmetic Logic Unit (ALU)
Lab 5: Arithmetic Logic Unit (ALU) September 29, 2009 Contents 1 Prelab 4 2 Lab 4 3 Supplementary Material 6 3.1 Verilog................................................. 6 3.1.1 Parameters..........................................
Introduction. Why Use HDL? Simulation output. Explanation
Introduction Verilog HDL is a Hardware Description Language (HDL) HDL is a language used to describe a digital system, for example, a computer or a component of a computer. Most popular HDLs are VHDL and
EE 231 Fall Lab 1: Introduction to Verilog HDL and Altera IDE
Lab 1: Introduction to Verilog HDL and Altera IDE Introduction In this lab you will design simple circuits by programming the Field-Programmable Gate Array (FPGA). At the end of the lab you should be able
Finite State Machine Lab
Finite State Machine Module: Lab Procedures Goal: The goal of this experiment is to reinforce state machine concepts by having students design and implement a state machine using simple chips and a protoboard.
Lab 4: Arithmetic Logic Unit (ALU)
EE 231-1 - Fall 2016 Lab 4: Arithmetic Logic Unit (ALU) Introduction The heart of every computer is an Arithmetic Logic Unit (ALU). This is the part of the computer which performs arithmetic operations
Verilog Module 1 Introduction and Combinational Logic
Verilog Module 1 Introduction and Combinational Logic Jim Duckworth ECE Department, WPI 1 Module 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog
Introduction to Verilog/System Verilog
NTUEE DCLAB Feb. 27, 2018 Introduction to Verilog/System Verilog Presenter: Yao-Pin Wang 王耀斌 Advisor: Prof. Chia-Hsiang Yang 楊家驤 Dept. of Electrical Engineering, NTU National Taiwan University What is
CSCB58 - Lab 3. Prelab /3 Part I (in-lab) /2 Part II (in-lab) /2 TOTAL /8
CSCB58 - Lab 3 Latches, Flip-flops, and Registers Learning Objectives The purpose of this exercise is to investigate the fundamental synchronous logic elements: latches, flip-flops, and registers. Prelab
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013
EPC6055 Digital Integrated Circuits EXAM 1 Fall Semester 2013 Print Here Student ID Signature This is a closed book exam. The exam is to be completed in one-hundred ten (110) minutes. Don t use scratch
University of Hawaii EE 361L. Getting Started with Spartan 3E Digilent Basys2 Board. Lab 4.1
University of Hawaii EE 361L Getting Started with Spartan 3E Digilent Basys2 Board Lab 4.1 I. Test Basys2 Board Attach the Basys2 board to the PC or laptop with the USB connector. Make sure the blue jumper
UNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination
Combinational Logic II
Combinational Logic II Ranga Rodrigo July 26, 2009 1 Binary Adder-Subtractor Digital computers perform variety of information processing tasks. Among the functions encountered are the various arithmetic
Brief Introduction to Verilog HDL (Part 1)
BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS FACULTY OF ELECTRICAL ENGINEERING AND INFORMATICS DEPARTMENT OF MEASUREMENT AND INFORMATION SYSTEMS Brief Introduction to Verilog HDL (Part 1) Tamás Raikovich
EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE
EE 8351 Digital Logic Circuits Ms.J.Jayaudhaya, ASP/EEE 1 Logic circuits for digital systems may be combinational or sequential. A combinational circuit consists of input variables, logic gates, and output
ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7
structure syntax different levels of abstraction
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this
This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital
Verilog Design Principles
16 h7fex // 16-bit value, low order 4 bits unknown 8 bxx001100 // 8-bit value, most significant 2 bits unknown. 8 hzz // 8-bit value, all bits high impedance. Verilog Design Principles ECGR2181 Extra Notes
Introduction to Verilog
Introduction to Verilog Structure of a Verilog Program A Verilog program is structured as a set of modules, which may represent anything from a collection of logic gates to a complete system. A module
Register Transfer and Micro-operations
Register Transfer Language Register Transfer Bus Memory Transfer Micro-operations Some Application of Logic Micro Operations Register Transfer and Micro-operations Learning Objectives After reading this
Workshop on Digital Circuit Design in FPGA
Organized by: Dept. of EEE Workshop on Digital Circuit Design in FPGA Presented By Mohammed Abdul Kader Assistant Professor, Dept. of EEE, IIUC Email:kader05cuet@gmail.com Website: kader05cuet.wordpress.com
PRELAB! Read the entire lab, and complete the prelab questions (Q1-Q3) on the answer sheet before coming to the laboratory.
PRELAB! Read the entire lab, and complete the prelab questions (Q1-Q3) on the answer sheet before coming to the laboratory. 1.0 Objectives In the last lab we learned that Verilog is a fast and easy way
Computer Aided Design Basic Syntax Gate Level Modeling Behavioral Modeling. Verilog
Verilog Radek Pelánek and Šimon Řeřucha Contents 1 Computer Aided Design 2 Basic Syntax 3 Gate Level Modeling 4 Behavioral Modeling Computer Aided Design Hardware Description Languages (HDL) Verilog C
Verilog introduction. Embedded and Ambient Systems Lab
Verilog introduction Embedded and Ambient Systems Lab Purpose of HDL languages Modeling hardware behavior Large part of these languages can only be used for simulation, not for hardware generation (synthesis)
Lab 0: Wire Wrapping Project: Counter Board
Lab 0: Wire Wrapping Project: Counter Board September 3, 2008 In this experiment, you will build a simple counter circuit that can be plugged into your breadboard. It will provide a set of TTL output signals
Introduction to Verilog HDL
Introduction to Verilog HDL Ben Abdallah Abderazek National University of Electro-communications, Tokyo, Graduate School of information Systems May 2004 04/09/08 1 What you will understand after having
ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL. Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS
ECE 574: Modeling and Synthesis of Digital Systems using Verilog and VHDL Fall 2017 Final Exam (6.00 to 8.30pm) Verilog SOLUTIONS Note: Closed book no notes or other material allowed apart from the one
Introduction to Verilog HDL. Verilog 1
Introduction to HDL Hardware Description Language (HDL) High-Level Programming Language Special constructs to model microelectronic circuits Describe the operation of a circuit at various levels of abstraction
Experiment 9: Binary Arithmetic Circuits. In-Lab Procedure and Report (30 points)
ELEC 2010 Laboratory Manual Experiment 9 In-Lab Procedure Page 1 of 7 Experiment 9: Binary Arithmetic Circuits In-Lab Procedure and Report (30 points) Before starting the procedure, record the table number
CSC 220: Computer Organization Unit 10 Arithmetic-logic units
College of Computer and Information Sciences Department of Computer Science CSC 220: Computer Organization Unit 10 Arithmetic-logic units 1 Remember: 2 Arithmetic-logic units An arithmetic-logic unit,
Course Topics - Outline
Course Topics - Outline Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 Behavioral modeling B Lecture 7
EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS
EE 2 Lab Manual, EE Department, KFUPM EXPERIMENT #8: BINARY ARITHMETIC OPERATIONS OBJECTIVES: Design and implement a circuit that performs basic binary arithmetic operations such as addition, subtraction,
HW1 Modeling Concepts
HW1 Modeling Concepts Verilog HDL modeling language supports three kinds of modeling styles: gate-level, dataflow, and behavioral. The gate-level and datafow modeling are used to model combinatorial circuits
Lab 2: Introduction to Verilog HDL and Quartus
Lab 2: Introduction to Verilog HDL and Quartus September 16, 2008 In the previous lab you designed simple circuits using discrete chips. In this lab you will do the same but by programming the CPLD. At
EEL 4783: Hardware/Software Co-design with FPGAs
EEL 4783: Hardware/Software Co-design with FPGAs Lecture 8: Short Introduction to Verilog * Prof. Mingjie Lin * Beased on notes of Turfts lecture 1 Overview Recap + Questions? What is a HDL? Why do we
EE 3170 Microcontroller Applications
EE 3170 Microcontroller Applications Lecture 4 : Processors, Computers, and Controllers - 1.2 (reading assignment), 1.3-1.5 Based on slides for ECE3170 by Profs. Kieckhafer, Davis, Tan, and Cischke Outline
Programmable machines
Page 1 of 9 Programmable machines indicates problems that have been selected for discussion in section, time permitting. Problem 1. Consider the following circuit: The heavy lines represent busses, which
ELEC 2200 Digital Logic Circuits
ELEC 22 Digital Logic Circuits Charles E. Stroud, Professor Dept. of Electrical & Computer Engineering Office: 325 Broun Hall Email: cestroud@eng.auburn.edu Text: Digital Logic Circuit Analysis & Design
Verilog. Like VHDL, Verilog HDL is like a programming language but:
Verilog Verilog Like VHDL, Verilog HDL is like a programming language but: Statements can execute simultaneously unlike programming e.g. nand(y1,a1,b1); nand(y2,a2,b2); or (out,y1,y2); a1 b1 all statements
General FSM design procedure
Sequential logic examples Basic design approach: a 4-step design process Hardware description languages and finite state machines Implementation examples and case studies finite-string pattern recognizer
EECS150, Fall 2004, Midterm 1, Prof. Culler. Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function.
Problem 1 (15 points) 1.a. Circle the gate-level circuits that DO NOT implement a Boolean AND function. 1.b. Show that a 2-to-1 MUX is universal (i.e. that any Boolean expression can be implemented with
Register-Level Design
Register-Level Design A digital system can be treated at different level of abstraction or compleity. So far, we have seen it at the gate level and the transistor level. At a higher level than the gate
General FSM design procedure
Sequential logic examples Basic design approach: a 4-step design process Hardware description languages and finite state machines Implementation examples and case studies finite-string pattern recognizer
PART 1. Simplification Using Boolean Algebra
Name EET 1131 Lab #5 Logic Simplification Techniques OBJECTIVES: Upon completing this lab, you ll be able to: 1) Obtain the experimental truth table of a logic circuit. 2) Use Boolean algebra to simplify
a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign
![a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign](/thumbs/91/106466219.jpg "a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign")
I hope you have completed Part 1 of the Experiment. This lecture leads you to Part 2 of the experiment and hopefully helps you with your progress to Part 2. It covers a number of topics: 1. How do we specify
Lab Manual for COE 203: Digital Design Lab
Lab Manual for COE 203: Digital Design Lab 1 Table of Contents 1. Prototyping of Logic Circuits using Discrete Components...3 2. Prototyping of Logic Circuits using EEPROMs...9 3. Introduction to FPGA
Verilog. Verilog for Synthesis
Verilog Verilog for Synthesis 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog enhanced version Verilog-XL 1987: Verilog-XL becoming more popular
Lecture #2: Verilog HDL
Lecture #2: Verilog HDL Paul Hartke Phartke@stanford.edu Stanford EE183 April 8, 2002 EE183 Design Process Understand problem and generate block diagram of solution Code block diagram in verilog HDL Synthesize
IA Digital Electronics - Supervision I
IA Digital Electronics - Supervision I Nandor Licker Due noon two days before the supervision 1 Overview The goal of this exercise is to design an 8-digit calculator capable of adding
N-input EX-NOR gate. N-output inverter. N-input NOR gate
Hardware Description Language HDL Introduction HDL is a hardware description language used to design and document electronic systems. HDL allows designers to design at various levels of abstraction. It
Verilog Design Principles
16 h7fex // 16-bit value, low order 4 bits unknown 8 bxx001100 // 8-bit value, most significant 2 bits unknown. 8 hzz // 8-bit value, all bits high impedance. Verilog Design Principles ECGR2181 Extra Notes
Microcomputer Architecture and Programming
IUST-EE (Chapter 1) Microcomputer Architecture and Programming 1 Outline Basic Blocks of Microcomputer Typical Microcomputer Architecture The Single-Chip Microprocessor Microprocessor vs. Microcontroller
Department of Computer and Mathematical Sciences. Lab 4: Introduction to MARIE
Department of Computer and Mathematical Sciences CS 3401 Assembly Language 4 Lab 4: Introduction to MARIE Objectives: The main objective of this lab is to get you familiarized with MARIE a simple computer
VERILOG. Deepjyoti Borah, Diwahar Jawahar
VERILOG Deepjyoti Borah, Diwahar Jawahar Outline 1. Motivation 2. Basic Syntax 3. Sequential and Parallel Blocks 4. Conditions and Loops in Verilog 5. Procedural Assignment 6. Timing controls 7. Combinatorial
ASSIGNMENT ECE514 (COMPUTER ORGANIZATION) ASSIGNMENT NO. 3
ASSIGNMENT ECE514 (COMPUTER ORGANIZATION) ASSIGNMENT NO. 3 This is an individual assignment for ECE514. It carries a mark of 10%. The rubric of marks is given in Appendix 3. This assignment is about designing
UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT
UNIT-III 1 KNREDDY UNIT-III REGISTER TRANSFER LANGUAGE AND DESIGN OF CONTROL UNIT Register Transfer: Register Transfer Language Register Transfer Bus and Memory Transfers Arithmetic Micro operations Logic
Arithmetic-logic units
Arithmetic-logic units An arithmetic-logic unit, or ALU, performs many different arithmetic and logic operations. The ALU is the heart of a processor you could say that everything else in the CPU is there
ENEE245 Digital Circuits and Systems Lab Manual
ENEE245 Digital Circuits and Systems Lab Manual Department of Engineering, Physical & Computer Sciences Montgomery College Modified Fall 2017 Copyright Prof. Lan Xiang (Do not distribute without permission)
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
General FSM design procedure
Sequential logic examples Basic design approach: a 4-step design process Hardware description languages and finite state machines Implementation examples and case studies finite-string pattern recognizer
Pre-Laboratory #Boolean Expressions ECE 332
Name: G Number: Pre-Laboratory #Boolean Expressions ECE 332 1 Introduction This pre-lab is divided into two parts. In part one you will build a circuit for providing inputs to your CPLD board on your breadboard.
Graduate Institute of Electronics Engineering, NTU. Lecturer: Chihhao Chao Date:
Synthesizable Coding of Verilog Lecturer: Date: 2009.03.18 ACCESS IC LAB Outline Basic concepts of logic synthesis Synthesizable Verilog coding subset Verilog coding practices Coding for readability Coding
14:332:231 DIGITAL LOGIC DESIGN. Hardware Description Languages
14:332:231 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering Fall 2013 Lecture #22: Introduction to Verilog Hardware Description Languages Basic idea: Language constructs
Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23
98-1 Under-Graduate Project Synthesis of Combinational Logic Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23 What is synthesis? Outline Behavior Description for Synthesis Write Efficient HDL
Chapter 3 Part 2 Combinational Logic Design
University of Wisconsin - Madison ECE/Comp Sci 352 Digital Systems Fundamentals Kewal K. Saluja and Yu Hen Hu Spring 2002 Chapter 3 Part 2 Combinational Logic Design Originals by: Charles R. Kime and Tom
A B A+B
ECE 25 Lab 2 One-bit adder Design Introduction The goal of this lab is to design a one-bit adder using programmable logic on the BASYS board. Due to the limitations of the chips we have in stock, we need
8051 Interfacing: Address Map Generation
85 Interfacing: Address Map Generation EE438 Fall2 Class 6 Pari vallal Kannan Center for Integrated Circuits and Systems University of Texas at Dallas 85 Interfacing Address Mapping Use address bus and
Nikhil Gupta. FPGA Challenge Takneek 2012
Nikhil Gupta FPGA Challenge Takneek 2012 RECAP FPGA Field Programmable Gate Array Matrix of logic gates Can be configured in any way by the user Codes for FPGA are executed in parallel Configured using
Chapter 10. case studies in sequential logic design
Chapter. case studies in sequential logic design This is the last chapter of this course. So far, we have designed several sequential systems. What is the general procedure? The most difficult part would
Lab 7 (All Sections) Prelab: Introduction to Verilog
Lab 7 (All Sections) Prelab: Introduction to Verilog Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work 1 Objective The
ECE 313 Computer Organization EXAM 2 November 11, 2000
This exam is open book and open notes. You have 50 minutes. Credit for problems requiring calculation will be given only if you show your work. 1. ALU Design / Logic Operations 20 Points The subset of
Homework deadline extended to next friday
Norm Midterm Grading Finished Stats on course homepage Pickup after this lab lec. Regrade requests within 1wk of posted solution Homework deadline extended to next friday Description Design Conception
Chap 6 Introduction to HDL (d)
Design with Verilog Chap 6 Introduction to HDL (d) Credit to: MD Rizal Othman Faculty of Electrical & Electronics Engineering Universiti Malaysia Pahang Ext: 6036 VERILOG HDL Basic Unit A module Module
7 8 9 C. PRELAB REQUIREMENTS You must adhere to the Lab Rules and Policies document for every lab.
Page 1/ Revision 1 OBJECTIVES To understand how a keypad functions as a raster scan input device and to learn how to interface a keypad to a microprocessor. Further explore and understand the implementation
Verilog Tutorial - Edited for CS141
- Edited for CS141 Lukasz Strozek October 8, 2005 Based on Weste and Harris and Verilog According to Tom 1 Introduction Verilog is language commonly used in designing digital systems. It s a hardware description
Verilog 1 - Fundamentals
Verilog 1 - Fundamentals FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2],
Modeling Concepts. Introduction
Introduction Verilog HDL modeling language supports three kinds of modeling styles: gate-level, dataflow, and behavioral. The gate-level and datafow modeling are used to model combinatorial circuits whereas
Input/Output Ports and Interfacing
Input/Output Ports and Interfacing ELEC 330 Digital Systems Engineering Dr. Ron Hayne Images Courtesy of Ramesh Gaonkar and Delmar Learning Basic I/O Concepts Peripherals such as LEDs and keypads are essential
NH 67, Karur Trichy Highways, Puliyur C.F, Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF INFORMATION TECHNOLOGY CS 2202 DIGITAL PRINCIPLES AND SYSTEM DESIGN UNIT 2 COMBINATIONAL LOGIC Combinational circuits Analysis
Digital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
Chapter 1: Basics of Microprocessor [08 M]
![Chapter 1: Basics of Microprocessor [08 M]](/thumbs/77/75860546.jpg "Chapter 1: Basics of Microprocessor [08 M]")
Microprocessor: Chapter 1: Basics of Microprocessor [08 M] It is a semiconductor device consisting of electronic logic circuits manufactured by using either a Large scale (LSI) or Very Large Scale (VLSI)
University of California, Davis Department of Electrical and Computer Engineering. Lab 1: Implementing Combinational Logic in the MAX10 FPGA
1 University of California, Davis Department of Electrical and Computer Engineering EEC180B DIGITAL SYSTEMS II Winter Quarter 2018 Lab 1: Implementing Combinational Logic in the MAX10 FPGA Objective: This
CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND:
CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOALS: Getting familiar with DE2 board installation, properties, usage.
ENEE245 Digital Circuits and Systems Lab Manual
ENEE245 Digital Circuits and Systems Lab Manual Department of Engineering, Physical & Computer Sciences Montgomery College Version 1.1 Copyright Prof. Lan Xiang (Do not distribute without permission) 1
ES611 FPGA Based System Design. Behavioral Model
ES611 FPGA Based System Design Behavioral Model Structural procedures Two statements Initial always initial they execute only once always they execute for ever (until simulation finishes) initial block
Verilog. What is Verilog? VHDL vs. Verilog. Hardware description language: Two major languages. Many EDA tools support HDL-based design
Verilog What is Verilog? Hardware description language: Are used to describe digital system in text form Used for modeling, simulation, design Two major languages Verilog (IEEE 1364), latest version is
Contents. Appendix D Verilog Summary Page 1 of 16
Appix D Verilog Summary Page 1 of 16 Contents Appix D Verilog Summary... 2 D.1 Basic Language Elements... 2 D.1.1 Keywords... 2 D.1.2 Comments... 2 D.1.3 Identifiers... 2 D.1.4 Numbers and Strings... 3
EN2911X: Reconfigurable Computing Lecture 05: Verilog (2)
EN2911X: Lecture 05: Verilog (2) Prof. Sherief Reda Division of Engineering, Brown University Fall 09 http://scale.engin.brown.edu Dataflow modeling Module is designed by specifying the data flow, where
ECE Digital System Design & Synthesis Exercise 1 - Logic Values, Data Types & Operators - With Answers
ECE 601 - Digital System Design & Synthesis Exercise 1 - Logic Values, Data Types & Operators - With Answers Fall 2001 Final Version (Important changes from original posted Exercise 1 shown in color) Variables
Lab 7 (Sections 300, 301 and 302) Prelab: Introduction to Verilog
Lab 7 (Sections 300, 301 and 302) Prelab: Introduction to Verilog Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work