# Switching Theory & Logic Design/Digital Logic Design Question Bank

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1 Switching Theory & Logic Design/Digital Logic Design Question Bank UNIT I NUMBER SYSTEMS AND CODES 1. A 12-bit Hamming code word containing 8-bits of data and 4 parity bits is read from memory. What was the original 8-bit data word that was written in to memory if 12-bit words read out is as follows? [4 4 = 16] (a) (b) (RR,R05,Nov 08SET II,III) (c) (d) RR,R05 Nov 06,mar06,R05 Nov 08) SET I,IV 2. Convert the following to Decimal and then to Hexadecimal. (a) 7448 (b) (c) (d) (e) (f) [ ] (Nov 05,Mar 06,SET II,IV) 3. (a) Perform the following using BCD arithmetic. [2 4 = 8] i ii (b) Convert the following. [4 2 = 8] i. AB16 = ( )10 ii = ( )10 iii = ( )10 iv = ( )16 (RR,R07,Nov 09SET IiI,IV) 4. Convert the following to Decimal and then to Octal. (a) (b) 12EF16 (c) (d) (e) (f) [ ] R07(MAY 10)SET I, II 5. Convert the following to Decimal and then to Binary. (a) (b) ABCD16 (c) (d) (e) (f) [ ] R07(MAY 10)SET III, IV 6. Convert the following to Decimal and then to Binary:(a) (b) A44D16 (c) (d) (e) f) [ ] (Aug2008,S-1,4) 7. Convert the following to Decimal and then to Octal. a) (b) 125F16 (c) (d) (e) (f) [ ]. Nov 06 SET2 8. a) What are Hamming Codes? Explain. b) Convert into 2 s complement c) What are signed bits explain with a example. [4+8+4] (RR,R07,MAY10SET IiI,IV) 9. a) What is meant by parity. b) Explain the concept of Error Correcting & Detecting Codes. [5+5] 10 a) find the 2 s complement of the numbers: (i) (ii) b) represent (-17)10 in (i) sign magnitude (ii) one s complement (iii) two s complement 11.Perform the following operation using 2 s complement operation. (i) 48, (-23) (ii) 23, (-48) (iii) (-23), (-48). 12. a)convert ( ) 8 into its equivalent decimal number. b) Convert ( ) 10 in to octal 13. Convert the following binary numbers to octal numbers a) b) c) Add (23) 8 and (67) 8 15 a) what are the different types of codes. b) write the various binary codes from 0 to 15 in decimal.

2 16 Given a = and b = Find i) a+b ii) a-b iii) a.b iv)b+a v)b-a 17. a) What is gray code? What are the rules to construct Grey code? Develop the 4 bit gray code for the decimal 0 to 15. b) What is the advantage of 1 s and 2 s complement in computers. Represent +45 and -45 in sign-magnitude, sign-1 s complement and sign-2 s complement representation. [8+8] 18.(a) Construct an even parity seven bit code to transmit the data (b) Find the 10 th element in the base 3 number system. [8+8] (NR)Nov (a) Generate Hamming code for the given 11 bit message and re write the entire message with Hamming code. [8] ( b) The binary numbers listed have a sign bit in the left most position and, if negative numbers are in 2 s complement form. Perform the arithmetic operations indicated and verify the answers. [4 2 = 8] i ii iii iv (a) Write the following binary numbers in signed 1 s complement form and signed 2 s complement form using 16 bit registers. i ii iii iv (b) Perform N1+N2, N1+(-N2) for the following 8 bit numbers expressed in a 2 s complement representation. Verify your answers by using decimal addition and subtraction i. N1= , N2= ii. N1= , N2= [10+6] 21 a) What is the necessity of Binary Codes in Computers? b) Convert (2AC5.D) to Binary and then to octal. 22. What are the rules for excess 3 addition? Add two decimal numbers 123 and 658 in XS Write short notes on different types and properties of four bit codes with the aid of suitable example. 24. Perform the subtraction with the following unsigned binary numbers by taking the 2 s complement of the subtrahend. A) B) C) D) The binary numbers listed have a sign bit in the left most position and if negative, are in 1 s complement form. Perform the arithmetic operations indicated and verify the answers. 26. Given the 8-bit data word , generate the 12 bit composite word for the hamming code that corrects and detects single errors. 27.Generate hamming code for a 4-bit excess-3 message to detect and correct single bit errors. BOOLEAN ALGEBRA AND SWITCHING FUNCTIONS: (a) Find the minimal expression for the function f(w,x,y,z)=p(0,2,5,9,15) +Pd (6,7,8,10,12,13) using Karnaughs-map. (b) i. Determine the Canonical sum-of-products form for T(x, y, z) = xy + z + xyz ii. Minimize the function f(x, y, z,w) = x + xyz + wx + xy + wx + xyz. [8+4+4] (R05,NOV 07,SET I) 2. (a) Simplify the following Boolean expressions. [8] i. A C + ABC + AC to three literals ii. (x y + z) + z + xy + wz to three literals iii. A B(D + C D) + B(A +A CD) to one literal iv. (A + C)(A + C )(A + B + C D) to four literals (b) Obtain the complement of the following Boolean expressions. [8] i. B C D + (B + C + D) + B C D E ii. AB + (AC) + (AB + C) iii. A B C + A?BC + AB C + ABC iv. AB + (AC) + AB C (R05,R07,RR,NOV 07,SET I,II) 3. (a) Simplify the function using Karnaugh map method F (A,B,C,D) = P(4,5,7,12,14,15)+ Pd(3,8,10). (b) Give three possible ways to express the function

3 F = A B D + A B C D + ABD + ABCD with eight or less literals. [8+8] 4. (a) Reduce the following Boolean Expressions [8] (R05,NOV 06) i. AB + A(B + C) + B (B + D) ii. A +B + A B C iii. A B + A BC + A BCD + A BC D E iv. ABEF + AB(EF) + (AB) EF (b) Obtain the Dual of the following Boolean expressions. [8] i. x yz + x yz + xy z + xy z ii. x yz + xy z + xyz + xyz iii. x z + x y + xy z + yz iv. x y z + x yz + xy z + xy z + xyz R05(NOV 06,SET I,IV) 5. (a) i. Simplify the Boolean Expression X[Y+Z[(XY + XZ)]. ii. Obtain the simplified expression in SOP form of x z + y z + yz + xyz. (b) Obtain the simplified expression in product of sums F(A, B, C,D) =P (5, 6, 7, 8, 9, 12, 13, 14,).[4+4+8] 6. i. Determine the Canonical sum-of-products form for T(x, y, z) = xy + z + xyz ii. Minimize the function f(x, y, z,w) = x + xyz + wx + xy + wx + xyz. [8+4+4] (R05,NOV 07,SET I) 7. (a) Simplify the following Boolean expressions. [8] i. A C + ABC + AC to three literals ii. (x y + z) + z + xy + wz to three literals iii. A B(D + C D) + B(A +A CD) to one literal iv. (A + C)(A + C )(A + B + C D) to four literals (b) Obtain the complement of the following Boolean expressions. [8] i. B C D + (B + C + D) + B C D E ii. AB + (AC) + (AB + C) iii. A B C + A?BC + AB C + ABC iv. AB + (AC) + AB C (R05,R07,RR,NOV 07,SET I,II) 8. (a) Simplify the function using Karnaugh map method F (A,B,C,D) = P(4,5,7,12,14,15)+ Pd(3,8,10). (b) Give three possible ways to express the function F = A B D + A B C D + ABD + ABCD with eight or less literals. [8+8] 9. (a) Reduce the following Boolean Expressions [8] (R05,NOV 06) i. AB + A(B + C) + B (B + D) ii. A +B + A B C iii. A B + A BC + A BCD + A BC D E iv. ABEF + AB(EF) + (AB) EF (b) Obtain the Dual of the following Boolean expressions. [8] i. x yz + x yz + xy z + xy z ii. x yz + xy z + xyz + xyz iii. x z + x y + xy z + yz iv. x y z + x yz + xy z + xy z + xyz 10. (a) i. Simplify the Boolean Expression X[Y+Z[(XY + XZ)]. ii. Obtain the simplified expression in SOP form of x z + y z + yz + xyz. (b) Obtain the simplified expression in product of sums F(A, B, C,D) =P (5, 6, 7, 8, 9, 12, 13, 14,).[4+4+8] (R 05,Nov 07,set I) 11. (a) For the given function find the min term designation and max term designation F = A'BC + ABC' + ABC + A'B'C (b) Write the Min terms and Max terms for the following functions F1= Σ(1,4,6,7,9) F2 = Π(3,5,7,11,14) [8+8 (R 05,Nov 07,set I) (NOV 06,SET I,IV) 12. Map the following function and simplify using K-Map (a) F = (A+B+C) (A+B'+C) (A+B'+C') (A'+B+C) (b) F = (A'BC'D' + A'BC'D + AB'CD + AB'CD' + ABCD + A'B'C'D') [16 (R05,Nov 08,set I) 13. (a) Simplify the following Boolean expressions. [8] i. A C + ABC + AC to three literals ii. (x y + z) + z + xy + wz to three literals iii. A B(D + C D) + B(A +A CD) to one literal iv. (A + C)(A + C )(A + B + C D) to four literals (b) Obtain the complement of the following Boolean expressions. [8] i. B C D + (B + C + D) + B C D E ii. AB + (AC) + (AB + C)

4 iii. A B C + A?BC + AB C + ABC iv. AB + (AC) + AB C (R07,Nov10,set III) 14. (a) Find the complement of the following and show that F.F?=0 and F+F =1. [8] i. F=xy +x y ii. F=(x+y +z)(x +z )(x+y) (b) Obtain the Dual of the following Boolean expressions. [8] i. B C D+(B+C+D) +B C D E ii. AB+(AC) +(AB+C) iii. A B C +A BC +AB C +ABC iv. AB+(AC) +AB C (RR,Nov 06,SET I) 15. (a) i. Simplify the Boolean Expression X[Y+Z[(XY + XZ)]. ii. Obtain the simplified expression in SOP form of x z + y z + yz + xyz. (b) Obtain the simplified expression in product of sums F(A, B, C,D) =P (5, 6, 7, 8, 9, 12, 13, 14,)[4+4+8] (R05,Nov08,set III) 16. (a) Reduce the following Boolean Expressions [8] i. AB + A(B + C) + B (B + D) ii. A +B + A B C iii. A B + A BC + A BCD + A BC D E iv. ABEF + AB(EF) + (AB) EF (b) Obtain the Dual of the following Boolean expressions. [8] i. x yz + x yz + xy z + xy z ii. x yz + xy z + xyz + xyz iii. x z + x y + xy z + yz iv. x y z + x yz + xy z + xy z + xyz 17. a) Simplify the following Boolean functions to minimum number of literals. i) XYXYZ ++ ii) A BAB b) State Duality theorem. List Boolean laws and their duals. [8+8] 18. a)obtain the simplified expression in product of sums F(A, B, C,D) =P (5, 6, 7, 8, 9, 12, 13, 14,). [16] b)obtain the simplified expression in SOP form of x z + y z + yz + xyz.[8] 19. Obtain the complement of the following Boolean expression. a) B C D + (B+C+D) +B C D E b) AB+(AC) +(AB+C) c) A B C+A BC +AB C+ABC. 20. Realize the following circuits using AND, OR, NOT gates. 21. simplify the following Boolean functions to minimum number of literals. (i) F = ABC+ABC +A B (ii) F= y(w(z +z)+xy (iii) F = A B C+ A BC+AB C+ABC. 22. Implement the following Boolean function using only NAND gates. (i) B+ACD+BC (ii) F = A B +A C+B C. 23. Simplify the following Boolean expression (i) A C +ABC+AC to THREE literals (ii) A B(D +C D)+B(A+A CD) to ONE literal. 24. State duality theorem. List Boolean laws and their duals. 25.state and prove the following Boolean laws: i) Commutative ii) Associative iii) Distributive. 26. a) Realize XOR gate using minimum number of NAND gates. b) Prove that AND-OR network is equivalent to NAND-NAND network. UNIT II MINIMIZATION OF SWITCHING FUNCTIONS 1. Using K-map Simplify f(x1, x2, x3, x4, x5, x6) = Pm (0, 3, 4, 5, 7, 8, 12, 13, 20, 21, 28, 29, 31, 34,35, 38, 39,42, 45, 46, 50, 54, 58, 61, 62, 63) [16m] R05 NOV 07,08,,SET I

5 2. Apply Branching method to simplify the following function F (A, B, C, D) =QM(0, 1, 4, 5, 9, 11, 13, 15, 16, 17, 25, 27, 28, 29, 31)d(20, 21, 22, 30). [ [16]R07 May10,Set Map the following function and simplify using K-Map (a) F = (A+B+C) (A+B'+C) (A+B'+C') (A'+B+C) (b) F = (A'BC'D' + A'BC'D + AB'CD + AB'CD' + ABCD + A'B'C'D') [16] RR NOV06,SET II 4. Use tabular procedure to simplify the given expression f(v,w,x,y,z) =Pm(0,4,12,16,19,24,27,28,29,31) in SOP form and draw the circuit using only NAND gates. [16]R05 NOV 06,SET I 5. (a) Simplify the Boolean expression using K-map F= (ABC D)+(A)+(AB D)+(D )( A B C ). [8] (b) Reduce the following function using K- map and identify the prime implicant and non prime implicant.f= Pm(2, 3, 6, 7, 10, 11, 12). [8] NR NOV 05 6.(a) Implement the following function using only NOR gates F=a.(b+ c.d) + (b. c) (b) Implement the following function using only NAND gates G=(a + b). (c. d+ e ) (c) Give the minimum two-level SOP realization of the following switching function using only NAND gates. F(x,y,z) = P m (0,3,4,5,7) [4+4+8]NR NOV 02 SET I 7. Derive the implicant chart for the given expression Is the prime-implicant chart cyclic? Apply the suitable method to find the minimal expression. NR NOV 02 SET II 8. a) Use a Karnaughs map to minimize. _ F = A B C D + A B C D + AB C D + A BCD + ABD + B CD + A B C D NR NOV 02 SET III 9. (i)simplify the logic function f = AB + A C + C + AD + A B C + ABC ii)simplify Boolean function F = A C + A B + AB C + BC 10. (i)find the Complement of the function Y=(A+BC) (B+CA) in its POS form ii)minimise the function using Karnaugh s map method m 11. Determine the canonical Product of sum form for the function and simplify using k-map (a) Y(x,y,z) = x(y'+z) (b) Y(a,b,c) = ab' + bc (c) Y(w,x,y,z) = wxy' + x(y'+z) (d) Y(a,b,c) = (ab + c')(ac + b') NR NOV 02 SETIV 09 R05 [16 ] MAY 07 R05 12.(a) Design a logic circuit to provide an output when any two or three or four switches are closed. (b) Minimize the following Boolean function using K-map F = Π (2, 7, 8, 9, 10, 12). [8+8] NOV07 R07 6. Design a combinational logic circuit with 4 inputs A, B, C, D. The output Y goes HIGH if and only if B and C inputs go HIGH. Draw the Truth table. Minimize the Boolean function using K-map. Draw the circuit diagram. [16]JAN 03 OR 13. Explain the type of Hazard if any in the EXCLUSIVE - OR circuit made by five NAND gates and the EXCLUSIVE?OR circuit made by four NAND gates as shown in figure BELOW. [ 16]NOV 09, MECH R09, III/I SEM. 14.a) State Duality theorem. List Boolean laws and their Duals. b) Simplify the following Boolean functions to minimum number of literals: a) xy + xy b) (x + y)(x+y ). c) Realize XOR gate using minimum number of NAND gates. [8+4+4] NOV 07 R07 15.a) State the purpose of reducing the switching functions to minimal form. b) Write the Dual of i) (A+BC +AB) ii) (AB+B C+CD)

6 c) Give the truth table for the Boolean expression (X +Y) [4+8+4] JAN 10 RR 16. (a) Derive Boolean expression for a 2 input Ex-NOR gate realized with two input NOR gates, without using complemented variables and draw the circuit. (b) Redraw the given circuit (_gure5b) after simpli_cation. [8+8] APR 08,R05 17.(a) For the given function find the min term designation and max term designation F = A'BC + ABC' + ABC + A'B'C (b) Write the Min terms and Max terms for the following functions F1= Σ(1,4,6,7,9) F2 = Π(3,5,7,11,14) [8+8] NOV R09 MECH 18. Apply Branching method to simplify the following function [16] F (A, B, C, D) =QM(0, 1, 4, 5, 9, 11, 13, 15, 16, 17, 25, 27, 28, 29, 31)d(20, 21, 22, 30). MAY 10 R Minimize the the following multiple output functions. f1 = Pm(0, 2, 6, 10, 11, 12, 13) + d(3, 4, 5, 14, 15) f2 = Pm(1, 2, 6, 7, 8, 13, 14, 15) + d(3, 5, 12). [16]NOV 09 RR 20. Give three possible ways to express the function F = A B D + A B C D + ABD + ABCD with eight or less literals. [16]MAY 03 RR ECE, EIE 21 a) Determine the minimal sum of product form of [8+8] i) f(w, x, y, z) = Σm(4, 5, 7, 12, 14, 15) + Ø(3, 8, 10). ii) f(a, B, C, D) = πm(0, 3, 5, 6, 8, 12, 15). JAN 03 OR 22 a) Simplify the following Boolean functions to minimum number of literals. (i) X +Y +XYZ (ii) (A+B) (A+B) b) State Duality theorem. List Boolean laws and their duals. [8+8] 23.a) Draw a logic diagram using only two-input NAND gates to implement the following expression: (AB + A'B') (CD' + C'D) [8+8] b)derive the circuits for a three-bit parity generator and four-bit parity checker using odd parity bit. 24..Simplify the following Boolean expressions and implement by using only NAND gates. (i) Y AABAB ( )( B ) [8+8] (ii) Z ( ABACB () () C ) 25.State the basic laws of Boolean algebra and explain. [16] Unit III COMBINATIONAL LOGIC DESIGN 1. a) Differentiate synchronous and asynchronous circuits. ( R07,R05 JUN2010, Set-2),RR SET II,IV b) Design a 2 to 4 decoder using NAND gates. [8+8]( R05 JUN2010, Set-2) 2.a) What is Encoder? Design decimal to BCD Encoder. b) Explain how a decoder can be converted in to a demultiplexer with relevant block diagrams and truth tables. [10+6] RR JUN10 SET 4 3. a) What is decoder? Construct 3*8 decoder using logic gates and truth table. b) Implement full adder using decoder and OR gates. [8+8]RR,R05,R07 JUN 07,MAY a) Design a converter circuit which converts 8,4,2,-1 code to 8,4,2,1 code b) Implement a Full adder using decoder and logic gates [8+8]RR,R05 JUN,05,10 SET 1,4 5.List the applications of Multiplexer and Demultiplexer. [8]RR,R05 NOV,05,06, SET 6.Write short notes on any Three: SOP and POS forms. PLA and PAL. RAM, ROM, EPROM and E 2 PROM. Multiplexer and decoder Nov 09 R05 MECH,EIE

7 8.a) List the advantages of synchronous counters over ripple counters. b)using a shift register and a combinational logic circuit, design a sequence generator which will generate the binary seque RO7 MAY 10 OR APR 04 9.a)Draw the block diagram of BCD Adder and explain its operation. b)explain the construction of a Johnson counter. R05 APR 08,OR,NR MAY 02, Implement Full adder circuit using ROM and Verify the working. (i) (JUN2010, Set-2) Unit IV SEQUENTIAL CIRCUITS-I (ii) (JUN2010, Set-2) (iii) (JUN2010, Set-2) (iv) (JUN2010, Set-4) (v) (JUN2010, Set-4) (R 07 JUN2010, Set-1) 6. a) Differentiate Latch and flip-flop. Explain the construction of S-R Latch. b) Construct a D-Latch and explain its operation. [8+8] (R 07 JUN2010, Set-2) 7. a) Differentiate edge triggering, Level triggering and Pulse triggering. b) Design a clocked JK flip flop. Explain its operation with the help of characteristic table and characteristic equation. Give the symbol of edge triggered JK flipflop. [8+8]

8 (RRJUN05, Set-2) 8. a) Design a 4-bit Bidirectional Shift Register. b) Convert D flip op to T flip flop. [8+8] (RR JUN 10) 9.a) Explain the operation of a master-slave JK flip flop in each clock cycle over a period of six consecutive clocks. b) Explain the operation of a Johnson counter with neat diagram. [16] 10. a) Draw the logic, diagram of a JK flip flop and using excitation table, explain its operation. b) Explain the operations of a 4-bit synchronous binary counter with neat diagram. [8+8] 11 a) Give the excitation tables of all flip flops and explain. b) Convert D flip flop in to T, JK and SR flip flop. [8+8] 12 a) What is the basic difference between a pulse mode and level mode circuits. b) Draw a neat circuit diagram of positive edge trigged JK flip flop and explain. [8+8] 13. (a) Compare synchronous & Asynchronous circuits (b) Design a Mod-6 synchronous counter using J-K flip flops. [6+10] (R07 JUN2010, Set-2) 14.a) Define state diagram. Explain the procedure to reduce the state diagram. b) For the state diagram shown, obtain the state table and design the circuit using minimum number of JK Flip Flops. (R05 APR 08) 15.a) Design a BCD counter with JK flip flops. b) Draw the diagram of a 4-bit Binary ripple counter using flip flops that trigger on the positive edge.16] Unit V : PROGRAMMABLE LOGIC DEVICES 1.Give the circuit implementation of a 4-bit carry look aheader carry? b) Give the implementation of a 2-bit magnitude comparator? c)bring out the differences among PAL and PLA? 2.a) Write in detail about types of Read only memories. b) Write in detail to program a ROM to implement Boolean functions. [8+8] ( R07 JUN2010, Set-2,4) 3.Write about Programmable Array Logic. Mention the advantages of Programmable Array logic. Represent the conventional symbol and array logic symbol of PAL. Give the internal connections of PAL. [16](R07JUN2010 Set-4] 4. Implement the following functions using PAL and PLA F1 = m (2,3,4,7,8,11) Σ F2 = m (1,3,5,7,9,11,13,15) [16]MAY 03 (ECE & EIE) 5. a) Generate a PLA program table to design a BCD to excess 3 code converter. b) Write brief note o n multi gate synthesis of threshold logic. [8+8] RR JUN 10,R05 JUN 10,RR NOV 09,R05 NOV a) Write a note on PROM, PAL and PLA architecture. b) Implement a full sub tractor using ROM[8+8] RR JUN 10,R05 JUN 10,RR,R05 NOV Derive the PLA programming table for the combinational circuit that squaresa 3 bit number. [16]

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