2 nd Year Laboratory. Experiment: FPGA Design with Verilog. Department of Electrical & Electronic Engineering. Imperial College London.

Size: px
Start display at page:

Download "2 nd Year Laboratory. Experiment: FPGA Design with Verilog. Department of Electrical & Electronic Engineering. Imperial College London."

Transcription

1 Department of Electrical & Electronic Engineering 2 nd Year Laboratory Experiment: FPGA Design with Verilog Objectives By the end of this experiment, you should know: How to design digital circuits using Altera s Quartus II Design Suite; How to design digital circuits targeting Altera s Cyclone III FPGA using a Terasic s DE0 Board; How to design digital circuits in efficient Verilog HDL; How to evaluate your design in terms of resource utilization and clock speed; How to use DE0 FPGA board with its custom daughter board for I/O functions such as ADC and DAC; Have designed something yourself for the Cyclone III FPGA. Both the experimental board and a PC would be made available to you during your allotted period in the second year laboratory. In addition, you may also borrow a DE0 board to take home to use for the rest of the second year. This instruction sheet is divided into four part, one for each week. It also provides you with information required to install Altera s Quartus II Design Suite (web free- version) on your own personal computer (PC or Mac). v1.2 - PYK Cheung, 20 Jan

2 PART I 1.0 Introduction This experiment is designed to support the second year course on digital electronics as part of the second year electronics lab. Due to the limitation of scheduling, this experiment will NOT be synchronized with the lectures or tutorial problem sheets. However, you are encouraged to borrow a DE0 Board from the stores and conduct this experiment at home in your own time if you so choose. All materials relating to this experiment can be found on the following experiment webpage: Background Reading You should have done some background reading before attending the laboratory session as suggested at the Lecture. 1.2 FPGAs FPGAs is a type of programmable logic devices introduced by Xilinx in It is now the predominant technology for implementing digital logic in low to moderate volume production. The basic structure of an FPGA is shown below. It consists of three main types of resources: 1) Logic Blocks (or Elements); 2) Routing Resources; 3) I/O Pad. For more information about FPGA, see Lecture 2 notes available on the E2 Digital Electronics course webpage. 1.3 Quartus II Design Suite Quartus II provides a complete environment for you to implement your design on an Altera FPGA. It supports all aspects of the design flow, which is typically following the flow diagram shown here. The best way to learn Quartus is to go through this experiment step- by- step. After you have learned the basics, you can start to explore other aspects of the Quartus system. 1.3 DE0 Board DE0 Board is designed and made by Terasic. It is based around a Cyclone III FPGA from Altera. Include on the DE0 board are various I/O devices such as 7- segment LED displays, LED, switches, VGA port, RS232 port, SD card slot etc. A block diagram of the DE0 board is shown below. v1.2 - PYK Cheung, 20 Jan

3 1.4 Verilog Hardware Description Language One of the key purposes of this lab experiment is to encourage you to learn the Verilog Hardware Description Language (HDL), which is the preferred and common means of specifying a FPGA design. You are expected to have learned the basics of the Verilog language before doing this experiment. If you happen to be schedule to do this experiment at the beginning of the term, you would need to teach yourself Verilog by reading my Lecture notes 3A and 3B and/or online tutorials. An excellent tutorial can be found on: world.com/verilog/veritut.html. A Verilog Syntax Summary sheet is provided in Appendix A. 1.5 Using Quartus II software and DE0 at home You are encourage to install a copy of the Quartus II software on your own computer and borrow a DE0 board (from EEE Stores with your ID card), so that you are not restricted to working in the Level 1 Lab. The version that comes with the DE0 board is version 9.0, which is already a few years old. You should go to Altera s website to register yourself, then download the free Web Edition from: Note that Quartus II and DE0 board will work with Windows XP/Windows 7/Windows 8, or Linux. If you are a Mac user, you would need to run a virtual machine (e.g. VirtualBox, Parallels or VMware), load a version of Windows or Linux, and then run Quartus under that environment. Plug the DE0 board to a USB port on your computer and turn it ON (red button). It will ask you for a device driver, which can be found in the Quartus software directory.\drivers. See Getting Started with Altera DE0 board manual. Copy from the DVD the directory \DE0\Contro_panel to your computer (best at the same directory as the Quartus software). Run DE0_ControlPanel.exe and check that the DE0 board is working properly 1. It allows you to test most of the functions on DE0 with an easy- to- use interface. PART I Experiment 1: Schematic capture using Quartus II 7- Segment Display Part I of the experiment should take no more than ONE 3- hour session. It will lead you through the entire design of a 7- segment decoder using schematic entry method. It will use switches 3-0 on the DE0 board as input, and display the 4- bit binary number as a hexadecimal digit on the right- most 7- segment display (HEX0). Step 1: See what you are aiming for Go to the Experiment webpage (see above) and download a copy of the solution for Experiment 1: My7Seg.sof onto your home directory (wherever that is). Now turn ON the DE0 board. 1 You needed to add "C:\altera\13.1\quartus\bin" to your search path a known problem. v1.2 - PYK Cheung, 20 Jan

4 Step 2: Programme the FPGA Start up Quartus II software on your computer. Click command: Tools > Programmer. In the popup window, click: Hardware Setup. You should see something like the diagram below. Then select: USB- Blaster. This is to tell Quartus software that you are using the DE0 USB interface to program (or blast) the FPGA. Then click Add File. specify the.sof file you have downloaded from your home directory. Click: Start. This shows you what you are aiming for: use the lower 4- bit of the slide switches to specify a 4- bit hex number, which is decoded to drive a 7- segment LED display. Step 3: Paper Design Designed a 7- segment decoder on paper. The overall block diagram for the decoder is shown below. The decoder outputs out[6..0] drive the seven segments [6..0] respectively. Note that the LED segments are low active, meaning that the LED will light up if the corresponding input is drive by a logical 0. The truth- table for the decoder is: v1.2 - PYK Cheung, 20 Jan

5 Your design should be in the form of 7 Boolean equations in sum- of- product form. Simplify where possible. Step 4: Create the project My7Seg Create in your home directory the folder Ex1a. Click file>new Project Wizard, complete the form. Use the same project name and top- design name. Select the FPGA device as Cyclone III EP3C16F484C6. Then click Finish. Create the top- level module My7Seg by: Click File > New.. There will be an empty schematic window. Click File > Save As enter the name My7Seg. Step 5: Specify the 7- segment decoder as schematic In order to save time in the Lab, you are provided with an incomplete version of the 7- segment display decoder. Go to the Experiment webpage and download: 7_Segment_Decoder_incompete.bdf. Rename it to 7_Segment_Decoder.bdf. This partially completed design has the logic that drives out[4] missing. You job is to design and enter the schematic to drive out[4] from in[3:0]. The diagram here shows one possible implementation. Your design may be different. The Graphic Editor provides a number of libraries which include circuit elements that can be imported into a schematic. Double- click on the blank space in the Graphic Editor window, or click on the icon in the toolbar that looks like an AND gate. A pop- up box will appear. Expand the hierarchy in the Libraries box as shown in the figure. First expand libraries, then expand the library primitives, followed by expanding the library logic which comprises the logic gates. Select and2, which is a two- input AND gate, and click OK. Now, the AND symbol will appear in the Graphic Editor window. Using the mouse, move the symbol to a desirable location and click to place it there. Repeat and place two and3 and one or3 gates on the schematic. Change the names of all the input and output nodes accordingly. (It is quickest to put down all the gates first before wiring them up later.) Having entered the logic- gate symbols, it is now necessary to enter the symbols that represent the input and output ports of the circuit. Use the same procedure as for importing the gates, but choose the port symbols from the library primitives/pin. Import one instance of the input port and one instance of the output port. Label the input port as in[3:0] and output port as out[6:0]. Grouping input and output ports as busses will make wiring much easier. Assign names to the input and output symbols as follows. Make sure nothing is selected by clicking on an empty spot in the Graphic Editor window. Point to the word pin_name on the top input symbol and double- click the mouse. The dialog box will appear. Type the pin name, in[0], and click OK. Similarly, assign the names in[3..1] to the other input ports and out[4] to the output port. Alternatively, it is v1.2 - PYK Cheung, 20 Jan

6 possible to change the name of an element by selecting it first, and then double- clicking on the name and typing a new one directly. You are now ready to wire up the gates. Click on the icon in the toolbar to activate the Orthogonal Node Tool. Position the mouse pointer over the right edge of the input pin. Click and hold the mouse button and drag the mouse to the right until the drawn line reaches the pinstub of the gate. Release the mouse button, which leaves the line connecting the two pinstubs. Note that a dot will appear indicating a connection between the two wires. All nodes with the same name will be connected. Having completed the circuit for out[4], you now need to do the same for the other six outputs. Step 6: Include this file in project Checkpoint: You should get to this point at after 1 to 1.5 hours. Every time you create a new entity or module as part of your design, you must include the file in the project. Click: Project > Add Current Files to Project., Step 7: Make a symbol for the decoder It is often convenient to encapsulate a circuit into a module, which is then used multiple times in a design. This is called an entity. For us to do so, we need to create a symbol for it. (This will create a 7_Segment_Decoder.bsf file.) Click File > Creat/Update > Create Symbol Step 8: Use this module at the top- level design schematic Open My7Seg, the empty top- level design entry file. Use the button to place the 7_Segment_Decoder module, input port and output port on the schematic. Double click the port symbol to edit the Pin Property, and enter the input and output names as SW[3..0] and HEX0_D[6..0] respectively. Use the bus wiring tool to wire up the ports to the module as two busses as shown below. Save this file. v1.2 - PYK Cheung, 20 Jan

7 Step 9: Pin assignment & Compilation You need to associate your design with the physical pins of the Cyclone III FPGA on the DE0 board. First specify the device by clicking: Assignments > Device Select Cyclone III EP3C16F484C6 (check that this is indeed the chip on the DE0 board). Click: Processing > Start > Start Analysis and Elaboration. This will work out the input/output port names for your design. This should complete without error. Otherwise, fix all errors and re- analyse. Click Assignment > Pin Planner and a new window with the chip package diagram. You should also see the top- level input/output ports shown as a list. Click on the appropriate pins one by one, and select the corresponding port (node name) according to the list shown below. The I/O standard (i.e. interface voltages) should be 3.3V LVTTL. Click: Processing > Start Compilation, to build the entire design, and to generate all the necessary files. There should be NO error, but some warnings. Step 10: Program the FPGA on the DE0 Board Program the DE0 board with your version of My7seg.sof and test that it is working properly. Congratulations! You have now completed your first FPGA design! v1.2 - PYK Cheung, 20 Jan

8 Step 11: Propagation Delay from inputs to outputs Click: Tools > TimeQuest Timing Analyzer to invoke the built in timing analyzer of Quartus II. A new TimeQuest window will appear. Click: Netlist > Create Timing Netlist. Then select post- fit and slow- corner, then OK. Now click: Netlist > Set Operating Conditions Then choose the slow model at 0. Now click: Netlist > Update Timing Netlist This will use the specified timing model and condition to produce a set of timing data. Click: Report > Datasheet > Report Datasheet. This will produce a table showing the input- to- output propagation delay for various combination of rise and fall times (RR, RF, FR and FF). Explore this to find out the worst- case propagation delay for your circuit. Then delete this timing netlist, and redo it again choosing 80 as the operating temperature. What is the delay difference at these two temperature extremes? Step 12: Examine the resources used We now examine how Quartus has compiled your specification (from schematic) to actual FPGA hardware. In the Compilation Report window, you should have seen that your design used 7 logic elements. Let us make sure that the FPGA implementation of out[4] is identical to your specification. Click: Tools > Netlist Viewers > Technology Map Viewer (Post- fitting). Then push down into the 7_Segment_Decorder module. You should see 7 instances of the logic element. Identify which Logic Element (LE) provides out[4]. Hover the mouse pointer to this LE (corresponding to out[4]), you should see a pop- up window with the Boolean equation of the FPGA implementation. (Note that in Quartus, & = AND, # = OR, $ = XOR,! = NOT.) Right click the symbol and select properties in the pop- up window. You will see the schematic equivalent of the Boolean equation: Check that this performs the same logic function as that specified in your schematic out[4]. (Don t trace for any other outputs.) In general, you do no need to worry about exactly how Quartus implements your logic. The synthesis software should provide a design that exactly matches your specification. v1.2 - PYK Cheung, 20 Jan

9 Experiment 2: 7- Segment decoder in Verilog HDL I hope you now appreciate how limiting and slow it is to enter a design as a schematic diagram. Modern digital designs DO NOT USE schematic as a method of entry any more. Instead a designer would either use Verilog or VHDL hardware description language to specify the design. By the end of this laboratory session, you should be convinced about the superiority of using a HDL over schematic capture. Step 1: hex_to_7seg.v Create a new project Ex2a as before, with a top- level schematic module as before. You may call it Ex2a_Decoder. In Quartus II, create a design file in Verilog HDL known as hex_to_7seg.v. The actual code is given to you in Lecture 3A slide 18 and is repeated here. A full compilation can take a long time. A far more efficient way to check the syntax of your code by clicking: Process > Analyze current file. After you verify that the current file has no syntax error, you may then check that it is consistent with other files in your design by clicking: Process > Start > Start analysis & elaboration. Step 2: Create a SYMBOL for this Verilog module Click: File > Create/Update > Create Symbol file. Step 3: Create the top- level schematic file Similar to last exercise, insert the symbol for the module hex_to_7seg in your new schematic file Ex2a_Decoder.bdf. Add input ports SW[3..0] and output ports HEX0_D[6..0], and connect to your decoder module. Beware of the difference in Quartus method in specifying a bus. It uses SW[3..0], which is different from Verilog using SW[3:0]. Compile the whole design. You should find that this design works as before. v1.2 - PYK Cheung, 20 Jan

10 Step 4: Pin Assignment the quick way Earlier you used the pin assignment editor to associate pins on the package to your signals. This is a tedious process. In Ex1, if you have correctly completed the design, the pin assignment would have been stored in a file: My7Seg.qsf file. Open this file, either using Quartus built- in editor by clicking: File > Open file or use your own favourite edit on your PC. You will find lines of statement such as: The first line defines the voltage standard used by the SW[3] signal. The second line defines the pin location of SW[3] is PIN G4. Now open the.qsf file for your current design, and copy & paste the assignments from Ex1 across. You will find that this is the easiest way to deal with PIN assignment with minimal chance of introducing an error. Step 5: Test your design Recompile your design, load your configuration to the DE0 board using: Tool > Programmer command. Test your design on the DE0 board. Step 6: Do everything in Verilog including Top- Level Specification It is in fact much easier to eliminate all needs for schematic capture. You can replace the top level schematic file Ex2a_Decoder.bdf with Ex2a_Decoder.v. Create this top level Verilog file as shown here. Click: Project > Add/Remove Files, and remove the.bdf file as part of this project. This allows you to remove the.bdf file and replace it with the.v file for the top- level specification. Compile and test. Step 7: Do this yourself Now complete this exercise but including the remaining switches and three of the four 7- segment LED display. You should find that doing so is much easier in Verilog than using schematics. You can find the pin assignment given in the file pin_assignment.txt (downloadable from the experiment webpage). Adding this to the.qsf file using a text editor is much easier than editing each pin one at a time. Checkpoint: You should get to this point by the end of the Lab Session. v1.2 - PYK Cheung, 20 Jan

11 Pin Assignments for the 4 HEX displays and 13 switches on DE0 board v1.2 - PYK Cheung, 20 Jan

Experiment VERI: FPGA Design with Verilog (Part 1)

Experiment VERI: FPGA Design with Verilog (Part 1) Experiment VERI: Department of Electrical & Electronic Engineering 2nd Year Laboratory Experiment VERI: FPGA Design with Verilog (Part 1) (webpage: www.ee.ic.ac.uk/pcheung/teaching/e2_experiment /) Objectives

More information

Laboratory Experiment Mastering Digital Design

Laboratory Experiment Mastering Digital Design MSc Course on Analogue and Digital IC Design Laboratory Experiment Mastering Digital Design (webpage: http://www.ee.ic.ac.uk/pcheung/teaching/msc_experiment/) This Laboratory Experiment is intended to

More information

EXPERIMENT VERI Digital Design with FPGA and Verilog

EXPERIMENT VERI Digital Design with FPGA and Verilog EXPERIMENT VERI Digital Design with FPGA and Verilog 14 th November 9 th December 2016 V4.0 - PYK Cheung, 11 Nov 2016 Experiment VERI: FPGA and Verilog Department of EEE Department of Electrical & Electronic

More information

EXPERIMENT VERI Digital Design with FPGA and Verilog

EXPERIMENT VERI Digital Design with FPGA and Verilog EXPERIMENT VERI Digital Design with FPGA and Verilog 12 th November 7 th December 2018 V4.2 - PYK Cheung, 7 Nov 2018 Experiment VERI: FPGA and Verilog Department of EEE Department of Electrical & Electronic

More information

Tutorial for Altera DE1 and Quartus II

Tutorial for Altera DE1 and Quartus II Tutorial for Altera DE1 and Quartus II Qin-Zhong Ye December, 2013 This tutorial teaches you the basic steps to use Quartus II version 13.0 to program Altera s FPGA, Cyclone II EP2C20 on the Development

More information

Tutorial on Quartus II Introduction Using Schematic Designs

Tutorial on Quartus II Introduction Using Schematic Designs Tutorial on Quartus II Introduction Using Schematic Designs (Version 15) 1 Introduction This tutorial presents an introduction to the Quartus II CAD system. It gives a general overview of a typical CAD

More information

Experiment VERI: FPGA Design with Verilog (Part 2) (webpage: /)

Experiment VERI: FPGA Design with Verilog (Part 2) (webpage:   /) Department of Electrical & Electronic Engineering 2 nd Year Laboratory Experiment VERI: FPGA Design with Verilog (Part 2) (webpage: www.ee.ic.ac.uk/pcheung/teaching/e2_experiment /) 1.0 Learning Outcomes

More information

structure syntax different levels of abstraction

structure syntax different levels of abstraction This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital

More information

Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this

Here is a list of lecture objectives. They are provided for you to reflect on what you are supposed to learn, rather than an introduction to this This and the next lectures are about Verilog HDL, which, together with another language VHDL, are the most popular hardware languages used in industry. Verilog is only a tool; this course is about digital

More information

ECSE-323 Digital System Design. Lab #1 Using the Altera Quartus II Software Fall 2008

ECSE-323 Digital System Design. Lab #1 Using the Altera Quartus II Software Fall 2008 1 ECSE-323 Digital System Design Lab #1 Using the Altera Quartus II Software Fall 2008 2 Introduction. In this lab you will learn the basics of the Altera Quartus II FPGA design software through following

More information

Terasic DE0 Field Programmable Gate Array (FPGA) Development Board

Terasic DE0 Field Programmable Gate Array (FPGA) Development Board Lecture FPGA-01 DE0 FPGA Development Board and Quartus II 9.1 FPGA Design Software Terasic DE0 Field Programmable Gate Array (FPGA) Development Board 1 May 16, 2013 3 Layout and Components of DE0 May 16,

More information

NIOS CPU Based Embedded Computer System on Programmable Chip

NIOS CPU Based Embedded Computer System on Programmable Chip 1 Objectives NIOS CPU Based Embedded Computer System on Programmable Chip EE8205: Embedded Computer Systems This lab has been constructed to introduce the development of dedicated embedded system based

More information

UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180A DIGITAL SYSTEMS I Winter 2015

UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180A DIGITAL SYSTEMS I Winter 2015 UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180A DIGITAL SYSTEMS I Winter 2015 LAB 1: Introduction to Quartus II Schematic Capture and ModelSim Simulation This

More information

Quartus II Introduction Using Schematic Design

Quartus II Introduction Using Schematic Design Quartus II Introduction Using Schematic Design This tutorial presents an introduction to the Quartus R II CAD system. It gives a general overview of a typical CAD flow for designing circuits that are implemented

More information

EMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 6: Quartus II Tutorial and Practice. Name: Date:

EMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 6: Quartus II Tutorial and Practice. Name: Date: EXPERIMENT # 6: Quartus II Tutorial and Practice Name: Date: Equipment/Parts Needed: Quartus II R Web Edition V9.1 SP2 software by Altera Corporation USB drive to save your files Objective: Learn how to

More information

Introduction to VHDL Design on Quartus II and DE2 Board

Introduction to VHDL Design on Quartus II and DE2 Board ECP3116 Digital Computer Design Lab Experiment Duration: 3 hours Introduction to VHDL Design on Quartus II and DE2 Board Objective To learn how to create projects using Quartus II, design circuits and

More information

FPGA Introductory Tutorial: Part 1

FPGA Introductory Tutorial: Part 1 FPGA Introductory Tutorial: Part 1 This tutorial is designed to assist in learning the basics of the Altera Quartus II v9.0 software. Part 1 of the tutorial will cover the basics of creating a Project,

More information

NIOS CPU Based Embedded Computer System on Programmable Chip

NIOS CPU Based Embedded Computer System on Programmable Chip NIOS CPU Based Embedded Computer System on Programmable Chip EE8205: Embedded Computer Systems NIOS-II SoPC: PART-II 1 Introduction This lab has been constructed to introduce the development of dedicated

More information

EXPERIMENT 1. INTRODUCTION TO ALTERA

EXPERIMENT 1. INTRODUCTION TO ALTERA EXPERIMENT 1. INTRODUCTION TO ALTERA I. Introduction I.I Objectives In this experiment, you will learn computer aided digital design and verification of it using Field Programmable Gate Arrays (FPGA).

More information

Quick Tutorial for Quartus II & ModelSim Altera

Quick Tutorial for Quartus II & ModelSim Altera Quick Tutorial for Quartus II & ModelSim Altera By Ziqiang Patrick Huang Hudson 213c Ziqiang.huang@duke.edu Download & Installation For Windows or Linux users : Download Quartus II Web Edition v13.0 (ModelSim

More information

The QR code here provides a shortcut to go to the course webpage.

The QR code here provides a shortcut to go to the course webpage. Welcome to this MSc Lab Experiment. All my teaching materials for this Lab-based module are also available on the webpage: www.ee.ic.ac.uk/pcheung/teaching/msc_experiment/ The QR code here provides a shortcut

More information

University of Florida EEL 3701 Dr. Eric M. Schwartz Madison Emas, TA Department of Electrical & Computer Engineering Revision 1 5-Jun-17

University of Florida EEL 3701 Dr. Eric M. Schwartz Madison Emas, TA Department of Electrical & Computer Engineering Revision 1 5-Jun-17 Page 1/14 Example Problem Given the logic equation Y = A*/B + /C, implement this equation using a two input AND gate, a two input OR gate and two inverters under the Quartus environment. Upon completion

More information

Tutorial on Quartus II Introduction Using Verilog Code

Tutorial on Quartus II Introduction Using Verilog Code Tutorial on Quartus II Introduction Using Verilog Code (Version 15) 1 Introduction This tutorial presents an introduction to the Quartus II CAD system. It gives a general overview of a typical CAD flow

More information

University of Florida EEL 3701 Dr. Eric M. Schwartz Department of Electrical & Computer Engineering Revision 0 12-Jun-16

University of Florida EEL 3701 Dr. Eric M. Schwartz Department of Electrical & Computer Engineering Revision 0 12-Jun-16 Page 1/14 Quartus Tutorial with Basic Graphical Gate Entry and Simulation Example Problem Given the logic equation Y = A*/B + /C, implement this equation using a two input AND gate, a two input OR gate

More information

Chapter 2 Getting Hands on Altera Quartus II Software

Chapter 2 Getting Hands on Altera Quartus II Software Chapter 2 Getting Hands on Altera Quartus II Software Contents 2.1 Installation of Software... 20 2.2 Setting Up of License... 21 2.3 Creation of First Embedded System Project... 22 2.4 Project Building

More information

PRELAB! Read the entire lab, and complete the prelab questions (Q1- Q3) on the answer sheet before coming to the laboratory.

PRELAB! Read the entire lab, and complete the prelab questions (Q1- Q3) on the answer sheet before coming to the laboratory. PRELAB! Read the entire lab, and complete the prelab questions (Q1- Q3) on the answer sheet before coming to the laboratory. 1.0 Objectives In this lab you will get familiar with the concept of using the

More information

EMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 7: VHDL and DE2 Board. Name: Date:

EMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 7: VHDL and DE2 Board. Name: Date: EXPERIMENT # 7: VHDL and DE2 Board Name: Date: Equipment/Parts Needed: Quartus II R Web Edition V9.1 SP2 software by Altera Corporation USB drive to save your files Objective: Learn how to create and modify

More information

UNIVERSITI MALAYSIA PERLIS

UNIVERSITI MALAYSIA PERLIS UNIVERSITI MALAYSIA PERLIS SCHOOL OF COMPUTER & COMMUNICATIONS ENGINEERING EKT 124 LABORATORY MODULE INTRODUCTION TO QUARTUS II DESIGN SOFTWARE : INTRODUCTION TO QUARTUS II DESIGN SOFTWARE OBJECTIVES To

More information

Lab 2 EECE473 Computer Organization & Architecture University of Maine

Lab 2 EECE473 Computer Organization & Architecture University of Maine Lab 2: Verilog Programming Instructor: Yifeng Zhu 50 Points Objectives: 1. Quatus II Programming assignment: PIN assignments, LEDs, switches; 2. Download and test the design on Altera DE2 board 3. Create

More information

E85: Digital Design and Computer Engineering Lab 2: FPGA Tools and Combinatorial Logic Design

E85: Digital Design and Computer Engineering Lab 2: FPGA Tools and Combinatorial Logic Design E85: Digital Design and Computer Engineering Lab 2: FPGA Tools and Combinatorial Logic Design Objective The purpose of this lab is to learn to use Field Programmable Gate Array (FPGA) tools to simulate

More information

ECE 3610 Microprocessing Systems Lab #1 Verilog Design of the TOC Using Quartus II

ECE 3610 Microprocessing Systems Lab #1 Verilog Design of the TOC Using Quartus II ECE 3610 Microprocessing Systems Lab #1 Verilog Design of the TOC Using Quartus II This lab manual presents an introduction to the Quartus II Computer Aided Design (CAD) system. This manual gives step-by-step

More information

QUARTUS II Altera Corporation

QUARTUS II Altera Corporation QUARTUS II Quartus II Design Flow Design Entry Timing Constraints Synthesis Placement and Routing Timing, Area, Power Optimization Timing and Power Analyzer Optimized Design 2 Can I still use a Processor?

More information

Quartus II Introduction Using Verilog Design

Quartus II Introduction Using Verilog Design Quartus II Introduction Using Verilog Design This tutorial presents an introduction to the Quartus R II CAD system. It gives a general overview of a typical CAD flow for designing circuits that are implemented

More information

EE 231 Fall Lab 1: Introduction to Verilog HDL and Altera IDE

EE 231 Fall Lab 1: Introduction to Verilog HDL and Altera IDE Lab 1: Introduction to Verilog HDL and Altera IDE Introduction In this lab you will design simple circuits by programming the Field-Programmable Gate Array (FPGA). At the end of the lab you should be able

More information

Engineering 303 Digital Logic Design Spring 2017

Engineering 303 Digital Logic Design Spring 2017 Engineering 303 Digital Logic Design Spring 2017 LAB 1 Introduction to Combo Logic and Quartus Deliverables: 0) A Simple Verilog Combinatorial Circuit 1) A Simple Block Diagram Combinatorial Circuit 2)

More information

EE 231 Fall EE 231 Lab 2

EE 231 Fall EE 231 Lab 2 EE 231 Lab 2 Introduction to Verilog HDL and Quartus In the previous lab you designed simple circuits using discrete chips. In this lab you will do the same but by programming the CPLD. At the end of the

More information

CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND:

CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND: CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOALS: Getting familiar with DE2 board installation, properties, usage.

More information

Digital Systems Laboratory

Digital Systems Laboratory 2012 Fall CSE140L Digital Systems Laboratory by Dr. Choon Kim CSE Department UCSD 1 Welcome to CSE140L! 2 3-way Light Controller, 2-1 MUX, Majority Detector, 7- seg Display, Binary-to- Decimal converter.

More information

Laboratory Exercise 8

Laboratory Exercise 8 Laboratory Exercise 8 Memory Blocks In computer systems it is necessary to provide a substantial amount of memory. If a system is implemented using FPGA technology it is possible to provide some amount

More information

Laboratory Exercise 1

Laboratory Exercise 1 Laboratory Exercise 1 Switches, Lights, and Multiplexers The purpose of this exercise is to learn how to connect simple input and output devices to an FPGA chip and implement a circuit that uses these

More information

NOTE: This tutorial contains many large illustrations. Page breaks have been added to keep images on the same page as the step that they represent.

NOTE: This tutorial contains many large illustrations. Page breaks have been added to keep images on the same page as the step that they represent. CSE 352 Tutorial # 4 Synthesizing onto an FPGA Objectives This tutorial will walk you through the steps of implementing a design made in Active-HDL onto the Altera Cyclone II FPGA NOTE: This tutorial contains

More information

Physics 536 Spring Illustrating the FPGA design process using Quartus II design software and the Cyclone II FPGA Starter Board.

Physics 536 Spring Illustrating the FPGA design process using Quartus II design software and the Cyclone II FPGA Starter Board. Physics 536 Spring 2009 Illustrating the FPGA design process using Quartus II design software and the Cyclone II FPGA Starter Board. Digital logic: Equivalent to a large number of discrete logic elements

More information

Quartus II Version 14.0 Tutorial Created September 10, 2014; Last Updated January 9, 2017

Quartus II Version 14.0 Tutorial Created September 10, 2014; Last Updated January 9, 2017 Quartus II Version 14.0 Tutorial Created September 10, 2014; Last Updated January 9, 2017 This tutorial will walk you through the process of developing circuit designs within Quartus II, simulating with

More information

University of Massachusetts Amherst Computer Systems Lab 2 (ECE 354) Spring Lab 1: Using Nios 2 processor for code execution on FPGA

University of Massachusetts Amherst Computer Systems Lab 2 (ECE 354) Spring Lab 1: Using Nios 2 processor for code execution on FPGA University of Massachusetts Amherst Computer Systems Lab 2 (ECE 354) Spring 2007 Lab 1: Using Nios 2 processor for code execution on FPGA Objectives: After the completion of this lab: 1. You will understand

More information

Quartus II Tutorial. September 10, 2014 Quartus II Version 14.0

Quartus II Tutorial. September 10, 2014 Quartus II Version 14.0 Quartus II Tutorial September 10, 2014 Quartus II Version 14.0 This tutorial will walk you through the process of developing circuit designs within Quartus II, simulating with Modelsim, and downloading

More information

CSE P567 - Winter 2010 Lab 1 Introduction to FGPA CAD Tools

CSE P567 - Winter 2010 Lab 1 Introduction to FGPA CAD Tools CSE P567 - Winter 2010 Lab 1 Introduction to FGPA CAD Tools This is a tutorial introduction to the process of designing circuits using a set of modern design tools. While the tools we will be using (Altera

More information

Contents. Appendix B HDL Entry Tutorial 2 Page 1 of 14

Contents. Appendix B HDL Entry Tutorial 2 Page 1 of 14 Appendix B HDL Entry Tutorial 2 Page 1 of 14 Contents Appendix B HDL Entry Tutorial 2...2 B.1 Getting Started...2 B.1.1 Preparing a Folder for the Project...2 B.1.2 Starting Quartus II...2 B.1.3 Creating

More information

Altera Quartus II Tutorial ECE 552

Altera Quartus II Tutorial ECE 552 Altera Quartus II Tutorial ECE 552 Quartus II by Altera is a PLD Design Software which is suitable for high-density Field-Programmable Gate Array (FPGA) designs, low-cost FPGA designs, and Complex Programmable

More information

CHAPTER 1 INTRODUCTION... 1 CHAPTER 2 ASSIGN THE DEVICE... 7 CHAPTER 3 DESIGN ENTRY CHAPTER 4 COMPILE AND VERIFY YOUR DESIGN...

CHAPTER 1 INTRODUCTION... 1 CHAPTER 2 ASSIGN THE DEVICE... 7 CHAPTER 3 DESIGN ENTRY CHAPTER 4 COMPILE AND VERIFY YOUR DESIGN... CONTENTS CHAPTER 1 INTRODUCTION... 1 1.1 DESIGN FLOW... 1 1.2 BEFORE YOU BEGIN... 2 1.3 WHAT YOU WILL LEARN... 6 CHAPTER 2 ASSIGN THE DEVICE... 7 2.1 ASSIGN THE DEVICE... 7 CHAPTER 3 DESIGN ENTRY... 11

More information

Chip Design with FPGA Design Tools

Chip Design with FPGA Design Tools Chip Design with FPGA Design Tools Intern: Supervisor: Antoine Vazquez Janusz Zalewski Florida Gulf Coast University Fort Myers, FL 33928 V1.9, August 28 th. Page 1 1. Introduction FPGA is abbreviation

More information

SCHEMATIC DESIGN IN QUARTUS

SCHEMATIC DESIGN IN QUARTUS SCHEMATIC DESIGN IN QUARTUS Consider the design of a three-bit prime number detector. Figure 1 shows the block diagram and truth table. The inputs are binary signals A, B, and C while the output is binary

More information

COSC 3215 Embedded Systems Laboratory

COSC 3215 Embedded Systems Laboratory COSC 3215 Embedded Systems Laboratory Lab 5 The Altera, Verilog and QuartusII Introduction This lab is an introduction to the Altera FPGA development board and the accompanying FPGA programming environment

More information

Lab 6: Integrated the Decoder with Muti-bit Counter and Programming a FPGA

Lab 6: Integrated the Decoder with Muti-bit Counter and Programming a FPGA Lab 6: Integrated the Decoder with Muti-bit Counter and Programming a FPGA For your report: The problem written in English The flowchart or function table to solve the problem if it is necessary The design

More information

SOPC LAB1. I. Introduction. II. Lab contents. 4-bit count up counter. Advanced VLSI Due Wednesday, 01/08/2003

SOPC LAB1. I. Introduction. II. Lab contents. 4-bit count up counter. Advanced VLSI Due Wednesday, 01/08/2003 SOPC LAB1 I. Introduction The purpose of this lab is to familiarize you with all the items in the kit. This tutorial tells you how to develop FPGA system in Quartus II. You are ready to begin using the

More information

QuartusII.doc 25/02/2005 Page 1

QuartusII.doc 25/02/2005 Page 1 1 Start Icon... 2 1.1 The Quartus II Screen... 2 2 Project creation... 2 3 Schematic entry... 5 3.1 Create new drawing... 5 3.2 Symbol selection... 7 3.3 Placement of an AND gate... 8 3.4 Deleting a symbol...

More information

discrete logic do not

discrete logic do not Welcome to my second year course on Digital Electronics. You will find that the slides are supported by notes embedded with the Powerpoint presentations. All my teaching materials are also available on

More information

NIOS CPU Based Embedded Computer System on Programmable Chip

NIOS CPU Based Embedded Computer System on Programmable Chip NIOS CPU Based Embedded Computer System on Programmable Chip 1 Lab Objectives EE8205: Embedded Computer Systems NIOS-II SoPC: PART-I This lab has been constructed to introduce the development of dedicated

More information

Programmable Logic Design Techniques I

Programmable Logic Design Techniques I PHY 440 Lab14: Programmable Logic Design Techniques I The design of digital circuits is a multi-step process. It starts with specifications describing what the circuit must do. Defining what a circuit

More information

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science. EECS 150 Spring 2000

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science. EECS 150 Spring 2000 University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Spring 2000 Lab 1 Introduction to Xilinx Design Software 1 Objectives In this

More information

Quartus II Introduction Using Verilog Designs. 1 Introduction. For Quartus II 12.0

Quartus II Introduction Using Verilog Designs. 1 Introduction. For Quartus II 12.0 Quartus II Introduction Using Verilog Designs For Quartus II 12.0 1 Introduction This tutorial presents an introduction to the Quartus II CAD system. It gives a general overview of a typical CAD flow for

More information

ELEC 4200 Lab#0 Tutorial

ELEC 4200 Lab#0 Tutorial 1 ELEC 4200 Lab#0 Tutorial Objectives(1) In this Lab exercise, we will design and implement a 2-to-1 multiplexer (MUX), using Xilinx Vivado tools to create a VHDL model of the design, verify the model,

More information

University of California, Davis Department of Electrical and Computer Engineering. Lab 1: Implementing Combinational Logic in the MAX10 FPGA

University of California, Davis Department of Electrical and Computer Engineering. Lab 1: Implementing Combinational Logic in the MAX10 FPGA 1 University of California, Davis Department of Electrical and Computer Engineering EEC180B DIGITAL SYSTEMS II Winter Quarter 2018 Lab 1: Implementing Combinational Logic in the MAX10 FPGA Objective: This

More information

IMPLEMENTING COUNTERS

IMPLEMENTING COUNTERS EECS:6660:0xxField Programmable Gate Arrays s11l1_fpga.fm - 1 Lab Assignment #1 Due Thursday, March 31 2011 IMPLEMENTING COUNTERS 1. OBJECTIVES - learning the VHDL implementation process using Language

More information

Chapter 2: Hardware Design Flow Using Verilog in Quartus II

Chapter 2: Hardware Design Flow Using Verilog in Quartus II Chapter 2: Hardware Design Flow Using Verilog in Quartus II 2.1 Introduction to Quartus II System Development Software This chapter is an introduction to the Quartus II software that will be used for analysis

More information

Laboratory 4 Design a Muti-bit Counter and Programming a FPGA

Laboratory 4 Design a Muti-bit Counter and Programming a FPGA Laboratory 4 Design a Muti-bit Counter and Programming a FPGA For your report: The problem written in English The flowchart or function table to solve the problem if it is necessary The design entry included

More information

EE183 LAB TUTORIAL. Introduction. Projects. Design Entry

EE183 LAB TUTORIAL. Introduction. Projects. Design Entry EE183 LAB TUTORIAL Introduction You will be using several CAD tools to implement your designs in EE183. The purpose of this lab tutorial is to introduce you to the tools that you will be using, Xilinx

More information

Lab 2: Introduction to Verilog HDL and Quartus

Lab 2: Introduction to Verilog HDL and Quartus Lab 2: Introduction to Verilog HDL and Quartus September 16, 2008 In the previous lab you designed simple circuits using discrete chips. In this lab you will do the same but by programming the CPLD. At

More information

Laboratory 4 Design a Muti-bit Counter

Laboratory 4 Design a Muti-bit Counter Laboratory 4 Design a Muti-bit Counter Background A. Approach I: Design 3-bit counter with and clear T-type flip-flop is shown in Figure 1. A T flip-flop is obtained from a JK flip-flop by tying the J

More information

Using XILINX WebPACK Software to Create CPLD Designs

Using XILINX WebPACK Software to Create CPLD Designs Introduction to WebPACK Using XILINX WebPACK Software to Create CPLD Designs RELEASE DATE: 10/24/1999 All XS-prefix product designations are trademarks of XESS Corp. All XC-prefix product designations

More information

CET4805 Component and Subsystem Design II. EXPERIMENT # 2: VHDL(VHSIC Hardware Descriptive Language) Name: Date:

CET4805 Component and Subsystem Design II. EXPERIMENT # 2: VHDL(VHSIC Hardware Descriptive Language) Name: Date: EXPERIMENT # 2: VHDL(VHSIC Hardware Descriptive Language) Name: Date: Equipment/Parts Needed: Quartus II R Web Edition V9.1 SP2 software by Altera Corporation USB drive to save your files Objective: Learn

More information

PRELAB! Read the entire lab, and complete the prelab questions (Q1-Q3) on the answer sheet before coming to the laboratory.

PRELAB! Read the entire lab, and complete the prelab questions (Q1-Q3) on the answer sheet before coming to the laboratory. PRELAB! Read the entire lab, and complete the prelab questions (Q1-Q3) on the answer sheet before coming to the laboratory. 1.0 Objectives In the last lab we learned that Verilog is a fast and easy way

More information

Tutorial 2 Implementing Circuits in Altera Devices

Tutorial 2 Implementing Circuits in Altera Devices Appendix C Tutorial 2 Implementing Circuits in Altera Devices In this tutorial we describe how to use the physical design tools in Quartus II. In addition to the modules used in Tutorial 1, the following

More information

Lecture 1: Introduction Course arrangements Recap of basic digital design concepts EDA tool demonstration

Lecture 1: Introduction Course arrangements Recap of basic digital design concepts EDA tool demonstration TKT-1426 Digital design for FPGA, 6cp Fall 2011 http://www.tkt.cs.tut.fi/kurssit/1426/ Tampere University of Technology Department of Computer Systems Waqar Hussain Lecture Contents Lecture 1: Introduction

More information

Name EGR 2131 Lab #6 Number Representation and Arithmetic Circuits

Name EGR 2131 Lab #6 Number Representation and Arithmetic Circuits Name EGR 2131 Lab #6 Number Representation and Arithmetic Circuits Equipment and Components Quartus software and Altera DE2-115 board PART 1: Number Representation in Microsoft Calculator. First, let s

More information

CSEE W4840 Embedded System Design Lab 1

CSEE W4840 Embedded System Design Lab 1 CSEE W4840 Embedded System Design Lab 1 Stephen A. Edwards Due January 31, 2008 Abstract Learn to use the Altera Quartus development envrionment and the DE2 boards by implementing a small hardware design

More information

DOWNLOADING DESIGNS TO THE ALTERA DE10-LITE FPGA

DOWNLOADING DESIGNS TO THE ALTERA DE10-LITE FPGA DOWNLOADING DESIGNS TO THE ALTERA DE10-LITE FPGA Consider the design of a three-bit prime number detector completed in the MSOE schematic entry tutorial. Figure 1 shows the block diagram and truth table.

More information

SFWR ENG 2DA4 Lab 1. Announcements: Marking Scheme: Lab Safety Manual:

SFWR ENG 2DA4 Lab 1. Announcements: Marking Scheme: Lab Safety Manual: SFWR ENG 2DA4 Lab 1 First lab Week of: Sept. 17, 2018 Prep Due week of: (8:40/14:40), Sept. 24, 2018 Demo Due Week of: (11:20/17:20), Sept. 24, 2018 Assignment due in class: 13:40, Sept. 28, 2018 Announcements:

More information

ANADOLU UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING. EEM Digital Systems II

ANADOLU UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING. EEM Digital Systems II ANADOLU UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EEM 334 - Digital Systems II LAB 1 - INTRODUCTION TO XILINX ISE SOFTWARE AND FPGA 1. PURPOSE In this lab, after you learn to use

More information

Introduction to Computer Engineering (E114)

Introduction to Computer Engineering (E114) Introduction to Computer Engineering (E114) Lab 1: Full Adder Introduction In this lab you will design a simple digital circuit called a full adder. You will then use logic gates to draw a schematic for

More information

Experiment 18 Full Adder and Parallel Binary Adder

Experiment 18 Full Adder and Parallel Binary Adder Objectives Experiment 18 Full Adder and Parallel Binary Adder Upon completion of this laboratory exercise, you should be able to: Create and simulate a full adder in VHDL, assign pins to the design, and

More information

LAB 2: INTRODUCTION TO LOGIC GATE AND ITS BEHAVIOUR

LAB 2: INTRODUCTION TO LOGIC GATE AND ITS BEHAVIOUR LAB 2: INTRODUCTION TO LOGIC GATE AND ITS BEHAVIOUR OBJECTIVE 1. To verify the operation of OR, AND, INVERTER gates 2. To implement the operation of NAND and NOR gate 3. To construct a simple combinational

More information

Verilog Simulation Mapping

Verilog Simulation Mapping 1 Motivation UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Lab 4 Verilog Simulation Mapping In this lab you will learn how to use

More information

CSCB58 - Lab 0. Intro to The Lab & The DE2 Board. Prelab /4 Part I (in-lab) /1 Part II (in-lab) /1

CSCB58 - Lab 0. Intro to The Lab & The DE2 Board. Prelab /4 Part I (in-lab) /1 Part II (in-lab) /1 CSCB58 - Lab 0 Intro to The Lab & The DE2 Board Learning Objectives This week we will be getting you familiar with the lab and the boards that we will be using in later labs. You will also learn how to

More information

1 Introduction 2. 2 Background 3. 3 Getting Started 4. 4 Starting a New Project 6. 5 Design Entry Using VHDL Code 13

1 Introduction 2. 2 Background 3. 3 Getting Started 4. 4 Starting a New Project 6. 5 Design Entry Using VHDL Code 13 Quartus Prime Introduction Using VHDL Designs For Quartus Prime 17.0 Contents 1 Introduction 2 2 Background 3 3 Getting Started 4 3.1 Quartus Prime Online Help................................................................................................

More information

Verilog Design Entry, Synthesis, and Behavioral Simulation

Verilog Design Entry, Synthesis, and Behavioral Simulation ------------------------------------------------------------- PURPOSE - This lab will present a brief overview of a typical design flow and then will start to walk you through some typical tasks and familiarize

More information

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science

University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 150 Fall 2000 Original Lab By: J.Wawrzynek and N. Weaver Edited by B. Choi, R.

More information

DKAN0011A Setting Up a Nios II System with SDRAM on the DE2

DKAN0011A Setting Up a Nios II System with SDRAM on the DE2 DKAN0011A Setting Up a Nios II System with SDRAM on the DE2 04 November 2009 Introduction This tutorial details how to set up and instantiate a Nios II system on Terasic Technologies, Inc. s DE2 Altera

More information

Xilinx ChipScope ICON/VIO/ILA Tutorial

Xilinx ChipScope ICON/VIO/ILA Tutorial Xilinx ChipScope ICON/VIO/ILA Tutorial The Xilinx ChipScope tools package has several modules that you can add to your Verilog design to capture input and output directly from the FPGA hardware. These

More information

TLL5000 Electronic System Design Base Module. Getting Started Guide, Ver 3.4

TLL5000 Electronic System Design Base Module. Getting Started Guide, Ver 3.4 TLL5000 Electronic System Design Base Module Getting Started Guide, Ver 3.4 COPYRIGHT NOTICE The Learning Labs, Inc. ( TLL ) All rights reserved, 2008 Reproduction in any form without permission is prohibited.

More information

PREFACE. Changes to the SOPC Edition

PREFACE. Changes to the SOPC Edition PREFACE Changes to the SOPC Edition Rapid Prototyping of Digital Systems provides an exciting and challenging laboratory component for undergraduate digital logic and computer design courses using FPGAs

More information

Experiment 8 Introduction to VHDL

Experiment 8 Introduction to VHDL Experiment 8 Introduction to VHDL Objectives: Upon completion of this laboratory exercise, you should be able to: Enter a simple combinational logic circuit in VHDL using the Quartus II Text Editor. Assign

More information

CET4805 Component and Subsystem Design II. EXPERIMENT # 5: Adders. Name: Date:

CET4805 Component and Subsystem Design II. EXPERIMENT # 5: Adders. Name: Date: EXPERIMENT # 5: Adders Name: Date: Equipment/Parts Needed: Quartus II R Web Edition V9.1 SP2 software by Altera Corporation USB drive to save your files Objective: Design a half adder by extracting the

More information

My First FPGA Design Tutorial

My First FPGA Design Tutorial 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com TU-01002-1.0 Copyright 2007 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized

More information

DE2 Board & Quartus II Software

DE2 Board & Quartus II Software January 23, 2015 Contact and Office Hours Teaching Assistant (TA) Sergio Contreras Office Office Hours Email SEB 3259 Tuesday & Thursday 12:30-2:00 PM Wednesday 1:30-3:30 PM contre47@nevada.unlv.edu Syllabus

More information

The board is powered by the USB connection, so to turn it on or off you plug it in or unplug it, respectively.

The board is powered by the USB connection, so to turn it on or off you plug it in or unplug it, respectively. Lab 1 You may work in pairs or individually on this lab Lab Objectives Learn about the equipment we will be using and how to handle it safely. Learn the basics of using Xilinx ISE to develop hardware designs

More information

EE 1315 DIGITAL LOGIC LAB EE Dept, UMD

EE 1315 DIGITAL LOGIC LAB EE Dept, UMD EE 1315 DIGITAL LOGIC LAB EE Dept, UMD EXPERIMENT # 1: Logic building blocks The main objective of this experiment is to let you familiarize with the lab equipment and learn about the operation of the

More information

Design Flow Tutorial

Design Flow Tutorial Digital Design LU Design Flow Tutorial Jakob Lechner, Thomas Polzer {lechner, tpolzer}@ecs.tuwien.ac.at Department of Computer Engineering University of Technology Vienna Vienna, October 8, 2010 Contents

More information

To practice combinational logic on Logisim and Xilinx ISE tools. ...

To practice combinational logic on Logisim and Xilinx ISE tools. ... ENGG1203: Introduction to Electrical and Electronic Engineering Second Semester, 2017 18 Lab 1 Objective: To practice combinational logic on Logisim and Xilinx ISE tools. 1 Find your lab partner You will

More information

Simulating a Design Circuit Using Qsim

Simulating a Design Circuit Using Qsim Simulating a Design Circuit Using Qsim 1. Start Qsim From version 11.1, Quartus II provides another simulating tool called Qsim. Qsim is bundled with both subscript edition and web edition of Quartus II.

More information