EEEP. PICMG EeeP. Embedded EEPROM Specification. Revision 1.0 August 8, 2010

Transcription

1 EEEP PICMG EeeP Embedded EEPROM Specification Revision 1.0 August 8, 2010 PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 1 of 84

2 Copyright 2009, PCI Industrial Computer Manufacturers Group. The attention of adopters is directed to the possibility that compliance with or adoption of PICMG specifications may require use of an invention covered by patent rights. PICMG shall not be responsible for identifying patents for which a license may be required by any PICMG specification or for conducting legal inquiries into the legal validity or scope of those patents that are brought to its attention. PICMG specifications are prospective and advisory only. Prospective users are responsible for protecting themselves against liability for infringement of patents. NOTICE: The information contained in this document is subject to change without notice. The material in this document details a PICMG specification in accordance with the license and notices set forth on this page. This document does not represent a commitment to implement any portion of this specification in any company's products. WHILE THE INFORMATION IN THIS PUBLICATION IS BELIEVED TO BE ACCURATE, PICMG MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, ANY WARRANTY OF TITLE OR OWNERSHIP, IMPLIED WARRANTY OF MERCHANTABILITY OR WARRANTY OF FITNESS FOR PARTICULAR PURPOSE OR USE. In no event shall PICMG be liable for errors contained herein or for indirect, incidental, special, consequential, reliance or cover damages, including loss of profits, revenue, data or use, incurred by any user or any third party. Compliance with this specification does not absolve manufacturers of equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.). PICMG, CompactPCI, AdvancedTCA, AdvancedTCA 300,ATCA, ATCA 300, CompactPCI Express, COM Express, SHB Express, and the PICMG, CompactPCI, AdvancedTCA, µtca and ATCA logos are registered trademarks, and MicroTCA, xtca and AdvancedMC are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holders. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 2 of 84

3 Table of Contents 1 Introduction Name and Logo Usage Intellectual Property Necessary Claims (referring to mandatory or recommended features) Unnecessary Claims (referring to optional features or non-normative elements) Third Party Disclosures Copyright Notice Trademarks Special Word Usage Acronyms / Definitions Applicable Documents and Standards Statement of Compliance General Overview Storage Conventions Multi-Byte Variables Structure Packing Detection Detecting EeeP EEPROM High Level Check Sample I2C Transfer Detecting COM0 R1.0 EEPROM High Level Check Sample I2C Transfer Identifying Device Type Standard/Extended Index Sample I2C Transfer EEPROM Header Components Concepts Common EeeP EEPROM Header Description Header Elements Universal Device Identifier Description Block Elements EEPROM Headers COM0 R2.0 Carrier Board EEPROM Header Description Header Elements COM0 R2.0 Module EEPROM Header Description Header Elements Expansion EEPROM Header Description Header Elements Dynamic Descriptor Blocks Common Dynamic Block Header Description Block Elements Parse Order / Block Priority Express Card Topology Description Block Elements Example Blocks Serial Port Configuration Block...38 PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 3 of 84

4 6.3.1 Description Block Elements Example Blocks SMBIOS Common Block Header Description Block Elements SMBIOS Block String Storage convention System Information Descriptor Block Description Block Elements Example Block Base Board (or Module) Information Descriptor Block Description Block Elements Example Block System Enclosure or Chassis Descriptor Block Description Block Elements Example Block LFP Device Descriptor Block Description Block Elements Example Block Vendor Specific Block Description Block Elements Example Block CRC16 Block Description Block Elements Example Block Expansion EEPROM descriptor Description Block Elements Example Block Sample EEPROM Content Sample Carrier Board EEPROM Content COM0R20 Type 2 Carrier Board With Expansion EEPROM COM0R20 Type 2 Carrier Board Sample COM0R20 Module EEPROM Content Sample 1 All in CRC Sample 2 With Data outside CRC Sample Expansion EEPROM Content Sample Chassis Expansion EEPROM Standard Data Formats Compressed ASCII PNPID Definition Example EEPROM Specification Revision Definition Examples Assembler Sample Code Headers EeeP.h COM0EEP.h Sample Code Revision History PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 4 of 84

5 Dynamic Block Structures Common Dynamic Block Header Express Card Extended Topology Express Card Extended Topology SMBIOS Dynamic Block Header SMBIOS System Info SMBIOS Module Information SMBIOS Chassis Info LFP Device Descriptor Vendor Specific CRC Additional EEPROM descriptor C Sample Code Detect COM0 R2.0 FRUPROM Detect COM0 R1.0 FRUPROM Decode PCIe Link Width & Start Lane...32 CRC-CCITT implementation MASM Sample Code Decode PCIe Link Width & Start Lane...66 CRC-CCITT 386 implementation EEPROM Header Structures Common EEPROM Header Universal Device Identifier COM0 R2.0 Carrier Board EEPROM Header...24 Module EEPROM Header Module EEPROM Header PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 5 of 84

6 Index of Tables Table 1-1: Terms and Definitions Table 4-1: Device Descriptor Byte Table 4-2: Example Device Unique Revision IDs...23 Table 5-1: USB Descriptor Byte Table 5-2: SATA / SAS Device Descriptor Byte...26 Table 5-3: LAN Descriptor Byte Table 5-4: Miscellaneous I/O Descriptor Byte...28 Table 5-5: Miscellaneous I/O Descriptor Byte Table 5-6: Digital Display Interface Descriptor Byte Table 5-7: PCI Express Lane Generation Descriptor...30 Table 5-8: PCI Express Lane Descriptor Nibble Descriptor...31 Table 5-9: PCI Express Valid Starting Lane Configurations...31 Table 6-1: Dynamic Block Ids Table 6-2: Dynamic Block Length Values...35 Table 6-3: Com Express Ports Table 6-4: Device Function Addresses...38 Table 6-5: Express Card Block Example Table 6-6: Express Card Block Example Table 6-7: Serial IRQ Description Ports...39 Table 6-8: Serial Base Address Table 6-9: Serial Base Address Table 6-10: Serial Port Configuration Block...40 Table 6-11: EeeP Defined SMBIOS Handles...41 Table 6-12: EeeP Defined SMBIOS Handles...41 Table 6-13: System Information Descriptor Block Example...43 Table 6-14: 'COM_0 Module' Module Information Descriptor Block Example...45 Table 6-15: 'Carrier Board' Module Information Descriptor Block Example...46 Table 6-16: Chassis Information Descriptor Block Example...48 Table 6-17: LFP Device Descriptor Block Example...49 Table 6-18: LFP Device Descriptor Block Example...49 Table 6-19: Vendor Specific Block Example...50 Table 6-20: CRC16 Block Example Table 6-21: Device Bus Ids Table 6-22: Expansion EEPROM descriptor Example...53 Table 7-1: COM0R20 Type 2 Carrier Board With Expansion EEPROM...54 Table 7-2: COM0R20 Type 2 Carrier Board...57 Table 7-3: Sample 1 All in CRC Table 7-4: Sample 2 With Data outside CRC...61 Table 7-5: Sample Chassis Expansion EEPROM...63 Table 11-1: Document Revision History...86 PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 6 of 84

7 1 Introduction 1.1 Name and Logo Usage The PCI Industrial Computer Manufacturers Group policies regarding the use of its logos and trademarks are as follows: Permission to use the PICMG organization logo is automatically granted to designated members only as stipulated on the most recent Membership Privileges document (available at during the period of time for which their membership dues are paid. Nonmembers may not use the PICMG organization logo. The PICMG organization logo must be printed in black or color as shown in the files available for download from the member s side of the Web site. Logos with or without the Open Modular Computing Specifications banner can be used. Nothing may be added or deleted from the PICMG logo. The use of the COM Express logo is a privilege granted by the PICMG organization to companies who have purchased the relevant specifications (or acquired them as a member benefit), and that believe their products comply with these specifications. Manufacturers' distributors and sales representatives may use the COM Express logo in promoting products sold under the name of the manufacturer. Use of the logos by either members or non-members implies such compliance. Only PICMG Executive and Associate members may use the PICMG logo. PICMG may revoke permission to use logos if they are misused. The COM Express logo can be found on the PICMG web site, The COM Express logo must be used exactly as shown in the files available for download from the PICMG Web site. The aspect ratios of the logos must be maintained, but the sizes may be varied.nothing may be added to or deleted from the COM Express logo. The PICMG name and logo and the COM Express name and logo are registered trademarks of PICMG. Registered trademarks must be followed by the symbol, and the following statement must appear in all published literature and advertising material in which the logo appears: PICMG, the COM Express name and logo and the PICMG logo are registered trademarks of the PCI Indust rial Computers Manufactu rers Group. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 7 of 84

8 1.2 Intellectual Property The Consortium draws attention to the fact that it is claimed that compliance with this specification may involve the use of a patent claim(s) ("IPR"). The Consortium takes no position concerning the evidence, validity or scope of this IPR. The holder of this IPR has assured the Consortium that it is willing to license or sublicense all such IPR to those licensees (Members and non-members alike) desiring to implement this specification. The statement of the holder of this IPR to such effect has been filed with the Consortium. Attention is also drawn to the possibility that some of the elements of this specification may be the subject of IPR other than those identified below. The Consortium shall not be responsible for identifying any or all such IPR. No representation is made as to the availability of any license rights for use of any IPR inherent in this specification for any purpose other than to implement this specification. This specification conforms to the current PICMG Intellectual Property Rights Policy and the Policies and Procedures for Specification Development and does not contain any known intellectual property that is not available for licensing under Reasonable and Non-discriminatory terms. In the course of Membership Review the following disclosures were made: Necessary Claims (referring to mandatory or recommended features) No disclosures in this category were made during subcommittee review Unnecessary Claims (referring to optional features or non-normative elements) No disclosures in this category were made during subcommittee review. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 8 of 84

9 1.2.3 Third Party Disclosures (Note that third party IPR submissions do not contain any claim of willingness to license the IPR.) No disclosures in this category were made during subcommittee review. Refer to PICMG IPR Policies and Procedures and the company owner of the patent for terms and conditions of usage. PICMG makes no judgment as to the validity of these claims or the licensing terms offered by the claimants. THIS SPECIFICATION IS BEING OFFERED WITHOUT ANY WARRANTY WHATSOEVER, AND IN PARTICULAR, ANY WARRANTY OF NON-INFRINGEMENT IS EXPRESSLY DISCLAIMED. ANY USE OF THIS SPECIFICATION SHALL BE MADE ENTIRELY AT THE IMPLEMENTER'S OWN RISK, AND NEITHER THE CONSORTIUM, NOR ANY OF ITS MEMBERS OR SUBMITTERS, SHALL HAVE ANY LIABILITY WHATSOEVER TO ANY IMPLEMENTER OR THIRD PARTY FOR ANY DAMAGES OF ANY NATURE WHATSOEVER, DIRECTLY OR INDIRECTLY, ARISING FROM THE USE OF THIS SPECIFICATION. Compliance with this specification does not absolve manufacturers of COM Express equipment from the requirements of safety and regulatory agencies (UL, CSA, FCC, IEC, etc.). PICMG and the COM Express logos are trademarks of the PCI Industrial Computer Manufacturers Group. All other brand or product names may be trademarks or registered trademarks of their respective holder. 1.3 Copyright Notice Copyright 2009, PICMG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without written permission from PICMG. PICMG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied as-is. 1.4 Trademarks Intel and Pentium are registered trademarks of Intel Corporation. ExpressCard is a registered trademark of Personal Computer Memory Card International Association (PCMCIA). PCI Express is a registered trademark of Peripheral Component Interconnect Special Interest Group (PCI-SIG). COM Express is a registered trademark of PCI Industrial Computer Manufacturers Group (PICMG). I2C is a registered trademark of NXP Semiconductors. CompactFlash is a registered trademark of CompactFlash Association. Winbond is a registered trademark of Winbond Electronics Corp. AVR is a registered trademark of Atmel Corporation. Microsoft, Windows, Windows NT, Windows CE and Windows XP are registered trademarks of Microsoft Corporation. VxWorks is a registered trademark of WindRiver. All product names and logos are property of their owners. 1.5 Special Word Usage Mandatory features are indicated by the use of the word shall. Recommended features are indicated by the use of the word should. Optional features are indicated by the use of the word may. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 9 of 84

10 1.6 Acronyms / Definitions Term a.out AC 97 ACPI Atomic Error Checking Basic Module BBS BIOS Big-endian Carrier Board CCTV CVBS Compact Module DDC DIMM DisplayPort Table 1-1: Terms and Definitions Definition a.out is a file format used in older versions of Unix-like computer operating systems for executable, object code, and, in later systems, shared libraries. The name stands for assembler output Audio CODEC (Coder-Decoder) Advanced Configuration Power Interface standard to implement power saving modes in PC-AT systems This Is used here to refer to the mechanism of validating all arguments before modifications are carried out. COM Express 125mm x 95mm Module form factor. Bios Boot Specification. Basic Input Output System firmware in PC-AT system that is used to initialize system components before handing control over to the operating system. Register Value: 0x0A0B0C0D Memory Order: 0x0A, 0x0B, 0x0C, 0x0D The most significant byte (MSB) value, which is 0x0A in our example, is stored at the memory location with the lowest address, the next byte value in significance, 0x0B, is stored at the following memory location and so on. This is akin to Left-to-Right reading in hexadecimal order. An application specific circuit board that accepts a COM Express Module. Closed Circuit Television Composite Video Baseband Signal COM Express 95x95 Module form factor Display Data Control VESA (Video Electronics Standards Association) standard to allow identification of the Dynamic of a VGA monitor Dual In-line Memory Module DisplayPort is a digital display interface standard put forth by the Video Electronics Standards Association (VESA). It defines a new license free, royalty free, digital audio/video interconnect, intended to be used primarily between a computer and its display monitor. Dynamic Random Access Memory DRAM DVI Digital Visual Interface - a Digital Display Working Group (DDWG) standard that defines a standard video interface supporting both digital and analog video signals. The digital signals use TMDS. EAPI Embedded Application Programming Interface Software interface for COM Express specific industrial functions System information Watchdog timer I2C Bus Flat Panel brightness control User storage are. GPIO edp Embedded Display Port. EEPROM Electrically Erasable Programmable Read-Only Memory EFI Extensible Firmware Interface(Next Generation BIOS) EFI BIOS Used to explicitly distinguish EFI and Legacy BIOS. EFP External Flat Panel Extended Module COM Express 155mm x 110mm Module form factor. FR4 A type of fiber-glass laminate commonly used for printed circuit boards. Gb Gigabit GBE Gigabit Ethernet GPI General Purpose Input GPIO General Purpose Input Output GPO General Purpose Output HDA Intel High Definition Audio (HD Audio) refers to the specification released by Intel in 2004 for delivering high definition audio that is capable of playing back more channels at higher quality than AC97. HDMI High Definition Multimedia Interface I 2 C Inter Integrated Circuit 2 wire (clock and data) signaling scheme allowing communication between integrated circuits, primarily used to read and load register values. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 10 of 84

11 Term IDE Legacy Device LAN Little-endian LFP LPC LS LVDS MS NA NC NTSC OEM PAL PATA PC-AT PCB PCI PCI Express PCIE PEG PHY Pin-out Type PNPID PS2 PS2 Keyboard PS2 Mouse R a ROM RTC SAS SCSI SPD SPI SO-DIMM S0, S1, S2, S3, S4, S5 SATA Definition Integrated Device Electronics parallel interface for hard disk drives also known as PATA Relics from the PC-AT computer that are not in use in contemporary PC systems: primarily the ISA bus, UART-based serial ports, parallel printer ports, PS-2 keyboards, and mice. Definitions vary as to what constitutes a legacy device. Some definitions include IDE as a legacy device. Local Area Network Register Value: 0x0A0B0C0D Memory Order: 0x0D, 0x0C, 0x0B, 0x0A The least significant byte (LSB) value, 0x0D, is at the lowest address. The other bytes follow in increasing order of significance. Local Flat Panel Low Pin-Count Interface: a low speed interface used for peripheral circuits such as Super I/O controllers, which typically combine legacy-device support into a single IC. Least Significant Low Voltage Differential Signaling widely used as a physical interface for TFT flat panels. LVDS can be used for many high-speed signaling applications. In this document, it refers only to TFT flat-panel applications. Most Significant Not Available No Connect National Television Standards Committee video broadcast standard used in North America Original Equipment Manufacturer Phase Alternating Line video broadcast standard used in many European countries. Parallel AT Attachment parallel interface standard for hard-disk drives also known as IDE, AT Attachment, and as ATA Personal Computer Advanced Technology an IBM trademark term used to refer to Intel x86 based personal computers in the 1990s Printed Circuit Board Peripheral Component Interface Peripheral Component Interface Express next-generation high speed Serialized I/O bus PCI Express Graphics Ethernet controller physical layer device A reference to one of six COM Express definitions for the signals that appear on the COM Express Module connector pins. Microsoft Plug-And-Play ID (PNP ID). This ID can be registered at the Microsoft web page ( free of charge. The PNP ID Format is XXX where 'A'<=X<='Z' Personal System 2 - an IBM trademark term used to refer to Intel x86 based personal computers in the 1990s. The term survives as a reference to the style of mouse and keyboard interface that were introduced with the PS2 system. Roughness Average a measure of surface roughness, expressed in units of length. Read Only Memory a legacy term often the device referred to as a ROM can actually be written to, in a special mode. Such writable ROMs are sometimes called Flash ROMs. BIOS is stored in ROM or Flash ROM. Real Time Clock battery backed circuit in PC-AT systems that keeps system time and date as well as certain system setup parameters Serial Attached SCSI high speed serial version of SCSI Small Computer System Interface an interface standard for high end disk drives and other computer peripherals Serial Presence Detect refers to serial EEPROM on DRAMs that has DRAM Module configuration information Serial Peripheral Interface Small Outline Dual In-line Memory Module System states describing the power and activity level S0 Full power, all devices powered S1 S2 S3 Suspend to RAM System context stored in RAM; RAM is in standby S4 Suspend to Disk System context stored on disk S5 Soft Off Main power rail off, only standby power rail present Serial AT Attachment: serial-interface standard for hard disks PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 11 of 84

12 Term SDVO SM Bus Super I/O TFT TMDS TPM USB VGA WDT XAUI Definition Serialized Digital Video Output Intel defined format for digital video output that can be used with Carrier Board conversion ICs to create parallel, TMDS, and LVDS flat-panel formats as well as NTSC and PAL TV outputs System Management Bus An integrated circuit, typically interfaced via the LPC bus that provides legacy PC I/O functions including PS2 keyboard and mouse ports, serial and parallel port(s) and a floppy interface. Thin Film Transistor refers to technology used in active matrix flat-panel displays, in which there is one thin film transistor per display pixel. Transition Minimized Differential Signaling - a digital signaling protocol between the graphics subsystem and display. TMDS is used for the DVI digital signals. Trusted Platform Module, chip to enhance the security features of a computer system. Universal Serial Bus Video Graphics Adapter PC-AT graphics adapter standard defined by IBM. Watch Dog Timer. 10 Gigabit / sec Attachment Unit Interface. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 12 of 84

13 1.7 Applicable Documents and Standards The following publications are used in conjunction with this standard. When any of the referenced specifications are superseded by an approved revision, that revision shall apply. All documents may be obtained from their respective organizations. Advanced Configuration and Power Interface Specification Revision 4.0, June 16, 2009 Copyright Compaq Computer Corporation, Intel Corporation, Microsoft Corporation, Phoenix Technologies Ltd., Toshiba Corporation. All rights reserved. ANSI/TIA/EIA-644-A-2001: Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, January 1, ANSI INCITS : AT Attachment with Packet Interface - 6 (ATA/ATAPI-6), November 1, ANSI INCITS : American National Standard for Information Technology Serial Attached SCSI (SAS), October 30, Audio Codec 97 Revision 2.3 Revision 1.0, April 2002 Copyright 2002 Intel Corporation. All rights reserved. download.intel.com/support/motherboards/desktop/sb/ac97_r23.pdf Display Data Channel Command Interface (DDC/CI) Standard (formerly DDC2Bi) Version 1, August 14, 1998 Copyright 1998 Video Electronics Standards Association. All rights reserved. ExpressCard Standard 2.0, June 2009 Copyright 2009 PCMCIA. All rights reserved. HDA - High Definition Audio Specification, Revision 1.0, April 15, 2004 Copyright 2002 Intel Corporation. All rights reserved. IEEE , IEEE Standard for Information technology, Telecommunications and information exchange between systems-local and metropolitan area networks-specific requirements Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications. IEEE 802.3ae (Amendment to IEEE ), Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, Amendment: Media Access Control (MAC) Parameters, Physical Layers, and Management Parameters for 10 Gb/s Operation. Intel Low Pin Count (LPC) Interface Specification Revision 1.1, August 2002 Copyright 2002 Intel Corporation. All rights reserved. PCI Express Base Specification Revision 2.0, December 20, 2006, Copyright PCI Special Interest Group. All rights reserved. PCI Express Card Electromechanical Specification Revision 2.0, April 11, 2007, Copyright PCI Special Interest Group. All rights reserved. PCI Local Bus Specification Revision 3.0, February 3, 2004 Copyright 1992, 1993, 1995, 1998, and 2004 PCI Special Interest Group. All rights reserved. PICMG Policies and Procedures for Specification Development, Revision 2.0, September 14, 2004, PCI Industrial Computer Manufacturers Group (PICMG ), 401 Edgewater Place, Suite 500, Wakefield, MA USA, Tel: , Fax: PICMG EAPI - Embedded Application Software Interface Specification, Revision 1.0, 2009, PCI Industrial Computer Manufacturers Group (PICMG ), 401 Edgewater Place, Suite 500, Wakefield, MA USA, Tel: , Fax: SDIO, Secure Digital Input/Output SD Specifications Part E1 SDIO Specification Version 2.00, February 8, 2007 Copyright 2007 SD Card Association DMTF SMBIOS - System Management BIOS Reference Specification Version PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 13 of 84

14 DMTF DMI - Desktop Management Interface Specification, Version 2.0.1s Serial ATA: High Speed Serialized AT Attachment Revision 1.0a January 7, 2003 Copyright , APT Technologies, Inc., Dell Computer Corporation, Intel Corporation, Maxtor Corporation, Seagate Technology LLC. All rights reserved. Smart Battery Data Specification Revision 1.1, December 11, System Management Bus (SMBus) Specification Version 2.0, August 3, 2000 Copyright 1994, 1995, 1998, 2000 Duracell, Inc., Energizer Power Systems, Inc., Fujitsu, Ltd., Intel Corporation, Linear Technology Inc., Maxim Integrated Products, Mitsubishi Electric Semiconductor Company, PowerSmart, Inc., Toshiba Battery Co. Ltd., Unitrode Corporation, USAR Systems, Inc. All rights reserved. USB 3.0 Specification, Revision 1.0, November 12, 2008, 2000 Copyright Hewlett-Packard Company, Intel Corporation,, Microsoft Corporation, NEC Corporation, ST-NXP Wireless and Texas Instruments. All rights reserved. SPI, Serial Peripheral Interface Bus Trusted Platform Module (TPM), Trusted Computing Group Specification 1.2 Revision 103, July 9, 2007, DisplayPort Standard Version High-Definition Multimedia Interface specification version Statement of Compliance Statements of compliance with this specification take the form specified in the PICMG Policies and Procedures for Specification Development: This product provides software support for PICMG EeeP Revision 1.0. Products making this simple claim of compliance must provide, at a minimum, all features defined in this specification as being mandatory by the use of the keyword shall in the body of the specification. Such products may also provide recommended features associated with the keyword should and permitted features associated with the keyword may as well. Because the specification provides for a number of recommended and permitted features beyond the mandatory minimum set and a wide range of performance Dynamic, more complete descriptions of product compliance are encouraged PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 14 of 84

15 2 General 2.1 Overview This specification was created to address 8 core issues. 1. Allow for Device Revision Identifiacation. 2. Allow standardized cross vendor cross platform I2C EEPROM Data storage and retrival. Specifically Product/Marketing/Branding information. 3. Allow for more flexible generic approach to data storage, sharing. 4. Facilitate Vendor specific data storage in a multi vendor enviroment. 5. Fascilitae the consolidataion of data curently stored in multiple discrete devices, into 1 device. E.G. PICMG EEPROM, OEM specific EEPROM, Display Device EEPROM. 6. Reduce the TCO for the PICMG EEPROM, for carrier and module vendors and oems. 1. Allow EEPROM consolidation. 2. Allow for maximum code reuse. 7. Reduce Manufacturing Cost, through allowing stanardized approach to system provisioning. 8. Improve EEPROM access characteristics and increase EEPROM device selection flexability. 2.2 Storage Conventions Multi-Byte Variables All Multi-Byte variables are stored in Big-endian(see page 10) unless otherwise stated. To facilitate easier architecture independent data access, all Multi byte variables are defined as byte arrays Structure Packing All structures are packed on byte boundaries. This means that alignment bytes should not be inserted by the compiler. See ' 9.1 EeeP.h' on page 66 for an example usage of the #pack pragma to achieve this. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 15 of 84

16 3 Detection 3.1 Detecting EeeP EEPROM High Level Check if(!memcmp( &EeePEEP[0x01], "3P", 0x02 ) ) { // Found EeeP EEPROM } C_SAMPLE 1: Detect COM0 R2.0 FRUPROM Sample I2C Transfer Device Address : 0xAE(0x57) Index Type : Extended Start<0x57><W>Ack<0x00>Ack<0x00>Ack Start<0x57><R>Ack<0xXX>Ack<'3'>Ack<'P'>Ack<'0x10'>Nak Stop XX is used to designate don't care, byte. 3.2 Detecting COM0 R1.0 EEPROM High Level Check if(!memcmp( &COM0EEP[0xE0], "COMExpressConfig", 0x10 ) ) { // Found COM0R10 EEPROM } C_SAMPLE 2: Detect COM0 R1.0 FRUPROM Sample I2C Transfer Device Address : 0xAE(0x57) Index Type : Standard PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 16 of 84

17 Start<0x57><W>Ack<0xE0>Ack Start<0x57><R>Ack<'C'>Ack<'O'>Ack<'M'>Ack<'E'>Ack<'x'>Ack<'p'>Ack <'r'>ack<'e'>ack<'s'>ack<'s'>ack<'c'>ack<'o'>ack <'n'>ack<'f'>ack<'i'>ack<'g'>nak Stop 3.3 Identifying Device Type Standard/Extended Index Sample I2C Transfer Device Address : 0xAE(0x57) Index Type : Unknown Start<0x57><W>Ack<0x00>Ack<0x01>Ack Start<0x57><R>Ack<'3'>Ack<'P'>Ack<'0x10'>Ack<'0xXX'>Ack<'DeviceDesc'>Nak Stop Standard Indexed Device With a Standard Indexed device the MSB of the Extended Index is used as the Complete Index and the LSB is written to the Don't care Byte of the EEPROM, causing an increment to the internal counter. Starting the Read operation at Device Offset 0x01.The Device Descriptor at offset 5 can then be used to interpret the Device correct method of device access Extended Indexed Device With an Extended Indexed device the Index is programed as normal. Starting the Read operation at Device Offset 0x0001. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 17 of 84

18 4 EEPROM Header Components. 4.1 Concepts There are multiple goals for an EEPROM header. One of the primary goals is to provide a mechanism for content Identification. This goal is achieved through inclusion of a header Id. A Secondary Goal is to provide information at fixed offsets. The purpose of providing information at fixed offsets is to allow for easier access. One of the costs of storing dynamic information in an EEPROM is that at an early system state it may not be convenient or possible to parse complex structures or hierarchies in order to extract information. To this extend it is advisable to segregate the information we wish to store in EEPROMs into 2 categories. Low Cost Access Information and Normal Cost Access Information. The Low Cost Access Information may be stored in the EEPROM Header. To Prevent Contention Header space is allocated in the following order. 1. EeeP Specific Header components. 2. Platform Specific Header Additions. 3. Vendor Specific Header Additions. 4.2 Common EeeP EEPROM Header typedef struct EeePCmn_s{ uint8_t DontCareByte;/ 0x00 Don't Care Byte The purpose of this Byte is to reduce the Damage Extended Index read access is used on a Standard Index Device uint8_t EepId[2] ; / 0x01 3P # define EEEP_EEPROM_MARKER "3P" uint8_t SpecRev ; / 0x03 EeeP Specification Revision uint8_t uint8_t }EeePCmn_t; EEP_HDR_C_STRUCT 1: Common EEPROM Header Description Standardized Header Entry point to allow for standardized Cross platform, Cross Vendor identification and access Header Elements BlkOffset ; / 0x04 Absolute Offset to First Dynamic Block in words(2 bytes) DeviceDesc ; / 0x05 Device Descriptor Dont Care Byte(DontCareByte) The purpose of this Byte is to reduce the the damage, if the incorrect access method is used on a standard EEPROM. I.E. extended Index read access is used to read from a Standard Index Device. In this scenario the second Command/Index byte is interpreted as a Data byte and is written to the MSB Index EEPROM ID(EepId) EEPROM Identifier. Defined as ASCII 3P. To allow for EEPROM Identification. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 18 of 84

19 EeeP Specification Revision(SpecRev) See 8.2 EEPROM Specification Revision. on page Block Offset(BlkOffset) Absolute offset from the start of the EEPROM to the first Dynamic Block. If 0 Dynamic Blocks Aren't supported. It is measured in units of 2 bytes Device Descriptor Byte(DeviceDesc) Table 4-1: Device Descriptor Byte Bits Description Values Meaning 5-7 Page Write Length/Alignment The Maximum number of internal low order address bits auto incremented on page writes 0 1 Byte 1 8 Bytes 2 16 Bytes 3 32 Bytes 4 64 Bytes Bytes Bytes Bytes 4 Standard/Extended Index 0 Standard Index/Command 0-3 Device Size Size 2^(8+n) Bytes (256 << n) Bytes Addressable Bytes Standard Index 8bit - 11Bit Extended Index 16bit - 19Bit 2048 KBit MBit 256 Bytes KBytes 1 Extended Index/Command 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D - 0x0F 256 Bytes 2 KBits 512 Bytes 4 KBits 1 KBytes 8 KBits 2 KBytes 16 KBits 4 KBytes 32 KBits 8 KBytes 64 KBits 16 KBytes 128 KBits 32 KBytes 256 Kbits 64 KBytes 512 Kbits 128 KBytes 1 Mbits 256 KBytes 2 Mbits 512 KBytes 4 Mbits Reserved 4.3 Universal Device Identifier Description typedef struct UDIdEep_s{ uint8_t VendId[2] ; / 0x06 Vendor Unique PNPID uint8_t DeviceId[2]; / 0x08 Vendor Specific Device ID uint8_t DeviceFlav ; / 0x0A Device Specific Flavor ID uint8_t RevId ; / 0x0B Device Specific Revision ID }UDIdEep_t; EEP_HDR_C_STRUCT 2: Universal Device Identifier Standardized block to create Unique Device Type Identifier. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 19 of 84

20 4.3.2 Block Elements Vendor ID(VendId) Compressed ASCII PNPID(see chapter 8.1 page 62) Device ID(DevId) Vendor Assigned 16Bit value to uniquely Identify all products. Stored In 'Big-endian' (see page 10) Device Flavor Vendor Assigned 8Bit value to distinguish product flavors I.E. to distinguish stuffing options Device Unique Revision ID Vendor Assigned Device Revision ID. No attempt is made here to give significance to this value. No assumptions should be made as to the meaning of this value, not even the assumption that higher digits mean newer product revisions. This is to allow for the complex nature of product revisions in the embedded market. See Table 4-2: Example Device Unique Revision IDs for examples. Table 4-2: Example Device Unique Revision IDs RID Board Revision PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 20 of 84

21 5 EEPROM Headers 5.1 COM0 R2.0 Carrier Board EEPROM Header typedef struct COM0R20_CB_s{ EeePCmn_t EeePHdr ; / 0x00 EeeP Common Header uint8_t GenId[4] ; / 0x06 "Com0" UDIdEep_t DevId ; / 0x0C Unique Device Id uint8_t CBType ; / 0x10 Carrier Board Type uint8_t SpecRev ; / 0x11 COM0 Specification Revision uint8_t UsbDesc ; / 0x12 USB Descriptor Byte uint8_t SasDesc; / 0x13 LAN Descriptor Byte uint8_t LanDesc; / 0x14 LAN Descriptor Byte uint8_t MiscIo1; / 0x15 Miscellaneous I/O Descriptor Byte 1 uint8_t MiscIo2; / 0x16 Miscellaneous I/O Descriptor Byte 2 uint8_t DDIDesc[2];/ 0x17 Digital Display Interface Descriptor Bytes uint8_t PCIeGen[8] ;/ 0x19 PCI Express Lane Generation uint8_t LaneMap[16];/ 0x21 PCI Express Lane Information }COM0R20_CB_t; Description Header For COM_0 Carrier Board EEPROM Header Elements EEP_HDR_C_STRUCT 3: COM0 R2.0 Carrier Board EEPROM Header EeePHdr Common EeeP EEPROM Header See ' 4.2 Common EeeP EEPROM Header' on page GenId COM0 Header Id to allow for identification of COM0 Carrier Board Specific Header Content. Case is used to distinguish Carrier Board headers from Module Headers DevId Unique Device Identifier. To allow Identification of COM0 Carrier Board. See ' 4.3 Universal Device Identifier' on page Carrier Board Type (CBType). COM_0 Carrier Board Type COM0 Specification Revision(SpecRev) COM_0 Specification Revision. See ' 8.2 EEPROM Specification Revision.' on page USB Descriptor Byte(UsbDesc) The configuration EEPROM shall use one byte to indicate how many USB ports the Carrier Board uses. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 21 of 84

22 Table 5-1: USB Descriptor Byte Bits Description Values Meaning 7 Reserved USB 3.0 Port Count. 0 No Ports Implemented 1 1 Port Implemented Ports Implemented 0-3 USB Port Count 0 No Ports Implemented 1 1 Port Implemented Ports Implemented PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 22 of 84

23 SATA / SAS Device Descriptor Byte(SasDesc) The configuration EEPROM shall use a byte to indicate how many SATA and SAS devices the Carrier Board uses, per the following table. Table 5-2: SATA / SAS Device Descriptor Byte Channel Number SATA / SAS Channel 4 Bit Description Values Meaning 7 Port Type 0 SATA Device 1 SAS Device 6 Port Implemented 0 Not Implemented 1 Implemented SATA / SAS Channel 3 5 Port Type 0 SATA Device 1 SAS Device 4 Port Implemented 0 Not Implemented 1 Implemented SATA / SAS Channel 2 3 Port Type 0 SATA Device 1 SAS Device 2 Port Implemented 0 Not Implemented 1 Implemented SATA / SAS Channel 1 1 Port Type 0 SATA Device 1 SAS Device 0 Port Implemented 0 Not Implemented 1 Implemented PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 23 of 84

24 LAN Descriptor Byte(LanDesc) The configuration EEPROM shall use one byte to indicate the LAN options used by the Carrier Board. 'Table 5-3: LAN Descriptor Byte' on page 24 shows the LAN Descriptor Byte definition. Table 5-3: LAN Descriptor Byte Description Bits Values Meaning Reserved 3-7 GBE Not Implemented 1 Implemented GBE Not Implemented 1 Implemented GBE Not Implemented 1 Implemented Miscellaneous I/O Descriptor Byte(MiscIo1) The configuration EEPROM shall use one byte to indicate usage by the Carrier Board of the following miscellaneous I/O signals. AC 97 / HDA Digital Interface Watchdog Timer External BIOS ROM Thermal Protection Battery Low Suspend Wake 'Table 5-4: Miscellaneous I/O Descriptor Byte' below shows the Miscellaneous I/O Descriptor Byte definition. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 24 of 84

25 Table 5-4: Miscellaneous I/O Descriptor Byte Feature/Function Bits Values Description AC 97 / HDA (AC/HD_ pins) Watchdog Timer (WDT) External BIOS ROM (BIOS_DISABLE#) Thermal Protection (THRM#, THERMTRIP#) Battery Low (BATLOW#) Suspend (SUS_ pins) Wake 1 (WAKE1#) Wake 0 (WAKE0#) 7 0 Not Implemented 1 Implemented 6 0 Not Implemented 1 Implemented 5 0 Not Implemented 1 Implemented 4 0 Not Implemented 1 Implemented 3 0 Not Implemented 1 Implemented 2 0 Not Implemented 1 Implemented 1 0 Not Implemented 1 Implemented 0 0 Not Implemented 1 Implemented Miscellaneous I/O Descriptor Byte 2(MiscIo2) The configuration EEPROM shall use one byte to indicate usage by the Carrier Board of the following miscellaneous I/O signals. SSC SD Card I/O Lid Switch Sleep Button Fan Serial Ports 0 and 1. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 25 of 84

26 Table 5-5: Miscellaneous I/O Descriptor Byte2 Feature/Function Bits Values Description Reserved 7 0 Reserved. Serial Port Not Implemented 1 Implemented Serial Port Not Implemented 1 Implemented FAN0 4 0 Not Implemented 1 Implemented Sleep Button 3 0 Not Implemented 1 Implemented Lid Switch 2 0 Not Implemented 1 Implemented SDIO on GPIO 1 0 Not Implemented 1 Implemented Spread Spectrum Clocking 0 0 Not Implemented 1 Implemented Digital Display Interface Descriptor Bytes(DDIDesc) The configuration EEPROM shall use two bytes to indicate the digital display interface connections supported. This byte is only used for Module Type 6 & 1. 'Table 5-6: Digital Display Interface Descriptor Byte1' below shows the Display Descriptor Byte definition. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 26 of 84

27 Table 5-6: Digital Display Interface Descriptor Byte1 DDI Port Byte Bits Values Description Reserved Reserved DDI Not Implemented 1 Embedded Display Port Implemented 2 Display Port Implemented 3 HDMI/DVI Implemented Reserved Reserved DDI Not Implemented 1 Embedded Display Port Implemented 2 Display Port Implemented 3 HDMI/DVI Implemented Reserved Reserved DDI Not Implemented 1 Embedded Display Port Implemented 2 Display Port Implemented 3 HDMI/DVI Implemented 4 SDVO Implemented 5-7 Reserved Reserved 3 0 Reserved DDI Not Implemented 1 Embedded Display Port Implemented 2 Display Port Implemented 3 HDMI/DVI Implemented 4 SDVO Implemented 5-7 Reserved Notes: further details about the type of video signals are beyond the scope and purpose of the configuration PCI Express Lane Generation Descriptor Data Structure(PCIeGen) Lane numbers 0 through 31 refer to the 32 possible COM Express lanes. Each COM Express connector PCI Express lane is allocated 2 bits to describe which PCI Express Generation is supported on the Carrier board. Table 5-7: PCI Express Lane Generation Descriptor Byte Bits Description Values Meaning Lane 31 0 Generation 1 1 Generation 2 2 Generation 3 3 Reserved Lane 0 0 Generation 1 1 Generation 2 2 Generation 3 3 Reserved PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 27 of 84

28 PCI Express Lane Descriptor Data Structure(LaneMap) Lane numbers 0 through 31 refer to the 32 possible COM Express lanes. Each COM Express connector PCI Express lane is allocated four bits to describe how the lanes are grouped on the Carrier Board to form PCI Express links. The 32 PCIe lanes are described in an array of 16 bytes, each lane using 4 bits. A lane is described by three bits indicating the width of the link it is part of, and a single bit defining the PCIe Generation of the link. This definition implies that the start lane of a link must be aligned at a boundary which is an integral multiple of the width of the link it is part of, e.g. a x4link can start only at lane no. 0,4,8,16,20,24, and 28. A link (along with its width and starting lane) can be decoded by inspecting the single Mapping Nibble of a lane which is part of the link. Figure "C_SAMPLE 3: Decode PCIe Link Width & Start Lane" on page 29 is showing this for lane 15.". Table 5-8: PCI Express Lane Descriptor Nibble Descriptor Bits Description Values Meaning 0-2 Link Width/Alignment 0 Not Implemented 1 x1 Link Width 2 x2 Link Width 3 x4 Link Width 4 x8 Link Width 5 x16 Link Width 6 x32 Link Width 7 Reserved 3 Reserved 0 Reserved. Table 5-9: PCI Express Valid Starting Lane Configurations Link Width Valid Starting Lane x1 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,... x2 0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30 x4 0,4,8,12,16,20,24,28 x8 0,8,16,24 x x32 0 PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 28 of 84

29 unsigned LaneIndex=15 // Example for Lane 15 unsigned ArrayIndex=LaneIndex/2 // 7 unsigned ByteShift =(LaneIndex&1)<<2 // Either 4, 0 unsigned EncLinkWidth =(LaneMapping[ArrayIndex]>>ByteShift)&0x7 if(enclinkwidth){ EncLinkWidth--; // Lane Used unsigned LinkWidth=1<<(EncLinkWidth) // 1,2,4,8,16,32 // The Following 3 lines Are equivalent // and are simply provided to aid in // understanding #if 0 unsigned StartingLane=(LaneIndex/LinkWidth)LinkWidth; #elseif 0 unsigned StartingLane=(LaneIndex>>EncLinkWidth)<<EncLinkWidth; #else unsigned StartingLane=LaneIndex&(~(LinkWidth - 1)); #endif } C_SAMPLE 3: Decode PCIe Link Width & Start Lane 5.2 COM0 R2.0 Module EEPROM Header typedef struct COM0R20_M_s{ EeePCmn_t EeePHdr ; / 0x00 EeeP Common Header uint8_t GenId[4] ; / 0x06 "com0" UDIdEep_t DevId ; / 0x0A Unique Device Id uint8_t MType ; / 0x10 Module Type uint8_t SpecRev ; / 0x11 COM0 Specification Revision }COM0R20_M_t; ; EEP_HDR_C_STRUCT 4: Module EEPROM Header Description Header For COM_0 Module EEPROMs Header Elements EeePHdr See ' 4.2 Common EeeP EEPROM Header' on page GenId COM0 Header Id to allow for identification of COM0 Module Specific Header Content. Case is used to distinguish Carrier Board headers from Module Headers DevId See ' 4.3 Universal Device Identifier' on page MType. COM_0 Module Type SpecRev COM0 Specification Revision. See ' 8.2 EEPROM Specification Revision.' on page 62. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 29 of 84

30 5.3 Expansion EEPROM Header typedef struct Exp_EEP_s{ EeePCmn_t EeePHdr ; / 0x00 EeeP Common Header uint8_t GenId[4] ; / 0x06 "EXP1" #define EEEP_EXP_HEADER_ID "EXP1" UDIdEep_t DevId ; / 0x06 Unique Device Id }Exp_EEP_t; EEP_HDR_C_STRUCT 5: Module EEPROM Header Description Skeleton Header For Expansion EEPROMs Header Elements EeePHdr See ' 4.2 Common EeeP EEPROM Header' on page GenId EXP1 Header Id to allow for identification of EeeP Expansion Specific Header Content DevId See ' 4.3 Universal Device Identifier' on page 19. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 30 of 84

31 6 Dynamic Descriptor Blocks. 6.1 Common Dynamic Block Header typedef struct DBlockIdHdr_s{ uint8_t DBlockId ; / 0x00 Dynamic Block Id uint8_t DBlockLength[2]; / 0x01 Block Length/ Offset to next Block in words (2 Bytes) }DBlockIdHdr_t; Description This is a method to allow dynamic reuse of a finite space. The theory is that different devices will wish to describe different features and that not all devices will wish to describe all features. Additional this allows for the fact that different devices may require different space to describe the same features. The mechanism is simple, it is in effect a linked list of descriptors. Each descriptor has an ID and and its own size., Blocks are defined as being contiguous. Once a starting point is defined it is possible to parse the link list to discover those block which if present configure or define the current operation. One of the most useful application of this mechanism is to allow for the optional description of complex topologies for express card slots. The goal of these link list systems is not to require dynamic generation but to allow dynamic parsing. It is valid to have vendor or platform specific fixed offset, wrapped with link list structures. At run time the EEPROM layout shall be viewed as Static. All changes to the EEPROM structure shall be immediately followed by a system restart. This is to allow for caching of EEPROM Offsets to reduce EEPROM access Overhead. EEPROM Layout shall only be modified in the context of either system maintenance or system manufacturing Block Elements CAP_C_STRUCT 1: Common Dynamic Block Header DBlockId Designates the Dynamic Block Type. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 31 of 84

32 Table 6-1: Dynamic Block Ids Id 0x00 0x01-0xBF 0xC0-0xCF 0xD0 0xD1 0xD2-0xDF 0xE0 0xE1 0xE2-0xEF 0xF0 0xF1 0xF2 0xF3-0xFE 0xFF Description unused Reserved Standard/Platform Specific Block SMBIOS Information Block. LFP Display Data (Virtual DDI EEPROM) Reserved Express Card Topology Serial Port Descriptor Reserved Vendor Specific Expansion EEPROM Descriptor CRC Reserved Unknown should be ignored DBlockLength Specifies the size of the current block in 2 byte increments. Stored in 'Big-endian' (see page 10). Table 6-2: Dynamic Block Length Values Offset Value Description 0x0000 End of list 0x0001 Reserved for future use 0x0002 Reserved for future use 0x0003-0xFFFE Current Block Size in 2 byte increments. 0xFFFF End of list Parse Order / Block Priority It is to be expected that there may be multiples instances of a block in a system. In order to prvide consistent behaviour for this situation the parse order is described here. The First Blocks encountered should have the higest Priority So taking a ComExpress System as an example.we firstly parse the Carrier Board EEPROM, and then the on Module EEPROM. Any Blocks on Expansion EEPROMS should parsed directly upon finding the Expansion EEPROM Descriptor. PICMG EEEP R1.0 Embedded EEPROM Specification, August 8, 2010 page 32 of 84