CSCI 402: Computer Architectures. Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI.
|
|
- Janice Hubbard
- 5 years ago
- Views:
Transcription
1 CSCI 402: Computer Architectures Instructions: Language of the Computer (3) Fengguang Song Department of Computer & Information Science IUPUI Recall Big endian, little endian Memory alignment Unsigned and signed integer representation 2s-complement: -x = x + 1 Sign extension (when copying to a longer register) R-format, I-format MIPS instructions A fixed size of 32 bits, or 4 bytes, or 1 word Bit-wise shift and logical operations Bitwise operations are common programming techniques 2 1
2 MIPS I-format Instructions op rs rt constant or offset address 6 bits 5 bits 5 bits 16 bits Immediate arithmetic operations Load/store operations rt: register number lw/sw $rt, 64($rs) Range of constants: 2 15 to Address: offset added to base address in rs Q: What part in the format would change if we increase #registers? addi $rt, $rs, 80 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits 3 Instruction Encoding: MIPS Instruction Examples $t0 $t7: reg s 8 15 $t8 $t9: $s0 $s7: reg s A few examples that can help you understand the format. 4 2
3 2/1/18 op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Registers MIPS bit GPRs (int registers) bit fp registers (dual use) R0=0 Additional special purpose registers Data types 8-bit byte 2 bytes = half word 4 bytes = word 8 bytes = dword Addressing modes Immediate and displacement register indirect and absolute are easily represented Byte addressable 64-bit address Big or littleendian Load/store architecture 5 tions 16 bits immediate words, words, dwords We ve seen arithmetic operations, bit-wise logical operations, and load/store. -They are computation-related code: a+b, a-b, a&b But how to support conditional statements in hardware? if ( ) { } else { } while() { } for(;;) { } How to support procedure calling in hardware? int main() { foo(); bar(); } foo() { do sth; return; } 8 ctions 3
4 How to Support Conditional Statements in the Hardware An example of C code: 5 variables int i, j; int f, g, h; if (i == j) { f = g + h; } else { f = g - h; } beq $s1, $s2, Label bne $s1, $s2, Label 9 Revisit the I-format Instructions op rs rt constant or offset address 6 bits 5 bits 5 bits 16 bits 1. Immediate arithmetic Range of constant: 2 15 to addi $s0, $s1, 80 lw/sw $s0, 64($s1) 3 rd type of usage 2. Load/store instructions rt: the destination register (for load) The offset address will be added to base address in rs Range of offset address: 2 15 to
5 beq $s1, $s2, Label bne $s1, $s2, Label Conditional Instructions instruction address op rs rt Address 6 bits 5 bits 5 bits 16 bits It is an I-format instruction Branch to a labeled instruction if condition is true Otherwise, execute the next instruction beq rs, rt, L1 if (rs == rt) branch to instruction labeled L1; bne rs, rt, L1 if (rs!= rt) branch to instruction labeled L1; 11 Compiling if Statements Previous C code: if (i==j) f = g+h; else f = g-h; i, j in $s3, $s4 f, g, h, in $s0, $s1, $s2, The compiled MIPS code: beq $s3, $s4, Then sub $s0, $s1, $s2 j Exit Then: add $s0, $s1, $s2 Exit: //f=g-h //f=g+h Assembler calculates the correct addresses 12 5
6 C code: Compiling a Loop $s3 $s6 $s5 while (array[i] == k) i += 1; array stores an array of words The compiled MIPS code: Loop: sll $t1, $s3, 2 //$t1 = i<<2 add $t1, $t1, $s6 //$t1 = array+ix4 lw $t0, 0($t1) //$t0 = array[i] bne $t0, $s5, Exit //check the condition addi $s3, $s3, 1 // i += 1; j Loop Exit: 13 Basic Blocks A basic block is a sequence of instructions with 1 entry point and 1 exit point. No embedded branches (except at end) That is, 1 exit point No branch targets (except at beginning) That is, 1 entry point n n A compiler identifies basic blocks for optimization An advanced processor can accelerate execution of basic blocks 14 6
7 Other Conditional Operations What about if (a<b)? In addition to: beq, bne slt rd, rs, rt Set result to 1 if the condition is true - Otherwise, set result to 0 - R type if (rs < rt) rd = 1; else rd = 0; slti rt, rs, constant if (rs < constant) rt = 1; else rt = 0; Use slt in combination with bne or beq slt $t0, $s1, $s2 # if ($s1 < $s2) bne $t0, $zero, L # branch to L 15 Branch Instruction Design beq, bne, but why not design blt, bge, etc? Reason: Hardware for <,, slower than =, So, if combine comparison with branch à involves more work per instruction à require a slower clock (then all following instructions penalized) Also, both slt and bne are common cases Two faster instructions are more useful than one slower instruction 16 7
8 Subtle Issues of Slt Q: 1xxxxxxx 2 vs 0xxxxxxx 2, which is it bigger? I don t know For signed integer comparison: slt, slti But, unsigned integer comparison: sltu, sltui For example: $s0 = $s1 = slt $t0, $s0, $s1 # signed integer 1 < +1 Þ $t0 = 1 sltu $t0, $s0, $s1 # unsigned integer +4,294,967,295 > +1 Þ $t0 = 0 17 Procedure Calling Procedure is used to structure programs Each procedure performs a specific task Works like a black box 6 Steps required to execute a procedure 1. Place parameters in registers 2. Transfer control to procedure 3. Allocate storage for procedure 4. Perform procedure s operations 5. Place result in register for caller 6. Return to place of call Caller vs Callee 18 8
9 Convention to Allocate Registers $a0 $a3: arguments (reg s 4 7) $v0, $v1: result values (reg s 2 and 3) $t0 $t9: temporaries OK to be overwritten by callee $s0 $s7: Saved to stack Must be saved/restored by callee $sp: stack pointer (reg 29) $fp: frame pointer (reg 30) $ra: return address (reg 31) low high 19 Procedure Call Instructions Procedure call: jump-and-link jal ProcedureName Puts address of the following instruction into $ra i.e., PC+4 Jump to target address Similar to a j(ump) instruction Procedure return: jump-register jr $ra Copies $ra to PC main: foo() foo: 22 9
10 Leaf Procedure Example A procedure that doesn t call others C code: int leaf_function (int g, h, i, j) { int f; f = (g + h) - (i + j); return f; } Arguments g, h, i, j are stored in $a0,, $a3 f uses $s0 (hence, need to save&restore $s0 on stack) Result in $v0 23 Leaf Procedure Example MIPS code: leaf_example: addi $sp, $sp, -4 sw $s0, 0($sp) add $t0, $a0, $a1 add $t1, $a2, $a3 sub $s0, $t0, $t1 add $v0, $s0, $zero lw $s0, 0($sp) addi $sp, $sp, 4 jr $ra Save $s0 on stack top low Procedure body Store result value Restore $s0 Return 24 high 10
11 Leaf Procedure Example MIPS code: leaf_example: addi $sp, $sp, -4 sw $s0, 0($sp) add $t0, $a0, $a1 add $t1, $a2, $a3 sub $s0, $t0, $t1 add $v0, $s0, $zero lw $s0, 0($sp) addi $sp, $sp, 4 jr $ra Save $s0 on stack top low Procedure body Store result value Restore $s0 Return 25 high Leaf Procedure Example MIPS code: leaf_example: addi $sp, $sp, -4 sw $s0, 0($sp) add $t0, $a0, $a1 add $t1, $a2, $a3 sub $s0, $t0, $t1 add $v0, $s0, $zero lw $s0, 0($sp) addi $sp, $sp, 4 jr $ra Save $s0 on stack top low Procedure body Store result value Restore $s0 Return 26 high 11
12 Non-Leaf Procedures Procedures that call other procedures For the special nested call, caller needs to save the following (on the stack): 1. Any arguments and temporaries needed after the call 2. Its return address (i.e., $ra=pc+4) Restore them from the stack after the call 27 Nested-Call Example Recursive C code: int fact (int n) { //compute n! if (n < 1) {//fact(0) = 1. return 1; } else { return n * fact(n - 1); } } Argument n in $a0 Result in $v
13 Non-Leaf Procedure Example MIPS code: fact: addi $sp, $sp, -8 # adjust stack for 2 items sw $ra, 4($sp) # push return address sw $a0, 0($sp) # push argument n slti $t0, $a0, 1 # test for n < 1 beq $t0, $zero, L1 addi $v0, $zero, 1 # if n<1, result is 1 addi $sp, $sp, 8 # pop 2 items from stack jr $ra # and return L1: addi $a0, $a0, -1 # if n >= 1, jal fact # recursive call lw $a0, 0($sp) # restore original n lw $ra, 4($sp) # restore return address main() { int n = 10; fact(n); printf(n); } 0 ->lw $a0 ->lw $a0 addi $sp, $sp, 8 # pop 2 items from stack mul $v0, $a0, $v0 # multiply to get result n jr $ra # and return main n-1 29 Byte and Halfword Operations MIPS has byte and halfword instructions 8 bits: 16 bits: lb rt, offset(rs) lh rt, offset(rs) Sign bit will extend to 32 bits in rt lbu rt, offset(rs) lhu rt, offset(rs) Zero will extend to 32 bits in rt sb rt, offset(rs) sh rt, offset(rs) Store just rightmost byte or halfword 32 13
14 32-bit constants Right now a constant has 16 bits If your code uses a constant that requires 32 bits, how to support it? E.g., b = a + 0x00_61_23_04 //addi cannot do it! Need lui and ori instructions to place the number to a register (see next slide) Then call add 33 Issue: How to Read 32-bit Constants and Addresses? I-format instructions: only 16 bits are used for constant To support occasional 32-bit constant? lui rt, constant //load upper immediate Copies a 16-bit constant to the left 16 bits of rt Clears right 16 bits of rt to 0 lui $s0, 0x0061 ori $s0, $s0, 0x
15 Homework 2 Book exercises: 2.4, 2.13, , 2.38, 2.41, 2.47 Due in two weeks Assigned on Feb 1, Thursday Due time: at 11:59:59pm on Feb 14, Wednesday night Submit an electronic copy to TA via Canvas No late submission is accepted 35 15
Chapter 2. Computer Abstractions and Technology. Lesson 4: MIPS (cont )
Chapter 2 Computer Abstractions and Technology Lesson 4: MIPS (cont ) Logical Operations Instructions for bitwise manipulation Operation C Java MIPS Shift left >>> srl Bitwise
More informationBranch Addressing. Jump Addressing. Target Addressing Example. The University of Adelaide, School of Computer Science 28 September 2015
Branch Addressing Branch instructions specify Opcode, two registers, target address Most branch targets are near branch Forward or backward op rs rt constant or address 6 bits 5 bits 5 bits 16 bits PC-relative
More informationMIPS R-format Instructions. Representing Instructions. Hexadecimal. R-format Example. MIPS I-format Example. MIPS I-format Instructions
Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register
More informationChapter 2. Instructions: Language of the Computer. Adapted by Paulo Lopes
Chapter 2 Instructions: Language of the Computer Adapted by Paulo Lopes Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing
More informationControl Instructions. Computer Organization Architectures for Embedded Computing. Thursday, 26 September Summary
Control Instructions Computer Organization Architectures for Embedded Computing Thursday, 26 September 2013 Many slides adapted from: Computer Organization and Design, Patterson & Hennessy 4th Edition,
More informationComputer Organization and Structure. Bing-Yu Chen National Taiwan University
Computer Organization and Structure Bing-Yu Chen National Taiwan University Instructions: Language of the Computer Operations and Operands of the Computer Hardware Signed and Unsigned Numbers Representing
More informationArchitecture II. Computer Systems Laboratory Sungkyunkwan University
MIPS Instruction ti Set Architecture II Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Making Decisions (1) Conditional operations Branch to a
More informationThomas Polzer Institut für Technische Informatik
Thomas Polzer tpolzer@ecs.tuwien.ac.at Institut für Technische Informatik Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq rs, rt, L1 if (rs == rt) branch to
More informationControl Instructions
Control Instructions Tuesday 22 September 15 Many slides adapted from: and Design, Patterson & Hennessy 5th Edition, 2014, MK and from Prof. Mary Jane Irwin, PSU Summary Previous Class Instruction Set
More informationChapter 2A Instructions: Language of the Computer
Chapter 2A Instructions: Language of the Computer Copyright 2009 Elsevier, Inc. All rights reserved. Instruction Set The repertoire of instructions of a computer Different computers have different instruction
More informationCOMPUTER ORGANIZATION AND DESIGN
COMPUTER ORGANIZATION AND DESIGN 5 th The Hardware/Software Interface Edition Chapter 2 Instructions: Language of the Computer 2.1 Introduction Instruction Set The repertoire of instructions of a computer
More informationMIPS Instruction Set Architecture (2)
MIPS Instruction Set Architecture (2) Jinkyu Jeong (jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu EEE3050: Theory on Computer Architectures, Spring 2017, Jinkyu
More informationLecture 2. Instructions: Language of the Computer (Chapter 2 of the textbook)
Lecture 2 Instructions: Language of the Computer (Chapter 2 of the textbook) Instructions: tell computers what to do Chapter 2 Instructions: Language of the Computer 2 Introduction Chapter 2.1 Chapter
More informationMachine Instructions - II. Hwansoo Han
Machine Instructions - II Hwansoo Han Conditional Operations Instructions for making decisions Alter the control flow - change the next instruction to be executed Branch to a labeled instruction if a condition
More informationInstructions: MIPS ISA. Chapter 2 Instructions: Language of the Computer 1
Instructions: MIPS ISA Chapter 2 Instructions: Language of the Computer 1 PH Chapter 2 Pt A Instructions: MIPS ISA Based on Text: Patterson Henessey Publisher: Morgan Kaufmann Edited by Y.K. Malaiya for
More informationChapter 2. Instructions: Language of the Computer
Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects in common Early computers
More informationComputer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.2: MIPS ISA -- Instruction Representation Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted from lectures on Computer Organization and Design,
More informationIntroduction to the MIPS. Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University
Introduction to the MIPS Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University Introduction to the MIPS The Microprocessor without Interlocked Pipeline Stages
More informationCS3350B Computer Architecture MIPS Instruction Representation
CS3350B Computer Architecture MIPS Instruction Representation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada
More informationCOMPSCI 313 S Computer Organization. 7 MIPS Instruction Set
COMPSCI 313 S2 2018 Computer Organization 7 MIPS Instruction Set Agenda & Reading MIPS instruction set MIPS I-format instructions MIPS R-format instructions 2 7.1 MIPS Instruction Set MIPS Instruction
More informationCOMP 303 Computer Architecture Lecture 3. Comp 303 Computer Architecture
COMP 303 Computer Architecture Lecture 3 Comp 303 Computer Architecture 1 Supporting procedures in computer hardware The execution of a procedure Place parameters in a place where the procedure can access
More informationCourse Administration
Fall 2017 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture 2/4 Avinash Kodi Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701 E-mail: kodi@ohio.edu
More informationcomp 180 Lecture 10 Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions
Outline of Lecture Procedure calls Saving and restoring registers Summary of MIPS instructions Procedure Calls A procedure of a subroutine is like an agent which needs certain information to perform a
More informationENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design
ENGN1640: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu School of Engineering Brown University Spring 2014 Sources: Computer
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the machine. Reduced number of cycles needed per instruction.
More informationCENG3420 Lecture 03 Review
CENG3420 Lecture 03 Review Bei Yu byu@cse.cuhk.edu.hk 2017 Spring 1 / 38 CISC vs. RISC Complex Instruction Set Computer (CISC) Lots of instructions of variable size, very memory optimal, typically less
More informationProcedure Calling. Procedure Calling. Register Usage. 25 September CSE2021 Computer Organization
CSE2021 Computer Organization Chapter 2: Part 2 Procedure Calling Procedure (function) performs a specific task and return results to caller. Supporting Procedures Procedure Calling Calling program place
More informationChapter 2. Instructions: Language of the Computer. HW#1: 1.3 all, 1.4 all, 1.6.1, , , , , and Due date: one week.
Chapter 2 Instructions: Language of the Computer HW#1: 1.3 all, 1.4 all, 1.6.1, 1.14.4, 1.14.5, 1.14.6, 1.15.1, and 1.15.4 Due date: one week. Practice: 1.5 all, 1.6 all, 1.10 all, 1.11 all, 1.14 all,
More informationReduced Instruction Set Computer (RISC)
Reduced Instruction Set Computer (RISC) Focuses on reducing the number and complexity of instructions of the ISA. RISC Goals RISC: Simplify ISA Simplify CPU Design Better CPU Performance Motivated by simplifying
More informationRechnerstrukturen. Chapter 2. Instructions: Language of the Computer
182.690 Rechnerstrukturen Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many
More informationChapter 2. Baback Izadi Division of Engineering Programs
Chapter 2 Baback Izadi Division of Engineering Programs bai@engr.newpaltz.edu Instruction Set Language of the Machine The repertoire of instructions of a computer Different computers have different instruction
More informationCharacter Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21
2.9 Communication with People: Byte Data & Constants Character Is a byte quantity (00~FF or 0~255) ASCII (American Standard Code for Information Interchange) Page 91, Fig. 2.21 32: space 33:! 34: 35: #...
More informationCS3350B Computer Architecture MIPS Introduction
CS3350B Computer Architecture MIPS Introduction Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada Thursday January
More informationMachine Language Instructions Introduction. Instructions Words of a language understood by machine. Instruction set Vocabulary of the machine
Machine Language Instructions Introduction Instructions Words of a language understood by machine Instruction set Vocabulary of the machine Current goal: to relate a high level language to instruction
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA
CISC 662 Graduate Computer Architecture Lecture 4 - ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationComputer Architecture. MIPS Instruction Set Architecture
Computer Architecture MIPS Instruction Set Architecture Instruction Set Architecture An Abstract Data Type Objects Registers & Memory Operations Instructions Goal of Instruction Set Architecture Design
More informationCISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization
CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer http://www.cis.udel.edu/~taufer/courses Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture,
More informationComputer Architecture Computer Science & Engineering. Chapter 2. Instructions: Language of the Computer BK TP.HCM
Computer Architecture Computer Science & Engineering Chapter 2 Instructions: Language of the Computer Computer Component 25-Aug-16 Faculty of Computer Science & Engineering 2 Instruction execution process
More informationCS3350B Computer Architecture
CS3350B Computer Architecture Winter 2015 Lecture 4.1: MIPS ISA: Introduction Marc Moreno Maza www.csd.uwo.ca/courses/cs3350b [Adapted d from lectures on Computer Organization and Design, Patterson & Hennessy,
More informationComputer Architecture
Computer Architecture Chapter 2 Instructions: Language of the Computer Fall 2005 Department of Computer Science Kent State University Assembly Language Encodes machine instructions using symbols and numbers
More informationComputer Architecture. The Language of the Machine
Computer Architecture The Language of the Machine Instruction Sets Basic ISA Classes, Addressing, Format Administrative Matters Operations, Branching, Calling conventions Break Organization All computers
More informationInstructions: Language of the Computer
Instructions: Language of the Computer Tuesday 22 September 15 Many slides adapted from: and Design, Patterson & Hennessy 5th Edition, 2014, MK and from Prof. Mary Jane Irwin, PSU Summary Previous Class
More informationChapter 2. Instructions: Language of the Computer. Jiang Jiang
Chapter 2 Instructions: Language of the Computer Jiang Jiang jiangjiang@ic.sjtu.edu.cn [Adapted from Computer Organization and Design, 4 th Edition, Patterson & Hennessy, 2008, MK] Chapter 2 Instructions:
More informationCSCI 402: Computer Architectures
CSCI 402: Computer Architectures Instructions: Language of the Computer (2) Fengguang Song Department of Computer & Information Science IUPUI Memory Operands Two tribes: Big Endian: Most-significant byte
More informationStored Program Concept. Instructions: Characteristics of Instruction Set. Architecture Specification. Example of multiple operands
Stored Program Concept Instructions: Instructions are bits Programs are stored in memory to be read or written just like data Processor Memory memory for data, programs, compilers, editors, etc. Fetch
More informationECE 331 Hardware Organization and Design. Professor Jay Taneja UMass ECE - Discussion 3 2/8/2018
ECE 331 Hardware Organization and Design Professor Jay Taneja UMass ECE - jtaneja@umass.edu Discussion 3 2/8/2018 Study Jams Leader: Chris Bartoli Tuesday 5:30-6:45pm Elab 325 Wednesday 8:30-9:45pm Elab
More informationChapter 2. Instructions: Language of the Computer
Chapter 2 Instructions: Language of the Computer Instruction Set The range of instructions of a computer Different computers have different instruction sets But with many aspects in common Early computers
More informationComputer Organization MIPS ISA
CPE 335 Computer Organization MIPS ISA Dr. Iyad Jafar Adapted from Dr. Gheith Abandah Slides http://www.abandah.com/gheith/courses/cpe335_s08/index.html CPE 232 MIPS ISA 1 (vonneumann) Processor Organization
More informationChapter 2. Instruction Set. The MIPS Instruction Set. Arithmetic Operations. Instructions: Language of the Computer
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 2 Instructions: Language of the Computer
More informationInstructions: Language of the Computer
CS359: Computer Architecture Instructions: Language of the Computer Yanyan Shen Department of Computer Science and Engineering 1 The Language a Computer Understands Word a computer understands: instruction
More information1/26/2014. Previously. CSE 2021: Computer Organization. The Load/Store Family (1) Memory Organization. The Load/Store Family (2)
CSE 202: Computer Organization Lecture-4 Code Translation-2 Memory, Data transfer instructions, Data segment,, Procedures, Stack Shakil M. Khan (adapted from Prof. Roumani) Previously Registers $s0 - $s7,
More informationMIPS Instruction Set
MIPS Instruction Set Prof. James L. Frankel Harvard University Version of 7:12 PM 3-Apr-2018 Copyright 2018, 2017, 2016, 201 James L. Frankel. All rights reserved. CPU Overview CPU is an acronym for Central
More informationECE 154A Introduction to. Fall 2012
ECE 154A Introduction to Computer Architecture Fall 2012 Dmitri Strukov Lecture 4: Arithmetic and Data Transfer Instructions Agenda Review of last lecture Logic and shift instructions Load/store instructionsi
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 2. Instructions: Language of the Computer
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers
More informationCS/COE1541: Introduction to Computer Architecture
CS/COE1541: Introduction to Computer Architecture Dept. of Computer Science University of Pittsburgh http://www.cs.pitt.edu/~melhem/courses/1541p/index.html 1 Computer Architecture? Application pull Operating
More informationProcedure Call Instructions
Procedure Calling Steps required 1. Place parameters in registers x10 to x17 2. Transfer control to procedure 3. Acquire storage for procedure 4. Perform procedure s operations 5. Place result in register
More informationCENG3420 L03: Instruction Set Architecture
CENG3420 L03: Instruction Set Architecture Bei Yu byu@cse.cuhk.edu.hk (Latest update: January 31, 2018) Spring 2018 1 / 49 Overview Introduction Arithmetic & Logical Instructions Data Transfer Instructions
More informationLecture 5: Procedure Calls
Lecture 5: Procedure Calls Today s topics: Memory layout, numbers, control instructions Procedure calls 1 Memory Organization The space allocated on stack by a procedure is termed the activation record
More informationInstructions: Assembly Language
Chapter 2 Instructions: Assembly Language Reading: The corresponding chapter in the 2nd edition is Chapter 3, in the 3rd edition it is Chapter 2 and Appendix A and in the 4th edition it is Chapter 2 and
More informationPreviously. CSE 2021: Computer Organization. Memory Organization. The Load/Store Family (1) 5/26/2011. Used to transfer data to/from DRAM.
CSE 2021: Computer Organization Lecture-4 Code Translation-2 Memory, Data transfer instructions, Data segment,, Procedures, Stack Shakil M. Khan (adapted from Profs. Roumani & Asif) Previously Registers
More informationChapter 2. Instructions: Language of the Computer
Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects in common Early computers
More informationCOMPUTER ORGANIZATION AND DESIGN. 5 th Edition. The Hardware/Software Interface. Chapter 2. Instructions: Language of the Computer
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers
More informationInstruction Set. The MIPS Instruction Set. Chapter 2
COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface 5 th Edition 1 Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers
More informationInstruction Set Architecture
Computer Architecture Instruction Set Architecture Lynn Choi Korea University Machine Language Programming language High-level programming languages Procedural languages: C, PASCAL, FORTRAN Object-oriented
More informationChapter 2. Instructions: Language of the Computer
Chapter 2 Instructions: Language g of the Computer Outlines Introduction to MIPS machine Operations of the Computer HW Operands of the Computer HW Representing instructions in the Computer Logical Operations
More informationLecture 5: Procedure Calls
Lecture 5: Procedure Calls Today s topics: Procedure calls and register saving conventions 1 Example Convert to assembly: while (save[i] == k) i += 1; i and k are in $s3 and $s5 and base of array save[]
More informationAll instructions have 3 operands Operand order is fixed (destination first)
Instruction Set Architecture for MIPS Processors Overview Dr. Arjan Durresi Louisiana State University Baton Rouge, LA 70803 durresi@csc.lsu.edu These slides are available at: http://www.csc.lsu.edu/~durresi/_07/
More informationEE 361 University of Hawaii Fall
C functions Road Map Computation flow Implementation using MIPS instructions Useful new instructions Addressing modes Stack data structure 1 EE 361 University of Hawaii Implementation of C functions and
More informationChapter 2: Instructions:
Chapter 2: Instructions: Language of the Computer Computer Architecture CS-3511-2 1 Instructions: To command a computer s hardware you must speak it s language The computer s language is called instruction
More informationELEC / Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2)
ELEC 5200-001/6200-001 Computer Architecture and Design Fall 2013 Instruction Set Architecture (Chapter 2) Victor P. Nelson, Professor & Asst. Chair Vishwani D. Agrawal, James J. Danaher Professor Department
More informationCourse Administration
Fall 2018 EE 3613: Computer Organization Chapter 2: Instruction Set Architecture Introduction 4/4 Avinash Karanth Department of Electrical Engineering & Computer Science Ohio University, Athens, Ohio 45701
More informationComputer Architecture Instruction Set Architecture part 2. Mehran Rezaei
Computer Architecture Instruction Set Architecture part 2 Mehran Rezaei Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a MIPS Interpreter
More informationToday s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.
Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic
More informationChapter 2. Instructions: Language of the Computer. Baback Izadi ECE Department
Chapter 2 Instructions: Language of the Computer Baback Izadi ECE Department bai@engr.newpaltz.edu Instruction Set Language of the Machine The repertoire of instructions of a computer Different computers
More informationChapter 2. Instructions: Language of the Computer
Chapter 2 Instructions: Language of the Computer Instruction Set The repertoire of instructions of a computer Different computers have different instruction sets But with many aspects in common Early computers
More informationCS3350B Computer Architecture MIPS Procedures and Compilation
CS3350B Computer Architecture MIPS Procedures and Compilation Marc Moreno Maza http://www.csd.uwo.ca/~moreno/cs3350_moreno/index.html Department of Computer Science University of Western Ontario, Canada
More informationEN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design
EN164: Design of Computing Systems Topic 03: Instruction Set Architecture Design Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown
More informationECE260: Fundamentals of Computer Engineering
Accessing and Addressing Memory James Moscola Dept. of Engineering & Computer Science York College of Pennsylvania Based on Computer Organization and Design, 5th Edition by Patterson & Hennessy American
More informationMIPS%Assembly% E155%
MIPS%Assembly% E155% Outline MIPS Architecture ISA Instruction types Machine codes Procedure call Stack 2 The MIPS Register Set Name Register Number Usage $0 0 the constant value 0 $at 1 assembler temporary
More informationCS222: MIPS Instruction Set
CS222: MIPS Instruction Set Dr. A. Sahu Dept of Comp. Sc. & Engg. Indian Institute of Technology Guwahati 1 Outline Previous Introduction to MIPS Instruction Set MIPS Arithmetic's Register Vs Memory, Registers
More informationECE232: Hardware Organization and Design. Computer Organization - Previously covered
ECE232: Hardware Organization and Design Part 6: MIPS Instructions II http://www.ecs.umass.edu/ece/ece232/ Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Computer Organization
More informationEEM 486: Computer Architecture. Lecture 2. MIPS Instruction Set Architecture
EEM 486: Computer Architecture Lecture 2 MIPS Instruction Set Architecture EEM 486 Overview Instruction Representation Big idea: stored program consequences of stored program Instructions as numbers Instruction
More information101 Assembly. ENGR 3410 Computer Architecture Mark L. Chang Fall 2009
101 Assembly ENGR 3410 Computer Architecture Mark L. Chang Fall 2009 What is assembly? 79 Why are we learning assembly now? 80 Assembly Language Readings: Chapter 2 (2.1-2.6, 2.8, 2.9, 2.13, 2.15), Appendix
More informationOverview. Introduction to the MIPS ISA. MIPS ISA Overview. Overview (2)
Introduction to the MIPS ISA Overview Remember that the machine only understands very basic instructions (machine instructions) It is the compiler s job to translate your high-level (e.g. C program) into
More informationComputer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: MIPS Instruction Set Architecture
Computer Science 324 Computer Architecture Mount Holyoke College Fall 2009 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture. Idea:
More informationECE468 Computer Organization & Architecture. MIPS Instruction Set Architecture
ECE468 Computer Organization & Architecture MIPS Instruction Set Architecture ECE468 Lec4.1 MIPS R2000 / R3000 Registers 32-bit machine --> Programmable storage 2^32 x bytes 31 x 32-bit GPRs (R0 = 0) 32
More informationECE369. Chapter 2 ECE369
Chapter 2 1 Instruction Set Architecture A very important abstraction interface between hardware and low-level software standardizes instructions, machine language bit patterns, etc. advantage: different
More informationMips Code Examples Peter Rounce
Mips Code Examples Peter Rounce P.Rounce@cs.ucl.ac.uk Some C Examples Assignment : int j = 10 ; // space must be allocated to variable j Possibility 1: j is stored in a register, i.e. register $2 then
More informationThe MIPS Instruction Set Architecture
The MIPS Set Architecture CPS 14 Lecture 5 Today s Lecture Admin HW #1 is due HW #2 assigned Outline Review A specific ISA, we ll use it throughout semester, very similar to the NiosII ISA (we will use
More informationInstruction Set Architecture part 1 (Introduction) Mehran Rezaei
Instruction Set Architecture part 1 (Introduction) Mehran Rezaei Overview Last Lecture s Review Execution Cycle Levels of Computer Languages Stored Program Computer/Instruction Execution Cycle SPIM, a
More informationLectures 3-4: MIPS instructions
Lectures 3-4: MIPS instructions Motivation Learn how a processor s native language looks like Discover the most important software-hardware interface MIPS Microprocessor without Interlocked Pipeline Stages
More informationAssembly Language Programming. CPSC 252 Computer Organization Ellen Walker, Hiram College
Assembly Language Programming CPSC 252 Computer Organization Ellen Walker, Hiram College Instruction Set Design Complex and powerful enough to enable any computation Simplicity of equipment MIPS Microprocessor
More informationChapter 2. Instructions:
Chapter 2 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control flow Very restrictive e.g., MIPS Arithmetic Instructions We ll be working with
More informationEEC 581 Computer Architecture Lecture 1 Review MIPS
EEC 581 Computer Architecture Lecture 1 Review MIPS 1 Supercomputing: Suddenly Fancy 2 1 Instructions: Language of the Machine More primitive than higher level languages e.g., no sophisticated control
More informationCS 61C: Great Ideas in Computer Architecture. MIPS Instruction Formats
CS 61C: Great Ideas in Computer Architecture MIPS Instruction Formats Instructor: Justin Hsia 6/27/2012 Summer 2012 Lecture #7 1 Review of Last Lecture New registers: $a0-$a3, $v0-$v1, $ra, $sp Also: $at,
More informationMIPS function continued
MIPS function continued Review Functions Series of related instructions one after another in memory Called through the jal instruction Pointed to by a label like any other Returns by calling Stack Top
More informationTopic Notes: MIPS Instruction Set Architecture
Computer Science 220 Assembly Language & Comp. Architecture Siena College Fall 2011 Topic Notes: MIPS Instruction Set Architecture vonneumann Architecture Modern computers use the vonneumann architecture.
More informationComputer Organization and Design
Computer Organization and Design The Hardware/Software Interface Chapter 2 - Introductions: Language of the Computer Dr. Feng Li fli@sdu.edu.cn https://funglee.github.io 1 Contents of Chapter 2 l 2.1 Introduction
More informationInstruction Set Architecture of. MIPS Processor. MIPS Processor. MIPS Registers (continued) MIPS Registers
CSE 675.02: Introduction to Computer Architecture MIPS Processor Memory Instruction Set Architecture of MIPS Processor CPU Arithmetic Logic unit Registers $0 $31 Multiply divide Coprocessor 1 (FPU) Registers
More information