Fig. 6-1 Conventional and Array Logic Symbols for OR Gate

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1 6- (a) Conventional symbol (b) Array logic symbol Fig. 6- Conventional and Array Logic Symbols for OR Gate 2 Prentice Hall, Inc.

2 6-2 k address lines Read n data input lines emory unit 2 k words n bits per word n data output lines Fig. 6-2 Block Diagram of emory 2 Prentice Hall, Inc.

3 6-3 emory address Binary Decimal emory contents Fig. 6-3 Contents of a 24 6 emory 2 Prentice Hall, Inc.

4 6-4 TABLE 6- Control Inputs to a emory Chip Chip CS Read/ R/W emory operation None to ed word Read from ed word Table 6- Control Inputs to a emory Chip 2 Prentice Hall, Inc.

5 6-5 2 ns Clock T T2 T3 T4 T Address Address valid emory enable Read/ Data input Data valid 75 ns 2 ns (a) cycle Clock T T2 T3 T4 T Address Address valid emory enable Read/ Data output Data valid (b) Read cycle Fig. 6-4 emory Cycle Timing Waveforms 2 Prentice Hall, Inc. 65 ns

6 6-6 Select B S Q C B R Q C Fig. 6-5 Static RA Cell 2 Prentice Hall, Inc.

7 Select 6-7 Word B S Q C B R Q C Word Word 2 n Select S R Q Q Word Word 2 n Read/ logic Data in S R Q Q Data in Read/ Data out Bit (b) Symbol logic Read/ Bit Read logic Data out (a) Logic diagram 2 Prentice Hall, Inc. Fig. 6-6 RA Bit Slice odel

8 6-8 A 3 A 3 4 to 6 Decoder 2 3 Word 2 A 2 A A 2 A A Data input 6 x RA Data output A Read/ 4 5 emory enable (a) Symbol Read/ logic Data input Data in Read/ Data out Bit Data output Read/ Chip (b) Block diagram Fig Word by -Bit RA Chip 2 Prentice Hall, Inc.

9 6-9 IN EN OUT EN IN OUT Hi-Z (a) Logic symbol Fig. 6-8 Three-state Buffer (b) Truth table 2 Prentice Hall, Inc.

10 6- EN EN IN IN OL Hi-Z (S) IN EN OL (S) (S) IN (S) EN (a) Logic Diagram (b) Truth table Fig. 6-9 Three-state Buffers Forming a ultiplexed Line OL 2 Prentice Hall, Inc.

11 6- A 3 Row decoder 2 to 4 Decoder 2 A Row Read/ logic Read/ logic Read/ logic Read/ logic Data in Data out Data in Data out Data in Data out Data in Data out Read/ Bit Read/ Bit Read/ Bit Read/ Bit Data input Read/ Column 2 3 Data output Column decoder 2 to 4 Decoder with enable 2 2 Enable A A Chip 2 Prentice Hall, Inc. Fig. 6- Diagram of a 6 RA Using a 4 4 RA Cell Array

12 6-2 A 2 A Row decoder 2 to 4 Decoder Row Read/ logic Read/ logic Read/ logic Read/ logic Data in Data out Data in Data out Data in Data out Data in Data out Read/ Bit Read/ Bit Read/ Bit Read/ Bit Data input Data input Read/ Column decoder 2 Prentice Hall, Inc. Fig. 6- Block Diagram of an 8 2 RA Using a 4 4 RA Cell Array A Column to 2 Decoder with enable 2 Enable Chip Data output Data output

13 6-3 Select B T C Select (a) D (b) (c) B D Q C (d) (e) C D model (h) (f) (g) Fig. 6-2 Dynamic RA Cell, Hydraulic Analogy of Cell Operation, and Cell odel 2 Prentice Hall, Inc.

14 6-4 Refresh controller Refresh counter Row address RAS Row address register Row timing logic Row decoder DRA bit slice DRA bit slice DRA bit slice CAS R/W OE Column address Column timing Logic Column address register Input/Output Logic Column decoder Data in/data out Fig. 6-3 Block Diagram of a DRA Including Refresh Logic 2 Prentice Hall, Inc.

15 6-5 Word Select B D Q C C D model Word D Word Word 2 n Select D Q Word 2 n D C D model D Read/ logic Data in Sense amplifier Data in Read/ Data out Bit (b) Symbol logic Read/ Bit Read logic Data out (a) Logic diagram 2 Prentice Hall, Inc. Fig. 6-4 DRA Bit Slice odel

16 6-6 Clock 2 ns T T2 T3 T4 T Address Row Address Column Address RAS CAS Output enable Read/ Data input 2 ns Data valid 75 ns (a) cycle Clock T T2 T3 T4 T Address Row Address Column Address RAS CAS Output enable Read/ Data output Hi-Z Data valid 65 ns (b) Read cycle Fig. 6-5 Timing for DRA and Read Operations 2 Prentice Hall, Inc.

17 6-7 64K x 8 RA Input data 8 DATA 8 Output data Address 6 ADRS Chip CS Read/ R/W Fig. 6-6 Symbol for a 64K 8 RA Chip 2 Prentice Hall, Inc.

18 6-8 Address Lines Lines Input data 8 emory enable EN 3 2 to 4 decoder 2 64K x 8 RA DATA ADRS CS Read/ R/W -65,535 64K x 8 RA DATA ADRS CS R/W 65,536-3,7 64K x 8 RA DATA ADRS CS R/W 3,72-96,67 64K x 8 RA DATA ADRS CS 8 R/W 96,68-262,43 Output data Fig. 6-7 Block Diagram of a 256K 8 RA 2 Prentice Hall, Inc.

19 6-9 6 input data lines 8 8 Address 6 64K x 8 RA 64K x 8 RA Chip Read/ 8 6 DATA ADRS CS R/W DATA 6 ADRS CS R/W output data lines Fig. 6-8 Block Diagram of a 64K 6 RA 2 Prentice Hall, Inc.

20 6-2 k inputs (address) 2 k x n RO n outputs (data) Fig. 6-9 Block Diagram of RO 2 Prentice Hall, Inc.

21 6-2 I I I 2 I 3 I 4 5 to 32 decoder A 7 A 6 A 5 A 4 A 3 A 2 A A Fig. 6-2 Internal Logic of a 32 8 RO 2 Prentice Hall, Inc.

22 2 Prentice Hall, Inc TABLE 6-2 RO Truth Table (Partial) Inputs Outputs I 4 I 3 I 2 I I A 7 A 6 A 5 A 4 A 3 A 2 A A Table 6-2 RO Truth Table (Partial)

23 6-23 I I I 2 I 3 I 4 5 to 32 decoder Fuse intact Fuse blown A 7 A 6 A 5 A 4 A 3 A 2 A A Fig. 6-2 Programming the RO According to Table Prentice Hall, Inc.

24 2 Prentice Hall, Inc TABLE 6-3 Truth Table for Circuit of Example 6- Inputs Outputs A 2 A A B 5 B 4 B 3 B 2 B B Decimal Table 6-3 Truth Table for Circuit of Example 6-

25 6-25 A A A 2 8 x 4 RO B B B 2 B 3 B 4 A 2 A A B 5 B 4 B 3 B 2 B 5 (a) Block diagram (b) RO truth table Fig RO Implementation of Example 6-2 Prentice Hall, Inc.

26 6-26 Inputs Fixed AND array (decoder) Programmable Connections Programmable OR array Outputs (a) Programmable read-only memory (PRO) Inputs Programmable Connections Programmable AND array Fixed OR array Outputs (b) Programmable array logic (PAL) device Inputs Programmable Connections Programmable AND array Programmable Connections Programmable OR array Outputs (c) Programmable logic array (PLA) device Fig Basic Configuration of Three PLDs 2 Prentice Hall, Inc.

27 6-27 A B C AB 2 AC Fuse intact Fuse blown 3 BC 4 ABC C C B B A A F F 2 Fig PLA with Three Inputs, Four Product Terms, and Two Outputs 2 Prentice Hall, Inc.

28 6-28 TABLE 6-4 Programming Table for the PLA in Figure 6-24 Inputs Outputs Product term A B C (T) F (C) F 2 AB AC BC ABC Table 6-4 Programming Table for the PLA in Figure Prentice Hall, Inc.

29 6-29 BC A B BC A B A A C C F = AB + AC + BC F = AB + AC + BC F 2 = AB + AC + ABC F 2 = AC + AB + ABC PLA programming table Outputs Product term Inputs A B C (C) F (T) F 2 AB AC 2 BC 3 ABC 4 Fig Solution to Example Prentice Hall, Inc.

30 6-3 Product term AND gates inputs F 3 I 4 5 F 2 I F 3 I 3 9 F 4 I Fig PAL Device with Four Inputs, Four Outputs, and a Three-wide AND-OR Structure 2 Prentice Hall, Inc.

31 6-3 TABLE 6-5 PAL Programming Table for Example 6-3 Product term AND Inputs A B C D W Outputs W Y Z ABC + ABCD A + BCD AB + CD + BD W + ACD + ABCD Table 6-5 PAL Programming Table for Example Prentice Hall, Inc.

32 6-32 AND gates inputs Product term A A B B C C D D W W 2 W 3 A 4 5 B 6 7 All fuses intact (always = ) 8 Y C 9 Z D 2 Fuse intact Fuse blown A A B B C C D D W W Fig Connection ap for PAL Device for Example Prentice Hall, Inc.

33 6-33 I/O control block Logic array block Logic array block Logic array block Logic array block Programmable interconnect array I/O control block Logic array block Logic array block Logic array block Logic array block Logic array block Logic array block Logic array block Logic array block I/O control block Logic array block Logic array block Logic array block Logic array block I/O control block Fig Altera A 7 Structure (Reprinted with Permission of Altera Corporation, Altera Corp., 99) 2 Prentice Hall, Inc.

34 6-34 Single length Long lines - Input/Output Block (IOB) - Configurable logic block (CLB) - Switch matrix Fig ilinx C4 FPGA Structure (Adapted with Permission of ilinx, Inc.) 2 Prentice Hall, Inc.

35 6-35 G S D (a) Pass transistor control U S A B C F(A, B, C) (b) ultiplexer control (c) Look up table implementation Fig. 6-3 SRA Bit Use in ilinx FPGAs 2 Prentice Hall, Inc.

36 (a) Switch atrix Transistors (b) Examples of Connections Fig. 6-3 Example of ilinx Switch atrix (Adapted with Permission of ilinx, Inc.) 2 Prentice Hall, Inc.

37 6-37 G G2 G3 Look up Table for G' G' H DIN S/R EC U G4 6 bits of SRA Look up Table for H' H' DIN F' G' H' S S/R Control U D PRE EC CLR YQ F F2 F3 Look up Table for F' 8 bits of SRA F' U G' H' S U S Y F4 K (CLOCK) 6 bits of SRA DIN F' G' H' S S/R Control U D PRE EC CLR Q U F' H' S S - S Fig Simplified Diagram of a ilinx Configurable Logic Block 2 Prentice Hall, Inc. (Adapted with permission of ilinx, Inc.)

38 6-38 Three-state TS Output Data O FPGA Interior PRE D CLR OUTPUT I/O PIN Input Data PRE D Input Data 2 CLR INPUT Fig Sketch of ilinx IOB Structure (Adapted with Permission of ilinx, Inc.) 2 Prentice Hall, Inc.

I 4 I 3 I 2 I 1 I 0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 T-125. ROM Truth Table (Partial) 1997 by Prentice-Hall, Inc.

I 4 I 3 I 2 I 1 I 0 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 T-125. ROM Truth Table (Partial) 1997 by Prentice-Hall, Inc. 997 by Prentice-Hall, Inc. ano & Kime Upper Saddle River, New Jersey 7458 T-5 Inputs Outputs I 4 I 3 I I I A 7 A 6 A 5 A 4 A 3 A A A...... RO Truth Table (Partial) 997 by Prentice-Hall, Inc. ano & Kime

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