IT T35 Digital system desigm y - ii /s - iii
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1 UNIT - V Introduction to Verilog Hardware Description Language Introduction HDL for combinational circuits Sequential circuits Registers and counters HDL description for binary multiplier. 5.1 INTRODUCTION TO HDL Ref: Morris Mano M. and Michael D. Ciletti, Digital Design, IV Edition, Pearson Education, Pg.No:159. In electronics, a hardware description language or HDL is any language from a class of computer languages and/or programming languages for formal description of digital logic and electronic circuits. HDLs are used to write executable specifications of some piece of hardware. A simulation program, designed to implement the underlying semantics of the language statements, coupled with simulating the progress of time, provides the hardware designer with the ability to model a piece of hardware before it is created physically HDL MODELS OF COMBINATIONAL CIRCUITS. The Verilog HDL model of a combinational circuit can be described in any one of the following modeling styles, Gate level modeling-using instantiations of predefined and user defined primitive gates. Dataflow modeling using continuous assignment with the keyword assign. Behavioral modeling using procedural assignment statements with the keyword always. Gate level modeling In this type, a circuit is specified by its logic gates and their interconnections. Gate level modeling provides a textual description of a schematic diagram. The verilog HDL includes 12 basic gates as predefined primitives. They are and, nand, or, nor, xor, xnor, not & buf. J. Veerendeswari /IT/RGCET Page 1
2 Dataflow modeling Dataflow modeling of combinational logic uses a number of operators that act on operands to produce desired results. Verilog HDL provides about 30 different operators. Dataflow modeling uses continuous assignments and the keyword assign. A continuous assignment is a statement that assigns a value to a net. The data type family net is used to represent a physical connection between circuit elements. HDL for 2-to-4 line decoder J. Veerendeswari /IT/RGCET Page 2
3 Behavioral modeling Behavioral modeling represents digital circuits at a functional and algorithmic level. It is used mostly to describe sequential circuits, but can also be used to describe combinational circuits. Behavioral descriptions use the keyword always, followed by an optional event control expression and a list of procedural assignment statements SEQUENTIAL CIRCUITS Ref: Morris Mano M. and Michael D. Ciletti, Digital Design, IV Edition, Pearson Education, Pg.No:225. We saw in the combinational circuits section how to design a combinational circuit from the given problem. We convert the problem into a truth table, then draw K-map for the truth table, and then finally draw the gate level circuit for the problem. Similarly we have a flow for the sequential circuit design. The steps are given below. Draw state diagram. Draw the state table (excitation table) for each output. Draw the K-map for each output. Draw the circuit. State Diagram -The state diagram is constructed using all the states of the sequential circuit in question. It builds up the relationship between various states and also shows how inputs affect the states. Let s consider designing the 2 bit up counter (Binary counter is one which counts a binary sequence) using the T flip-flop. J. Veerendeswari /IT/RGCET Page 3
4 State Table - The state table is the same as the excitation table of a flip-flop, i.e. what inputs need to be applied to get the required output. In other words this table gives the inputs required to produce the specific outputs. Q1 Q0 Q1+ Q0+ T1 T K-map -The K-map is the same as the combinational circuits K-map. Only difference: we draw K-map for the inputs i.e. T1 and T0 in the above table. From the table we deduct that we don't need to draw K- map for T0, as it is high for all the state combinations. But for T1 we need to draw the K-map as shown below, using SOP. Circuit- There is nothing special in drawing the circuit, it is the same as any circuit drawing from K- map output. Below is the circuit of 2-bit up counter using the T flip-flop. VHDL Operators Highest precedence first, left to right within same precedence group, use parenthesis to control order. Unary operators take an operand on the right. "result same" means the result is the same as the right operand. Binary operators take an operand on the left and right. "result same" means the result is the same as the left operand. J. Veerendeswari /IT/RGCET Page 4
5 ** exponentiation, numeric ** integer, result numeric abs absolute value, abs numeric, result numeric not complement, not logic or boolean, result same * multiplication, numeric * numeric, result numeric / division, numeric / numeric, result numeric mod modulo, integer mod integer, result integer rem remainder, integer rem integer, result integer + unary plus, + numeric, result numeric - unary minus, - numeric, result numeric + addition, numeric + numeric, result numeric - subtraction, numeric - numeric, result numeric & concatenation, array or element & array or element, result array sll shift left logical, logical array sll integer, result same srl shift right logical, logical array srl integer, result same sla shift left arithmetic, logical array sla integer, result same sra shift right arithmetic, logical array sra integer, result same rol rotate left, logical array rol integer, result same ror rotate right, logical array ror integer, result same = test for equality, result is boolean /= test for inequality, result is boolean < test for less than, result is boolean <= test for less than or equal, result is boolean > test for greater than, result is boolean >= test for greater than or equal, result is Boolean and logical and, logical array or boolean, result is same or logical or, logical array or boolean, result is same nand logical complement of and, logical array or boolean, result is same nor logical complement of or, logical array or boolean, result is same xor logical exclusive or, logical array or boolean, result is same xnor logical complement of exclusive or, logical array or boolean, result is same VHDL for Serial Comparator Things to observe: 1. Flip-flop implementation: reset priority, event, rising edge sensitive. 2. If and case -- sequential statements -- are valid only within a process. J. Veerendeswari /IT/RGCET Page 5
6 3. Concurrent assignment is a ``process.'' 4. Semantics of a process: sensitivity list, assignments: 5. b <= a; 6. c <= b; does not behave as it would in C. 7. VHDL architecture broken into three processes: 1. State storage. 2. Next state generation. 3. Output generation. Compare process inputs to sensitivity lists. -- VHDL for serial comparator. The inputs a and b are input lsb first. -- The Mealy machine uses rising edge sensitive flip-flops and an -- asynchronous active low reset The output is 1 if b > a, otherwise 0. library ieee; use ieee.std_logic_1164.all; entity comparator is port (a, b, clk, reset : in std_logic; o : out std_logic ); end comparator; J. Veerendeswari /IT/RGCET Page 6
7 architecture process_defn of comparator is -- Two states needed. type state_type is (S0, S1); -- State assignment. attribute enum_encoding : string; attribute enum_encoding of state_type : type is "0 1"; signal state, next_state : state_type; -- For convenience, concatenate a and b. signal inputs : std_logic_vector (1 downto 0); begin -- Concurrent assignment executes the rhs changes. -- Concatenate a and b into inputs. inputs <= a & b; -- Processes execute whenever something on their sensitivity list -- changes. All assignments take place when the process exits This process implements the D flip-flop. state_register : process (clk, reset) begin -- If/else construct only valid within a process. if (reset = '0') then state <= S0; elsif (clk'event AND clk = '1') then state <= next_state; end process; -- This process computes the next state. next_state_process : process (inputs, state) begin case state is when S0 => if (inputs = "01") then next_state <= S1; else next_state <= S0; when S1 => if (inputs = "10") then next_state <= S0; else next_state <= S1; end case; J. Veerendeswari /IT/RGCET Page 7
8 end process; -- This process computes the output. output_process : process (inputs, state) begin case state is when S0 => if (inputs = "01") then o <= '1'; else o <= '0'; when S1 => if (inputs = "10") then o <= '0'; else o <= '1'; end case; end process; end process_defn; A test bench is a virtual environment used to verify the correctness or soundness of a design or model (e.g., a software product). The term has its roots in the testing of electronic devices, where an engineer would sit at a lab bench with tools of measurement and manipulation, such as oscilloscopes, multimeters, soldering irons, wire cutters, and so on, and manually verify the correctness of the device under test. In the context of software or firmware or hardware engineering, a test bench refers to an environment in which the product under development is tested with the aid of a collection of testing tools. Often, though not always, the suite of testing tools is designed specifically for the product under test. J. Veerendeswari /IT/RGCET Page 8
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